# migrations

dir: embeddings_queue
filename: 00001-embeddings.sqlite.sql
hash: d3755dfd232be8e8301f4d7fcfb3a486
sql:
CREATE TABLE embeddings_queue (
    seq_id INTEGER PRIMARY KEY,
    created_at TIMESTAMP NOT NULL DEFAULT CURRENT_TIMESTAMP,
    operation INTEGER NOT NULL,
    topic TEXT NOT NULL,
    id TEXT NOT NULL,
    vector BLOB,
    encoding TEXT,
    metadata TEXT
);


dir: sysdb
filename: 00001-collections.sqlite.sql
hash: 38352d725ad1c16074fac420b22b4633
sql:
CREATE TABLE collections (
    id TEXT PRIMARY KEY,
    name TEXT NOT NULL,
    topic TEXT NOT NULL,
    UNIQUE (name)
);

CREATE TABLE collection_metadata (
    collection_id TEXT REFERENCES collections(id) ON DELETE CASCADE,
    key TEXT NOT NULL,
    str_value TEXT,
    int_value INTEGER,
    float_value REAL,
    PRIMARY KEY (collection_id, key)
);


dir: sysdb
filename: 00002-segments.sqlite.sql
hash: 2913cb6a503055a95f625448037e8912
sql:
CREATE TABLE segments (
    id TEXT PRIMARY KEY,
    type TEXT NOT NULL,
    scope TEXT NOT NULL,
    topic TEXT,
    collection TEXT REFERENCES collection(id)
);

CREATE TABLE segment_metadata (
    segment_id TEXT  REFERENCES segments(id) ON DELETE CASCADE,
    key TEXT NOT NULL,
    str_value TEXT,
    int_value INTEGER,
    float_value REAL,
    PRIMARY KEY (segment_id, key)
);


dir: sysdb
filename: 00004-tenants-databases.sqlite.sql
hash: 048867ce8fcdefe4023c7110e4433591
sql:
CREATE TABLE IF NOT EXISTS tenants (
    id TEXT PRIMARY KEY,
    UNIQUE (id)
);

CREATE TABLE IF NOT EXISTS databases (
    id TEXT PRIMARY KEY, -- unique globally
    name TEXT NOT NULL, -- unique per tenant
    tenant_id TEXT NOT NULL REFERENCES tenants(id) ON DELETE CASCADE,
    UNIQUE (tenant_id, name) -- Ensure that a tenant has only one database with a given name
);

CREATE TABLE IF NOT EXISTS collections_tmp (
    id TEXT PRIMARY KEY, -- unique globally
    name TEXT NOT NULL, -- unique per database
    topic TEXT NOT NULL,
    dimension INTEGER,
    database_id TEXT NOT NULL REFERENCES databases(id) ON DELETE CASCADE,
    UNIQUE (name, database_id)
);

-- Create default tenant and database
INSERT OR REPLACE INTO tenants (id) VALUES ('default_tenant'); -- The default tenant id is 'default_tenant' others are UUIDs
INSERT OR REPLACE INTO databases (id, name, tenant_id) VALUES ('00000000-0000-0000-0000-000000000000', 'default_database', 'default_tenant');

INSERT OR REPLACE INTO collections_tmp (id, name, topic, dimension, database_id)
    SELECT id, name, topic, dimension, '00000000-0000-0000-0000-000000000000' FROM collections;
DROP TABLE collections;
ALTER TABLE collections_tmp RENAME TO collections;


dir: metadb
filename: 00001-embedding-metadata.sqlite.sql
hash: 2b4cf52c4bb2676e21d6860a4409f856
sql:
CREATE TABLE embeddings (
    id INTEGER PRIMARY KEY,
    segment_id TEXT NOT NULL,
    embedding_id TEXT NOT NULL,
    seq_id BLOB NOT NULL,
    created_at TIMESTAMP NOT NULL DEFAULT CURRENT_TIMESTAMP,
    UNIQUE (segment_id, embedding_id)
);

CREATE TABLE embedding_metadata (
    id INTEGER REFERENCES embeddings(id),
    key TEXT NOT NULL,
    string_value TEXT,
    int_value INTEGER,
    float_value REAL,
    PRIMARY KEY (id, key)
);

CREATE TABLE max_seq_id (
    segment_id TEXT PRIMARY KEY,
    seq_id BLOB NOT NULL
);

CREATE VIRTUAL TABLE embedding_fulltext USING fts5(id, string_value);


dir: metadb
filename: 00002-embedding-metadata.sqlite.sql
hash: 12a570f7121b3a8ce750a2a7c36da20f
sql:
-- SQLite does not support adding check with alter table, as a result, adding a check
-- involve creating a new table and copying the data over. It is over kill with adding
-- a boolean type column. The application write to the table needs to ensure the data
-- integrity.
ALTER TABLE embedding_metadata ADD COLUMN bool_value INTEGER


dir: metadb
filename: 00003-full-text-tokenize.sqlite.sql
hash: f97ad6334aeaa8f419f01110b648b97a
sql:
CREATE VIRTUAL TABLE embedding_fulltext_search USING fts5(string_value, tokenize='trigram');
INSERT INTO embedding_fulltext_search (rowid, string_value) SELECT rowid, string_value FROM embedding_metadata;
DROP TABLE embedding_fulltext;


# embeddings_queue

created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_add_mapped_instance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.add_mapped_instance.txt", "chroma:document": "add_mapped_instance\nAdd mapped instance pair between REF and IMP\nUsage: add_mapped_instance($ref_instance, $imp_instance);\nExamples:\n  add_mapped_instance(\"u_subtop/u_def/state_reg\", \"u_subtop/uinst_def/state_reg\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_buffer.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.buffer.txt", "chroma:document": "buffer\nECO command. Buffer high fanout ECO nets\nUsage: buffer($net_names, $buffer_name, $fanout);\n$net_names: Net names to be buffered. Use \",\" to separate multiple nets, like \"eco1_net1,reset2\"\n$buffer_name: The buffer module name from library, leave it blank to let the tool pick one.\n              It supports repeater case by \",\", for example, \"INVX1,INVX16\" would have 'INVX1'\n              drives 'INVX16' and 'INVX16' drives the fanouts.\n$fanout: How many fanout to insert a buffer.\n\nExamples:\n\n#1. For every 10 fanout of test_mode, add a buffer, BUFX6\nbuffer(\"test_mode\", \"BUFX6\", 10); \n\n#2. For every 10 fanout of 'clock', add repeaters, INVX2,INVX16\nbuffer(\"clock\", \"INVX2,INVX16\", 10);\n\n#3. Let the tool pick a buffer\nbuffer(\"clock\", \"\", 10);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_change_gate.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.change_gate.txt", "chroma:document": "change_gate\nECO command. Modify an instance in ECO\nTwo types of usages\nUsage1: change_gate($instance, $new_reference, $pin_mapping);\n$instance: The instance under ECO. Support hierarchical name, \"u_abc/U123\"\n$new_reference: The new reference name which the instance changes to, E.G. 'AND3X1'. \n                If no reference is present, the ECO operation is assumed to \n                  change the instance's pin connections.\n$pin_mapping: Input pins mapping, \".new(old)\", E.G. \".A1(A),.B1(B)\"\n              if two references have same input pins. The option can be empty\nUsage2: change_gate($instance, $pin_connections);\n$pin_connections: New pin connections, \".A(n242)\".\n                  The unspecified pins keeps the original connection.\n                  E.G. pin 'B' connection is unchanged.\n\nExamples:  \n\n#1. U123 has reference OR3X1 with input pins, A,B,C originally\n# change U123 to AND3X1, all input pins are the same.\nchange_gate('U123', 'AND3X1', \"\"); \n\n#2. A and B keep the connections, discard C\nchange_gate('U123', 'AND2X1', \"\");\n\n#3. A keeps the connections, B connects to what the old C connects. And discard old B\nchange_gate('U123', 'AND2X1', \".B(C)\"); \n\n#4. A,B,C keep the same, and new D pin connects to net n123\nchange_gate('U123', 'AND4X1', \".D(n123)\"); \n\n#5. AO21X1 has input pins, A0, A1 and B0 \nchange_gate('U123', 'AO21X1', \".A0(A),.A1(B),.B0(C)\");\n\n#6. change U123 A to n123, B to n124, keep C connection. \nchange_gate(\"U123\", \".A(n123),.B(n124)\"); \n\n#7. Rotating A/B/C connections.\nchange_gate(\"U123\", \".A(B),.B(C),.C(A)\"); \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_change_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.change_net.txt", "chroma:document": "change_net\nECO command. Change a existing net's driver\nUsage: change_net($net, $gate, $instance, $connections);\n$net: The net to be ECOed\n$gate: New leaf gate to drive the net\n$instance: The instance name of the new gate. Optional, if it is empty, assigned by the tool\n$connections:  The new gate input pins connections. If it is empty, the gate is inserted in the net\n   Supported formats, 1. Very detail  \".A(net0),.B(net1),.C(net2)\"\n                      2. Connect to the pins in alphabetical sequence \n                          \"net1,net0,net2\" indicating A->net1,B->net0,C->net2\n                      3. Other instance/pin \"U408/Y,U409/Y,net2\" indicating A->U408/Y,B->U409/Y,C->net2\n                      4. Special character '-' is used to connect up the original connection\n\nExamples:\n\n#1. Drive n123 with BUFX2 driven by n40\nchange_net(\"n123\", \"BUFX2\", \"\", \"n40\");   \n\n#2. Drive n123 with AND2X2 driven by n40 and original n123 driver\nchange_net(\"n123\", \"AND2X2\", \"\", \"-,n40\");    \n\n#3. Insert a buffer into n123\nchange_net(\"n123\", \"BUFX2\");   \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_change_pin.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.change_pin.txt", "chroma:document": "change_pin\nECO command. Modify pin connection of instances by inserting gates, changing connection to other signal (LLM: change pin insert gate)\nTwo types of usages. \n\nUsage1: change_pin($pin_name, $net);\nChange pin's connection to a net\n$pin_name: In the format of \"instance/pin\", can be more than one pins separated by \",\",\n             \"instance1/pinA,instance2/pinB\", E.G. \"U123/A\", \"U123/A,U345/B\"\n             Hierarchical naming style is supported as well, \"u_abc/U123/A\"\n             The pins have to be input in this mode.\n$net: The net name the pin connects to.\n      Hierarchical naming style is supported, \"u_abc/net123\"\n      When the pin and the net are in different hierarchies, ports are added automatically\n      E.G. \n      # The tool creates 4 ports across the hierarchies to connect the net to the pin.\n      change_pin(\"u_abc/u_cde/U200/A\", \"u_xyz/u_stv/net300\");\n      # The tool gets the net tie to Y pin of U300 and do the the same as the previous example.\n      change_pin(\"u_abc/u_cde/U200/A\", \"u_xyz/u_stv/U300/Y\");\n\nUsage2:my $inst = change_pin($pin_name, $leaf_cell, $new_instance, $connection);\nInsert a new leaf cell to drive the pin\n$inst: Return new instance name if new gate is created in the command.\n$pin_name: In the format of \"instance/pin\", E.G. U123/A  Hierarchical naming is supported, u_abc/U123/A\n           The pin can be output in this mode. The tool gets the net the pin drives,\n             and change the command to \n             change_net($thenet, $leaf_cell, $new_instance, $connection);\n$leaf_cell: The leaf cell name to drive the $pin_name\n$new_instance: The instance name for the new inserted leaf cell. \n               The option is optional, the tool assigns one if it's empty\n               If use '.', the instance is added to the same hierarchy as the $pin_name\n$connection: The pins connection for the new cell. \n   Supported formats, 1. Detail format:  \".A(net0),.B(net1),.C(net2)\"\n                      2. Simple format: Connect to the pins in alphabetical sequence \"net1,net0,net2\"\n                      3. Mixed format: \"u_abc/U123/Y,.B(net1),net2\"\n                      4. Special character '-' is used to connect up the original connection\n                      5. Advanced nesting format: \n                         change_pin(\"U189/A\", \"AOI21X2\", \"\", \"U190/Y,,BUFX6(BUFX6(BUFX6(n412)))\");\n\nNote: All strings should be quoted by ' or \" to avoid syntax error or undesired effects.\n     \n\nExamples:\n\n#1. U123 has input pins A,B,C, U234 has input pins A0,A1,B\n# Change A pin of U123 to net12345\nchange_pin(\"U123/A\", \"net12345\"); \n\n#2. Change A pin of U123 to $net which is defined in the ECO script.\nchange_pin(\"U123/B\", $net); \n\n#3. Change A pin of U123 to net12345\nchange_pin(\"U123/A,U234/B\", \"net12345\");\n\n#4. Insert \"NAND2X2 eco12345_U0(.A(net1234),.B(net5678));\"\n# to drive U123/A\nchange_pin(\"U123/A\", \"NAND2X2\", \"eco12345_U0\", \"net1234,net5678\"); \n\n#5. Same as above, with more detail of pin connections\nchange_pin(\"U123/A\", \"NAND2X2\", \"eco12345_U0\", \".A(net1234),.B(net5678)\"); \n\n#6.Insert a buffer to U123 A pin\nchange_pin(\"U123/A\", \"BUFX4\", \"\", \"-\"); \n\n#7. Insert NAND2X1 to drive CK pin and new A connects to the original net\nchange_pin(\"abc_reg_1_/CK\", \"NAND2X1\", \"\", \".A(-),.B(1'b1)\"); \n\n#8. Do hierarchical connection\nchange_pin(\"u_abc/u_cde/U200/A\", \"u_xyz/u_stv/U300/Y\"); \n\n#9. Nested connection\nchange_pin(\"qcif/num2/u_spare1/B\", \"AOI21X2\", \"eco_inst_on_top1\", \\\n           \"NAND2X2(gte_344/u_smod/U100/Y, gte_344/n114), gte_343/U111, BUFX6(BUFX6(n105))\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_change_port.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.change_port.txt", "chroma:document": "change_port\nECO command. Change an output port's driver, or add gate after input port \nUsage1: change_port($port, $gate, $instance, $connections);\n$port: The port under ECO, can be input port or output port\n$gate: New leaf gate to drive the port if the port is output\n       Or add the gate after input port\n$instance: The instance name for the new leaf cell, optional, the tool assigns one if it's empty\n$connections: The new gate input pins connections. If it is empty, the gate is inserted in the net\n   Supported formats, 1. Very detail  \".A(net0),.B(net1),.C(net2)\"\n                      2. Connect to the pins in alphabetical sequence \n                          \"net1,net0,net2\" indicating A->net1,B->net0,C->net2\n                      3. Other instance/pin \"U408/Y,U409/Y,net2\" indicating A->U408/Y,B->U409/Y,C->net2\n                      4. Special character '-' is used to connect up the original connection\nUsage2: change_port($port, $inst_pin);\n$port: The port under ECO, output port\n$inst_pin: In the format of 'u1234/Y', instance-name/pin-name\nNote: The difference of change_net and change_port command\n      change_net changes all drains of the net.\n      change_port changes only the port driver.\n\nExamples:\n\n#1. Add buffer to output port 'out1'\nchange_port(\"out1\", \"BUFX1\", \"eco_buf0\", \"-\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_check_design.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.check_design.txt", "chroma:document": "check_design\nCheck if the netlist status, searching for unresolved modules, floating and multi-drivers \nUsage: check_design(@options);\n@options:\n   -ignore list: Ignore the issues matching the list, E.G. 'FE_UNCONNECT*,SCAN_*'. \n   -eco: Only check instances/wires having been done ECO. Default check all instances/wires\n   -fixfile filename: Create ECO fix file\n   -nouniquify: Dont check uniquify\n\nExamples:\n\ncheck_design;\ncheck_design('-ignore', 'FE_UNCONNECT*');\ncheck_design('-ignore', 'FE_UNCONNECT*,SCAN_*');\ncheck_design('-ignore', 'W-108');\ncheck_design(\"-eco\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_compare.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.compare.txt", "chroma:document": "compare\nLogic equivalence check on output port and register input pins\nUsage: my $no_eq_num = compare(@nets, @options);\n@options:\n   -help: Print this info\n$no_eq_num: Return back non-equivalent number\n\nExamples:\n\n#1. Check if output port 'state_out' is equivalent in IMP/REF netlists\ncompare(\"state_out\");\n\n#2. Check two points at the same time.\n    Check if 'state_reg_0_/D' is equivalent in IMP/REF netlists\n    And check if 'state_reg_1_/D' are equivalent in IMP/REF netlists\ncompare(\"state_reg_0_/D\", \"state_reg_1_/D\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_compare_nets.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.compare_nets.txt", "chroma:document": "compare_nets\nCheck equivalence of two nets in the reference and implementation netlist\nUsage: my $result = compare_nets($net0, $net1, @options);\n$net0: The net in the reference netlist.\n$net1: The net in the implementation netlist.\n@options:\n$result: 1, they are equal, \n         0, they are not equal.\n\nExamples:\n\n#1 Compare reg1/D in the reference and reg1/D in the implementation netlist\ncompare_nets(\"reg1/D\", \"reg1/D\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_convert_gated_clocks.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.convert_gated_clocks.txt", "chroma:document": "convert_gated_clocks\nECO command. Convert gated clocks to MUX logic.\nIn metal ECO, if gated clock cell is not in spare gate list, this command should run before map_spare_cells\nUsage: my $cnt = convert_gated_clocks();\n$cnt: The number of gated clock cells having been converted\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_create_clock.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.create_clock.txt", "chroma:document": "create_clock\nTiming command and GOF Formal command. Create clock for fault verification\nUsage: create_clock($clock_name, $clock_period);\n$clock_name: Clock name, input port name or black box instance output pin\n$clock_period: Clock period\n\nNote: This command can be used multiple times. The clock period is recommended to be multiples of 2\n\nExamples:\n\n#1. Create clock on PIN_SPI_CLK, period 4ns\ncreate_clock(\"PIN_SPI_CLK\", 4);\n\n#2. Create clock on PIN_APB_CLK and PLL clk_out\ncreate_clock(\"PIN_APB_CLK\", 2);\ncreate_clock(\"u_pll_top/u_pll_core/clk_out\", 2);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_create_pin_mapping_json_file.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.create_pin_mapping_json_file.txt", "chroma:document": "create_pin_mapping_json_file\nCreate pin mapping file between original synthesis netlist and pre-ECO netlist\nUsage: create_pin_mapping_json_file($filename);\n$filename: JSON file name\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_create_reset.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.create_reset.txt", "chroma:document": "create_reset\nCreate reset for the design\nUsage: create_reset($reset_name, $active_level);\n$reset_name: Reset name, input port name or black box instance output pin\n$active_level: The level that the reset is active\n\nExamples:\n\n#1. Create reset on PIN_RESETN, active low\ncreate_reset(\"PIN_RESETN\", 0);\n\n#2. Create reset on PIN_RESET, active high\ncreate_reset(\"PIN_RESET\", 1);\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_current_design.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.current_design.txt", "chroma:document": "current_design\nSet the current top level module (LLM: current design module)\nUsage: current_design($module);\n$module: Set $module as the current top level module.\n         If the argument is missing, return the current setting\n         \"..\" set to parent module, \"~\" set to the most top level module \nNote: It can be reset to the root top module by 'undo_eco'. It is alias command of 'set_top'\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_current_instance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.current_instance.txt", "chroma:document": "current_instance\nSet the current instance, alias of 'set_inst'\nUsage: current_instance($instance);\n$instance: Set $instance as the current instance.\n         If the argument is missing, return the current setting\n         \"..\" set to parent module, \"~\" set to the most top level module \nNote: It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_del_gate.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.del_gate.txt", "chroma:document": "del_gate\nECO command. Delete gate\nUsage: del_gate($inst);\n$inst: The instance to be deleted.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_del_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.del_net.txt", "chroma:document": "del_net\nECO command. Delete net\nUsage: del_net($net);\n$net: The net to be deleted.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_del_port.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.del_port.txt", "chroma:document": "del_port\nECO command. Delete port\nUsage: del_port($port);\n$port: The port to be deleted.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_dft_drc.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.dft_drc.txt", "chroma:document": "dft_drc\nDFT DRC checker\nUsage: my $error = dft_drc(@options);\n$error: DRC errors in the checker\n@options:\n    -single: One clock for each scan chain\n    -glitch: Check reset/set pin glitch\n\nExamples:\n\n#1. Run full DFT DRC\ndft_drc;\n#2. One clock for each scan chain in DRC\ndft_drc(\"-single\");\n#3. Check reset/set pin glitch\ndft_drc(\"-glitch\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_elaborate.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.elaborate.txt", "chroma:document": "elaborate\nElaborate and compile RTL files\nUsage: elaborate();\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_elab_rtl.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.elab_rtl.txt", "chroma:document": "elab_rtl\nElaborate on RTL design\nUsage: elab_rtl();\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_exist_inst.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.exist_inst.txt", "chroma:document": "exist_inst\nCheck if an instance exists (LLM: instance existence)\nUsage:my $ret = exist_inst($inst);\n$inst: The instance for checking\n$ret: 1, the instance exists 0, the instance does not exist\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_exist_wire.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.exist_wire.txt", "chroma:document": "exist_wire\nCheck if a wire exists (LLM: wire existence)\nUsage:my $ret = exist_wire($wire);\n$wire: The wire name for checking\n$ret: 1: exists 0: not exist\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_find_equal_nets.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.find_equal_nets.txt", "chroma:document": "find_equal_nets\nFind equivalent nets in IMP for the listed nets in REF, the results are printed out on the screen\nUsage: find_equal_nets(@ref_nets);\noptions: (\"help\",\"full=i\")\n   -help: Print this info\n\nExamples:\n\n#1. Find IMP equal nets for 'mbist_done', 'sync_start' in REF\nfind_equal_nets('mbist_done', 'sync_start');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_fix_design.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.fix_design.txt", "chroma:document": "fix_design\nECO command to fix the design in automatic ECO (LLM: automatic eco)\nUsage: fix_design(@options);\n@options:\n    -help: Print this information\n    -opt_set optimization_set: Patch optimization set, 0: area/timing 1: cell count, default 0\n    -no_patch_opt: Disable patch optimization. Also see API set_no_patch_opt\n    -flatten: Enable flatten mode ECO. The default mode is hierarchical\n    -list_file the_list_file: The ECO point list file converted from RTL-to-RTL LEC result\n             The list file format:\n                inst u_def/u_sdef/state_reg_1_\n                pin  u_control/u_sreg/u_mem_128x24/A[0]\n                port PORT_READY_OUT\n    -iteration iteration_number: Fix design iteration by default 3 times.\n          The tool repeats the fix process until there is no non-equivalent points or iteration number reached\nExamples:\n\n#1. Fix design on module 'VIDEO_TOP' and its sub-modules\nset_top('VIDEO_TOP');\nset_ignore_output(\"TEST_SO*\");\nset_pin_constant(\"TEST_EN\", 0);\nfix_design;\nsave_session(\"this_eco\");\nmy $error = LEC;\n\n#2. Do ECO in flatten mode\nfix_design(\"-flatten\");\n\n#3. Do ECO on points listed in the file\nfix_design(\"-list_file\", $list_file);\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_fix_logic.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.fix_logic.txt", "chroma:document": "fix_logic\nECO command. Fix listed points\nUsage: fix_logic(@pin_port_list,@options);\n@options:\n    -force: Force the tool to replace the logic cone of the points in @pin_port_list\n@pin_port_list: \n    List of the pins or ports whose logic will be fixed by the reference logic in Reference Netlist\n     The format is \"sic_cnt_reg_0/D\",\"sic_cnt_reg_1/D\",'\\bbr_ccd_reg[0] /D',\"out_port\"\n     '\\' should be kept if the instance has '\\' as prefix. \n     E.G. '\\bbr_ccd_reg[0] ' instance has '\\' and last space in the name.\n\n\nExamples:\n\n#1. Fix state_regs's D inputs\nfix_logic(\"state_reg_0/D\", \"state_reg_1/D\");\n\n#2. Fix state_regs's D inputs and one output port\nfix_logic(\"state_reg_0/D\", \"state_reg_1/D\", \"out_port\");\n\n#3. Add one new flop, input pins have the same connections as the Reference Netlist\n#  and the output is floating, -recover option sets to 0\nfix_logic('new_flop_reg/D', 'new_flop_reg/CK', 'new_flop_reg/RB');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_flatten_modules.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.flatten_modules.txt", "chroma:document": "flatten_modules\nFlatten hierarchical modules in reference netlist\nUsage: flatten_modules(@module_names);\n@module_names: List of modules to be flatten\n\nExamples:\n\nflatten_modules(\"retime_1\", \"sync_cell_0\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_cells.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_cells.txt", "chroma:document": "get_cells\nGet all cells in the current module or sub-modules (LLM: find/get instance)\nUsage: my @cells = get_cells($pattern, @options);\n$pattern: The pattern matching instance name, '*', 'U*', 'U123' or '/UI_.*_./' \n          It can have path, 'u_clk/*', 'u_abc/u_def/*'\n@options:\n    -help: Print this information\n    -hier: Or -h, do the command hierarchically\n    -ref ref_pattern: Get cells that has reference matching ref_pattern, E.G. -ref OAI*\n    -type type_pattern: Type_pattern can be 'ff','latch','itiming','cg','not','rom','ram' ... \n                        run 'get_lib_cells -type_info' for all existing type in the current libraries\n    -type_match type_pattern: Get cells that have one of the types matches the type_pattern\n    -leaf: Only leaf cells\n    -new: Only new created ECO instances\n    -verbose: To print out reference with instance\n    -dotpath: Path delimit is '.' instead of '/'\n    -nobackslash: Remove backslash \n    -nonscan: Flops/sync-cells not in scan chain including those scan pins tied off\n@cells: Returned array with all instances matched\n\nExamples:\n\n#1. Get all instances in the current module \nmy @cells = get_cells('*');\n\n#2. Get all instances in the current module \nmy @cells = get_cells();\n\n#3. Get all instances matching 'U234*' in the current module\nmy @cells = get_cells('U234*');\n\n#4. Regular expression. Get all instances starting with U and followed by \n#    two characters, like U10, U99\nmy @cells = get_cells('/U../');   \n\n#5. Get all instances matching *reg_*_ hierarchically\nmy @cells = get_cells('*reg_*_', '-hier');\n\n#6. Get all instances hierarchically and having reference matching DFF*\nmy @cells = get_cells('*', '-hier', '-ref', 'DFF*');\n\n#7. Get all instances in 'u_kb'\nmy @cells = get_cells('u_kb/*');\n\n#8. Get all flops, sync-cells not in scan chain \nmy @cells = get_cells('-hier', '-nonscan');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_cell_cofactors.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_cell_cofactors.txt", "chroma:document": "get_cell_cofactors\nGet combinational cell pin Shannon expansion cofactors\nUsage: @cofactors = get_cell_cofactors($cell, $pin);\n$cell: Leaf cell name\n$pin: Input pin name\n@cofactors: Shannon cofactors for the pin of the cell\n            It has two items if the cell is combinational \n            It is empty if the cell is sequential or black-box\n\nExamples:\n\n#1. NAND2X1 A pin \n@ret = get_cell_cofactors(\"NAND2X1\", \"A\"); # @ret = (1, B);\n#2. AOI222X1 A0 pin\n@ret = get_cell_cofactors(\"OAI222X4\", \"A0\"); \nreturned @ret = (\"!(A1*(B0*(C0+C1)+!B0*(B1*(C0+C1))))\", \"!(B0*(C0+C1)+!B0*(B1*(C0+C1)))\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_cell_info.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_cell_info.txt", "chroma:document": "get_cell_info\nGet information of a module or instance (LLM: information)\nUsage: $data = get_cell_info($module_or_inst, @options);\n$module_or_inst: The module or instance's name\n@options:\n    -help: Print this information\n    -conns: Get Connections of the item, only when it's instance\n    -type: Get the item's type information. It can be 'ff','cg,'latch','buf', \n            run 'get_lib_cells -type_info' for all existing type in the current libraries\n            An array is returned if this option is present\n    -libname: Get the library name that the cell is in\n    -area: Get the area of the item\n    -size: Get the size of the item\n    -fun:  Get the function string of the item\n    -leakage: Get the leakage of the item\n    -ref:     Same as 'get_ref instance' if the item property is instance\n    -context: Get detail library information\n    -attribute attribute_name: Check if the cell has the attribute set. 0 or 1 is returned\n$data: Returned data, if '-attribute' option is present, $data is 0 or 1\nIn option is '-conns' case,\nIt is a hash having the following data structure\nmy $module = $hash->{module};\nmy $instance: $hash->{instance};\nforeach my $port (keys %{$hash->{connections}}){\n    my $net = $hash->{connections}{$port};\n}\n\nIf no option is present, it return the item's property:\nleaf_instance leaf_module hierarchical_instance hierarchical_module \n\nExamples:\n\n#1. Get area of one leaf cell\nmy $area = get_cell_info(\"AND2X2\", \"-area\");\n\n#2. Get an attribute of one leaf cell\nmy $is_iso = get_cell_info(\"ISOX2\", \"-attribute\", \"is_isolation_cell\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_conns.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_conns.txt", "chroma:document": "get_conns\nGet connections of net or pin in the top level module, return the leafs and the hierarchical connections (LLM: conns)\nUsage: @result = get_conns($net_or_pin, @options);\n$net_or_pin: The net name or pin name that needs to get connections.\n@options:\n   -driver: Return driver only\n   -load: Return load only\n   -count: Return connections count\n@result: a two dimension array\n          instance, port_name, pin_or_port, load_or_driver, is_it_a_leaf, \n@result = ([instance_0, pin_0, 'pin', 'load', 1],\n           ...\n          )\n\nExamples:\n\n#1. Net 'n599' has three connections, instance 'U198' is the driver\nget_conns(\"n599\");\ngte_344 A[14] pin load 0\nU198 Y pin driver 1\nU94 AN pin load 1\n\n#2. Net 'qcifhbeat' has three connections, it is output port of the current top level module\nget_conns(\"qcifhbeat\")\n qcifhbeat port load\nU80 A pin load 1\nqcifhbeat_reg Q pin driver 1\n\n#3. The argument in inst/pin format\nget_conns(\"U187/A\")\nU294 A1 pin load 1\nU187 A pin load 1\nU80 Y pin driver 1\n\n#4. Return connections count\nget_conns(\"U187/A\", \"-count\");\n3\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_coord.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_coord.txt", "chroma:document": "get_coord\nGet an instance's coordination (LLM: coordination)\nUsage: my ($x, $y) = get_coord($instance);\n$instance: Instance name\n\nExamples:\n\nmy ($x, $y) = get_coord(\"xbar/U1234\");\n# $x=100, $y=200 in um\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_definition.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_definition.txt", "chroma:document": "get_definition\nGet instantiation of instance\nUsage: my $line = get_definition($inst);\n$inst: Instance name.\n$line: The instantiating line\n\nExamples:\n\nget_definition('U78');\nReturns \"AND2X1 U78(.A(n1), .B(n2), .Z(n3));\"\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_driver.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_driver.txt", "chroma:document": "get_driver\nGet the driver of a net or pin (LLM: driver)\nUsage: @driver = get_driver($point, @options);\n$point: net name or pin name, 'n12345' or 'U12345/A1'\n@options:\n   -pin: Return in \"inst/pin\" format, E.G. \"state_reg/Q\"\n         Return an array if '-pin' is not present\n   -nonbuf: Trace the drivers until none buffer \n@driver: The driver in array format, if '-pin' is not present.\n         If the point is floating, @driver is empty, \n         $driver[0]: Driver instance name. It is empty if the driver is port\n         $driver[1]: Driver pin or port name. If the driver is a port, it is the port name\n         $driver[2]: Driver type. It is string \"pin\" or \"port\" depending on the driver is port or leaf cell\n         $driver[3]: Driver phase. It is valid when -nonbuf is present, \n                     indicating if the driver path is inverted\n                     0: not inverted 1: inverted              \n\nNote:\n1. If '-pin' is present, return a scalar, $driver = get_driver(\"n12345\", \"-pin\");\n2. Use 'get_drivers' if there are multiple drivers, the return data has different structure\n\nExamples:\n\n#1. Get driver of a net\n@driver = get_driver(\"net12345\");\n@driver has content of (\"U1247\", \"Y\", \"pin\");\n\n#2. port_abc is input port\n@driver = get_driver(\"port_abc\"); \n@driver has content of (\"\", \"port_abc\", \"port\");\n           \n#3. Return in instance/pin format\n$driver = get_driver(\"net12345\", \"-pin\");\n$driver has content of \"U1247/Y\"\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_drivers.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_drivers.txt", "chroma:document": "get_drivers\nGet the drivers of a net or pin (LLM: drivers)\nUsage: @drivers = get_drivers($point, @options);\n$point: net name or pin name, 'n12345' or 'U12345/A1'\n@options:\n   -nonbuf: Trace the drivers until none buffer \n@drivers: An array of the drivers, if the point is floating, @drivers is empty, \n         if the point has multi-drivers, @drivers has more than one items.\n         For each item in @drivers\n         Index 0: instance, it is empty if the driver is port\n         Index 1: pin or port, if the driver is port, return port\n         Index 2: string \"pin\" or \"port\" depending on the driver is port or leaf cell\n         Index 3: indicating drive path inverted or not\n         If 'nonbuf' is present, the last item in @drivers is the non-buffer driver\n         So '$nonbuf = pop @drivers' can get the non-buffer driver \nNote:\nUse 'get_driver' instead if the net has only one driver and 'nonbuf' option is not used\n\nExamples:\n\n#1. Get drivers of a net\n@drivers = get_drivers(\"net12345\");\n@drivers has content of ([\"U1247\", \"Y\", \"pin\"]);\n\n#2. 'port_abc' is input port\n@drivers = get_drivers(\"port_abc\"); \n@drivers has content of ([\"\", \"port_abc\", \"port\"]);\n   \n#3. Buffers in the path\n @drivers = get_drivers(\"state_reg/CK\", \"-nonbuf\");\n @drivers has content of\n  (\n    [\"buf_inst0\", \"Y\", \"pin\"],\n    [\"inv_inst1\", \"Y\", \"pin\"],\n    [\"and_inst2\", \"Y\", \"pin\"]\n  )\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_instance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_instance.txt", "chroma:document": "get_instance\nGet instance in the top level module\nUsage: my $instance = get_instance($pattern, @options);\n$pattern: Match pattern, can have wildcard \"*\", if it is empty, it is treated as \"*\"\n@options:\n    -module: module name to have its instance name found\n$instance: Return the first instance matching\n\nExamples:\n\n#1. The fist hierarchical instance matching 'ui_*'.\n$instance = get_instance(\"ui_*\");  \n\n#2. Find the instance name of module 'enet_control' \n$instance = get_instance(\"-module\", \"enet_control\");   \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_instances.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_instances.txt", "chroma:document": "get_instances\nGet all hierarchical instances in the top level module (LLM: hierarchical instances)\nUsage: my @instances = get_instances($pattern);\n$pattern: Match pattern, can have wildcard \"*\", if it is empty, it is treated as \"*\"\n\n@instances: Array of the hierarchical instances\n\nExamples:\n\n@instances = get_instances(\"UI_*\"); # Any hierarchical instances with UI_ as prefix.\n@instances = get_instances;         # All hierarchical instances. \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_leafs_count.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_leafs_count.txt", "chroma:document": "get_leafs_count\nGet all leaf cells name and count in the top level module, return an array \nUsage: @leaf_count = get_leafs_count;\n@leaf_count: Array of leaf name and count\n ( [leaf0, cnt0], [leaf1, cnt1], ...)\n\nExamples:\n\n@leaf_count = get_leafs_count;\nforeach my $leaf_point (@leaf_count){\n   my $leaf_name = $leaf_point->[0];\n   my $count = $leaf_point->[1];\n   print \"LEAF: $leaf_name has $count cells\n\";\n}\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_leaf_pin_dir.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_leaf_pin_dir.txt", "chroma:document": "get_leaf_pin_dir\nGet leaf cell pin's direction input/output/inout\nUsage: my $dir = get_leaf_pin_dir(\"$leaf_name/$pin\");\n$pin: pin name, E.G.  A or B or Y\n$leaf: Leaf cell name, E.G. NAND2X2\n$dir: return direction, input/output/inout\n\nExamples:\n\nmy $dir = get_leaf_pin_dir(\"NAND2X2/A\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_lib_cells.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_lib_cells.txt", "chroma:document": "get_lib_cells\nGet leaf gates in libraries \nUsage: my @cells = get_lib_cells($pattern, @options);\n@options:\n     -help:            This information\n     -char:            All cells characterization\n     -type leaf_type:  Get leaf gates matching type. \n                       Leaf_type can be 'ff', 'latch', 'cg', 'buf', 'not', 'and' ...\n     -type_info:       List all types in the current loaded libraries\n     -verbose:         If $pattern matches only one lib cell, print the cell lib information\n$pattern: Library cell name pattern, can have '*'.\n@cells: Return array with name matching\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_loads.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_loads.txt", "chroma:document": "get_loads\nGet loads of net in the top level module, return the leafs connections (LLM: loads)\nUsage: @result = get_loads($net_or_pin, @options);\n$net_or_pin: The net name or pin name that needs to get fanouts.\n@options:\n   -nonbuf: Trace the loads until none buffer \n   -bypbuf: Don't include buffer/inverter in the return array\n   -hier: Loads cross hierarchies\n   -fanend: Fanout endpoints, flops or ports\n@result: A two dimension array. Each item has format of 'instance' and 'pin_name' if\n         the load is leaf cell. Or 'port_name' and 'GOF_PIN_IN' \n@result = ([instance_0, pin_0],\n           [instance_1, pin_1],\n           [port_name, GOF_PIN_IN],\n           ...\n          )\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_loads_phase.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_loads_phase.txt", "chroma:document": "get_loads_phase\nGet loads of net with phase in the top level module, return the non-buffer/inverter leafs connections (LLM: loads with phase)\nUsage: @result = get_loads_phase($net_or_pin, @options);\n$net_or_pin: The net name or pin name that needs to get fanouts.\n@options:\n   -help: This information\n@result: A two dimension array. Each item has format of 'instance', 'pin_name' and 'phase', if\n         the load is leaf cell. Or 'port_name', 'GOF_PIN_IN' and 'phase' \n@result = ([instance_0, leaf_0, pin_0, 0],\n           [instance_1, leaf_0, pin_1, 1],\n           [port_name,  GOF_CELL_OUTPORT,GOF_PIN_IN, 1],\n           ...\n          )\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_logic_cone.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_logic_cone.txt", "chroma:document": "get_logic_cone\nGet logic cone of nets or pins\nUsage: $result = get_logic_cone(@InstancePinList, @options);\n@InstancePinList: Instance/pin and net list. \n$result: 1, the command fails. 0, the command completed successfully\n@options:\n    -o file_name: Write output to the file. Default logic_cone.v\n\nExamples:\n\nmy @InstPin = ('abc_reg/D', 'n12345');\nmy $ret = get_logic_cone(@InstPin, '-o', 'MyLogicCone.v');\n# The logic cone is written out to verilog file 'MyLogicCone.v'\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_modules.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_modules.txt", "chroma:document": "get_modules\nGet modules under current module (LLM: submodules)\nUsage: @modules = get_modules($pattern, @options);\n$pattern: Match pattern, can have wildcard \"*\", if it is empty, it is treated as \"*\"\n@options:\n    -help: Print this information\n    -hier: Get all modules hierarchically\n@modules: Modules list, (\"module0\", \"module1\", ...)\n\nExamples:\n\n@modules = get_modules(\"*TM*\");  # Any hierarchical modules with TM in the name.\n@modules = get_modules;          # All hierarchical modules.\n@modules = get_modules(\"-hier\"); # All hierarchical modules and sub-modules under current module.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_nets.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_nets.txt", "chroma:document": "get_nets\nGet nets that matching pattern (LLM: matched nets)\nUsage: @nets = get_nets($pattern, @options);\n$pattern: The net naming pattern, \"*\" or empty for all nets\n@options:;\n   -const0: Get all constant zero nets\n   -const1: Get all constant one nets\n@nets: returned net array.\n\nExamples:\n \n1#. Get all nets.\n@nets = get_nets(\"*\"); \n\n2#. All nets with 'dbuffer' as prefix \n@nets = get_nets(\"dbuffer_*\"); \n\n3#. Get constant nets\n@nets = get_nets(\"-const0\"); \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_net_of.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_net_of.txt", "chroma:document": "get_net_of\nGet net name connecting to a pin (LLM: net of pin)\nUsage: my $net = get_net_of($pin);\n$pin: The pin of the instance, 'U1234.A1' or 'U1234/A1' \n$net: The net name connecting to the pin\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_path.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_path.txt", "chroma:document": "get_path\nGet current hierarchical path (LLM: path)\nUsage: $path = get_path();\n$path: The current path\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_pins.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_pins.txt", "chroma:document": "get_pins\nGet pins of instance or module (LLM: pins)\nUsage: @pins = get_pins($name, @options);\n$name: The instance or module name, it can be hierarchical or leaf\n@options:\n    -input: Get input pins\n    -output: Get output pins\n    -inout: Get inout pins\n    -clock: Get clock pin, only valid for sequential cell, flop latch and gated-clock-cell\n    -reset: Get reset pin, return \"\" if it doesn't exist\n    -set:   Get set pin, return \"\" if it doesn't exist\n    -data: Get data pins\n    -attribute attribute: Get pins with the attribute\n    -nextstate_type type: Get pins matching the type \n            which can be 'data', 'load', 'scan_in', 'scan_enable'\n            This option is only valid for sequential cell, flop, latch and gated-clock-cell\nIf no option is present, get all pins\n@pins: All pins returned, in 'instance/pin' format\n\nExamples:\n\n#1. Get input pins of a hierarchical instance\nmy @pins = get_pins(\"-input\", \"u_abc/U123\");\nResult @pins = (\"u_abc/U123/A\", \"u_abc/U123/B\")\n\n#2. Get pins of a leaf cell\n@pins = get_pins(\"AND2X2\");\nResult @pins = (\"A\",\"B\",\"Y\") \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_ports.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_ports.txt", "chroma:document": "get_ports\nGet all ports in the current top level module (LLM: ports)\nUsage: @matching_ports = get_ports($pattern, @options);\n$pattern: Match pattern, can have wildcard \"*\". If it is empty, it is treated as \"*\"\n@options:\n          -input: Get input ports only\n          -output: Get output ports only\n          -inout: Get inout ports only\n          -bus: Get ports in bus format instead of bit blast. \n                The API returns an array point if this option present\n                The item in the array has format of [port, IsBus, MaxIndex, MinIndex]\n                if IsBus == 1, MaxIndex is the Max Index of the bus, E.G, 7 if the bus is port_a[7:0]\n                if ISBus==0, MaxIndex and MinIndex are not defined\n  \nIf no option is present, get all ports\n\n@matching_ports: Return ports matching the pattern and the option specified in \n                  the current top level module\n\nExamples:\n\n@ports = get_ports(\"-input\", \"dsp2mc_*\");  # Get input ports with \"dsp2mc_\" as prefix\n@ports = get_ports;                       # Get all ports\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_ref.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_ref.txt", "chroma:document": "get_ref\nGet the reference of the instance, return leaf cell name or hierarchical module name (LLM: design name)\nUsage: $reference = get_ref($instance);\n$instance: Instance name, \"U123\"\n$reference: Return reference name, \"NAND2X4\" \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_resolved.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_resolved.txt", "chroma:document": "get_resolved\nResolve the relative path to module and leaf item\nUsage: ($module, $leaf) = get_resolved($relative_path);\n$relative_path: Relative path, like \"u_abc/u_def/U456\"\n$module: Resolved module name, like \"def\"\n$leaf: Resolved leaf name, like U456\n\nExamples:\n\nmy ($module, $leaf) = get_resolved(\"u_abc/u_def/U456\");\n$module has value \"def\"\n$leaf has value \"U456\"\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_roots.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_roots.txt", "chroma:document": "get_roots\nGet root designs name\nUsage: my @rootdesigns = get_roots;\n@rootdesign: returned root designs name\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_scan_flop.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_scan_flop.txt", "chroma:document": "get_scan_flop\nGet scan flop for the non scan flop (LLM: scan flop)\nUsage: my $scanflop = get_scan_flop($nonscanflop);\n\nExamples:\n\n# Get a corresponding scan flop for non scan flop DFFHQX1\nmy $scanflop = get_scan_flop(\"DFFHQX1\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_spare_cells.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_spare_cells.txt", "chroma:document": "get_spare_cells\nECO command. Get spare cells (LLM: metal only)\nUsage: get_spare_cells($pattern,@options);\n$pattern: Spare leaf cell instance pattern, E.G. 'spare_inst*/spare_gate*'\n          Extract spare cells from the database with the pattern\n          The first half before '/' is hierarchical instance pattern, it is '*' for top level\n          The second half after '/' is leaf instance pattern\n          It is ignored if -file option is present\n@options:\n    -o file_name: Write updated spare cell list to the file, \n                  by default, it has name 'spare_cells_scriptname.list'\n    -file spare_list_file: Load in spare cell list file instead of extracting from the database\n    -gate_array gate_array_naming: Gate Array naming style, like 'G*', most standard libraries have Gate Array cells naming starting with 'G'\n                  This option enables Metal Only Gate Array Spare Cells ECO flow\n    -gate_array_filler gate_array_filler_naming: Gate Array Filler naming style, like 'GFILL*',\n                  or 'GFILL*|GDCAP*' to include both GA Filler and GA DCAP\n    -ignore_load: By default, if the spare cell has fanout, it won't be added into the list. When this option is set, \n                  any matched spare cell is added into the list \n    -exclude_cell_type cell_type: Exclude cell type matching cell_type, cell_type supports wild card like DFFRS*\n    -addfreed: Only use deleted gates as spare resource\n\nExamples:\n\n#1. Extract spare cells from the database, matching instances like \"SPARE_u0\"\nget_spare_cells(\"*/SPARE_*\");   \n\n#2. Matching hierarchical instance \"someSpare_*\" and leaf instance \"spr_gate*\"\nget_spare_cells(\"someSpare_*/spr_gate*\"); \n\n#3. Extract spare cells from file \"spare_cells_list.txt\"\nget_spare_cells(\"-file\", \"spare_cells_list.txt\"); \n\n#4. Enable Gate Array Spare Cells Metal Only ECO Flow, map_spare_cells will map to Gate Array Cells only\nget_spare_cells(\"-gate_array\", \"G*\", \"-gate_array_filler\", \"GFILL*|GDCAP*\");\n\n#5. Matching hierarchical instance \"someSpare_*\" and leaf instance \"spr_gate*\", but excluding DFFRS*\nget_spare_cells(\"someSpare_*/spr_gate*\", \"-exclude_cell_type\", \"DFFRS*\"); \n\n#6. Only used freed gated in metal only ECO\ndel_gate(\"u_control/the_status_reg\"); # Delete the unused flop and its logic cone will be deleted\nfix_design;\nget_spare_cells(\"-addfreed\");\nmap_spare_cells;\n\nNote:\n\nThe API has to run on top level, \nset_top('most_top_module')\nget_spare_cells(\"someSpare_*/spr_gate*\"); \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_get_spare_in_use.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.get_spare_in_use.txt", "chroma:document": "get_spare_in_use\nGet spare cells used in the ECO \nUsage: set_spare_in_use();\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_gexit.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.gexit.txt", "chroma:document": "gexit\nExit the command interactive mode\nUsage: gexit;\n "}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_gof_version.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.gof_version.txt", "chroma:document": "gof_version\nPrint out GOF version\nUsage: gof_version;\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_gprint.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.gprint.txt", "chroma:document": "gprint\nPrint the message and save to log file (LLM: print)\nUsage: gprint($info);\n$info: The message to be printed.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_is_leaf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.is_leaf.txt", "chroma:document": "is_leaf\nCheck if a module or instance is leaf cell (LLM: leaf)\nUsage: my $leaf = is_leaf($name);\n$name: The module or instance under check\n$leaf: 0, it's a hierarchical module, (Or the module is not defined)\n       1, it's leaf cell. Like, NAND4X8\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_is_pin_masked.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.is_pin_masked.txt", "chroma:document": "is_pin_masked\nCheck if an instance pin has been masked in the current constraint (LLM: masked)\nUsage: my $is_masked = is_pin_masked($inst_pin);\n$inst_pin: Instance pin, for instance u_control/u_mbist/U1/A\n$is_masked: 0, it is not masked\n            1, it is masked\n\nExamples:\n\n#1. Check if a DFT MUX has B pin masked in DFT mode 'MX2X4 uMUXD9(.A(ana_in),.B(test_in),.S(atpg_mode),.Z(mux_out9));\nset_pin_constant('atpg_mode', 1);\nmy $is_masked = is_pin_masked(\"uMUXD9/A\"); # It returns 1\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_is_scan_flop.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.is_scan_flop.txt", "chroma:document": "is_scan_flop\nCheck if an instance is scan flop (LLM: scan flop)\nUsage: my $isscan = is_scan_flop($name);\n$name: The cell name or instance name\n$isscan: 0, it's not a scan flop\n         1, it's a scan flop\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_is_seq.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.is_seq.txt", "chroma:document": "is_seq\nCheck if an instance or a leaf cell is a specific sequential cell (LLM: sequential)\nUsage: my $isseq = is_seq($name, @options);\n$name: The instance under check\n@options:\n    -help:  This information\n    -ff:    Check if it's a flipflop\n    -bank:  Check if it's a multibit flop\n    -latch: Check if it's a latch\n    -cg:    Check if it's a gated clock\n    -rom:   Check if it's a rom\n    -ram:   Check if it's a ram\n$isseq: 0, it is not the specific sequential cell\n        1, it is the specific sequential cell\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_list_wireload.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.list_wireload.txt", "chroma:document": "list_wireload\nTiming command. List all wireload defined in the liberty files\nUsage: list_wireload;\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_map_spare_cells.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.map_spare_cells.txt", "chroma:document": "map_spare_cells\nECO command. Map all new created cells to spare cells (LLM: metal only)\nUsage: $status = map_spare_cells;\n$status: 0: the mapping is successful\n         non zero: the mapping fails \n@options:\n    -help: Print this information.\n    -syn Synthesis_command_line: \n            By default, the built-in Synthesis Engine is used.\n            External Synthesis tool can be picked by this option\n            RTL Compiler and Design Compiler are supported. \n            E.G. \"map_spare_cells('-syn', 'rc')\" to pick RTL compiler\n                 \"map_spare_cells('-syn', 'dc_shell')\" to pick Design Compiler \n            User can specify more values in the synthesis command\n            E.G. '-rc', \"rc -E -use_lic RTL_Compiler_Physical\"\n    -lib_header file_name: This option is Valid when '-syn' option is present. To insert the content of \n                           file 'file_name' to the header of synthesis tcl script. So that '.lib' file to\n                           '.db' conversion can be avoided in Design Compiler case. \n                           For example, in Design Compiler case, the file content should have\n                             set_search_path [list /project/lib/_db]\n                             set_target_library [list art40_hvt art40_svt]\n                             set link_library [list art40_hvt art40_svt]\n    -nofreed: Don't add freed gates for synthesis. \n    -nobuf: Don't insert buffers/repeaters in long wires. \n    -notielow: Don't tie low of the input pins of output floating gates, delete them instead\n    -pause: Pause the tool before apply the patch\n    -exact: Map to the exact name of spare cell, by default the tool picks up a spare cell with \n            the same function, for example, pick up 'INVX2' for 'INVX4'\n    -gcmp: Use GOF compiler\n    -nospare_mapping: Don't map to physical spare gates even DEF file is loaded\nNote: A DEF file is needed for mapping to exact spare instances.\n\nExamples:\n\n#1. Map to spare cells and use the built-in Synthesis Engine\nmy $status = map_spare_cells;\n\n#2. Use extra 'rc' option\nmap_spare_cells('-syn', \"rc -E -use_lic RTL_Compiler_Physical\")\n\n#3. Don't add freed cells for synthesis\nmap_spare_cells('-syn', \"rc -E -use_lic RTL_Compiler_Physical\", \"-nofreed\")\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_new_gate.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.new_gate.txt", "chroma:document": "new_gate\nECO command. Create new gate\nUsage: @return = new_gate($new_net, $reference, $new_instance, $connections);\nNote: if the command is called in the context of return a scalar, the new created instance name\n        returns. \n      The usage is the same as new_net, except $reference has to be defined, \n        and return back instance if scalar present.\n      Run \"help new_net\" for detail in the shell \"GOF >\"\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_new_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.new_net.txt", "chroma:document": "new_net\nECO command. Create a new net\nUsage: @return = new_net($new_net, $reference, $new_instance, $connections);\n$new_net: The new net to be created, if not defined, the tool assigns one automatically\n$reference: The leaf gate name to drive the net.\n$new_instance: The instance name of the new cell, or leave it empty to get automatically assigned.\n$connections: The new gate input pins connections \n   Supported formats, 1. Detail format:  \".A(net0),.B(net1),.C(net2)\"\n                      2. Simple format: Connect to the pins in alphabetical sequence \n                          \"net1,net0,net2\" indicating .A(net1),.B(net0),.C(net2)\n                      3. Mixed format: \"instance/pin\" and net, \"U408/Y,U409/Y,net2\" indicating \n                          A to U408/Y, B to U409/Y and C to net2\n                      4. The \"instance/pin\" can have sub-instance hierarchy, \"u_abc/U408/Y\"\n@return: Have the new created instance and net name.\n$return[0] : New created instance.\n$return[1] : New created net.\n\nNote: Hierarchical path is supported in any net or instance in the command, \n         for instance, new_net('u_abc/net124', ...\n      If the command is called in the context of return a scalar, the new created net name is returned. \n      The new net is assumed to be driven in the path it is created, \n         for instance, new_net('u_abc/eco12345_net124');\n      eco12345_net124 should be driven in sub-instance u_abc after it is created.\n\nExamples:\n\n#1. NAND2x2 instance name 'U_eco_123' driving new net 'net123'\nnew_net(\"net123\", \"NAND2X2\", \"U_eco_123\", \".A(n200),.B(n201)\");  \n\n#2. INVX2 with instance name 'U_inv' is created in u_abc sub-instance\n#  and the input pin of the new invert is driven by n200 in current top level\n#  port would be created if n200 doesn't drive input port to u_abc\nnew_net(\"u_abc/net123\", \"INVX2\", \"u_abc/U_inv\", \"n200\"); \n\n#3. Create a new net \"net500\"\nnew_net(\"net500\");  \n \n#4. Create a new instance with new net tied to output pin, input pin is floating.\n# $return[0] is new created instance, $return[1] is new created net.\n@return = new_net(\"\", \"INVX2\", \"\", \"\"); \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_new_port.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.new_port.txt", "chroma:document": "new_port\nECO command. Create a new port for the current top level module\nUsage: new_port($name, @options);\n$name: Port name\n@options:\n    -input: New an input port\n    -output: New an output port\n    -inout: New an inout port\n\nNote: The port name has to be pure words or with bus bit, like, abc[0], abc[1]\n\nExamples:\n\nnew_port('prop_control_en', '-input');  # create an input port naming 'prop_control_en'\nnew_port('prop_state[2]', '-output');   # create an output port with bus bit 'prop_state[2]'\nnew_port('prop_state[3]', '-output');   # create an output port with bus bit 'prop_state[3]'\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_place_gate.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.place_gate.txt", "chroma:document": "place_gate\nECO command. Place an instance to a specific position\nUsage: place_gate($inst, $x, $y);\n$inst: The instance to be placed\n$x,$y: The coordinate\n\nNote: This command affects the spare gate mapping of the instance.\n\nExamples:\n\n# A flop is added and placed in some location\n# In 'map_spare_cells' command, the flop is mapped to a spare flop closest to the location\nchange_pin(\"U123/A\", \"DFFX1\", \"eco_dff_reg\", \".D(-),.CK(clock)\");\nplace_gate(\"eco_dff_reg\", 100, 200); # location, 100um, 200um\nmap_spare_cells;\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_place_port.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.place_port.txt", "chroma:document": "place_port\nECO command. Place port position\nUsage: place_port($port, $x, $y);\n$port: The port to be placed\n$x,$y: The coordinate\nThis command has effect on change_port ECO command\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_pop_top.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.pop_top.txt", "chroma:document": "pop_top\nPop out the saved top level module from the stack and discard the current setting (LLM: pop current top design from stack)\nUsage: pop_top;\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_post_recovery.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.post_recovery.txt", "chroma:document": "post_recovery\nECO command. recover deleted gates after ECO\nUsage: post_recovery(@options);\n@options:\n   -inv: Replace INV by NAND/NOR\n   -incr: Incremental, preceded by map_spare_cells\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_preserve_modules.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.preserve_modules.txt", "chroma:document": "preserve_modules\nPreserve wires in the modules listed or all modules\nUsage: preserve_modules(@module_list, @options);\n@options:\n   -all: Preserve wires in all modules\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_push_top.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.push_top.txt", "chroma:document": "push_top\nSet the current top level module and push the previous setting to stack, pop_top can retrieve it (LLM: push stack current top design)\nUsage: push_top($module);\n$module: Set the $module as the top level module, push the previous setting to the stack\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_def.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_def.txt", "chroma:document": "read_def\nRead DEF file\nUsage: my $status = read_def(@files, @options);\n@files:  DEF files\n@options:\n   -defverbose: Report all DEF parsing warnings and errors\n$status: If zero, the files have been read in successfully\n         if non-zero, failed to read in the files\n\nExamples:\n\nmy $status = read_def(\"soc_top.def\");  # Read in soc_top.def \nmy $status = read_def(\"soc_top1.def\", \"soc_top2.def\");  # Multiple DEF files\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_design.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_design.txt", "chroma:document": "read_design\nRead verilog netlist files (LLM: read verilog)\nUsage: my $top_module = read_design(@files, @options);\n@files: Verilog netlist files\n@options:\n    -imp: The netlists are for the Implementation which are under ECO\n    -ref: The netlists are for the Reference\n    -prelayout: The netlists are prelayout for hierarchical ports phase detection\n    -Top_1: Read design to create Top_1 tree database\n    -Top_2: Read design to create Top_2 tree database\nNote: If no -imp or -ref option is provided, the netlist is assumed 'implementation'\n$top_module: Return top level module name after the successful read \n\n\nExamples:\n\n#1. Read in an implementation netlist file\nmy $top_module = read_design(\"-imp\", \"soc_design_resynthesized.gv\");\n\n#2. Read in a reference netlist file\nmy $top_module = read_design(\"-ref\", \"soc_design_released.gv\");\n\n#3. Read in two reference netlist files\nmy $top_module = read_design(\"-ref\", \"soc_design_released.gv\", \"soc_io.gv\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_file.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_file.txt", "chroma:document": "read_file\nRead timing violation report file\nUsage: my $status = read_file($file_name, @options);\n$file_name: file name\n@options:\n    -format format: accu/pt\n                    accu --- Accucore report file. \n                    pt   --- Prime Time report file\n$status: If zero, the file is read in successfully\n         if one, failed to read in the file\n\n\nNote: Prime Time timing report file should be generated by report_timing command with these options\n      report_timing -nosplit -path_type full_clock_expanded -delay max/min -input_pins \\\n                    -nets -max_paths 10000 -transition_time -capacitance\n\nExamples:\nmy $status = read_file(\"soc_primetime_hold.report\", \"-format\", \"pt\"); \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_lef.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_lef.txt", "chroma:document": "read_lef\nRead LEF file\nUsage: my $status = read_lef(@files);\n@files:  LEF files\n$status: If zero, the files are read in successfully\n         if one, failed to read in the files\n\nExamples:\n\nmy $status = read_lef(\"soc_top.lef\");  # Read in soc_top.lef \nmy $status = read_lef(\"soc_top.lef\", \"soc_top1.lef\", \"soc_top2.lef\");  # Read in multiple LEF files \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_library.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_library.txt", "chroma:document": "read_library\nRead standard library or verilog library files (LLM: read library)\nUsage: my $status = read_library(@files, @options);\n@options:\n   -v: Treat the @files as verilog library files\n   -lib: Treat the @files as standard library files\n   -f library_list_file: Load library files from list file, the list file has format of\n                         -v verilog_lib0.v\n                         -v verilog_lib1.v\n                         -lib tsmc40.lib\n   -vmacro: Treat the @files as macro library files which are used as macro cell in ECO\n   -rtl: Treat as RTL format\n   -gate: Treat as gate format, if not specify -rtl or -gate, the tool automatic picks one\n   -top top_module: Only process the module top_module as the leaf cell, discard all other modules\n   -ref: The library is for the Reference Netlist only\n@files: Standard library files, or verilog library files\n\nNote: The three options, '-v' '-lib' and '-vmacro' don't coexist.\n      If the file has .lib extension, '-lib' can be omitted, and it is treated as standard library file.\n      If the file has .v or .vlib extension, '-v' can be omitted, and it is treated as verilog file.\n$status: If zero, the file is read in successfully\n         if one, failed to read in the file\n\nExamples:\n\nmy $status = read_library(\"arm_40_hvt.lib\", \"arm_40_io.lib\");\nmy $status = read_library(\"analog_stub.v\", \"analog_stub2.vlib\");\nmy $status = read_library(\"-v\", \"analog_stub.gv\");\nmy $status = read_library(\"-vmacro\", \"macrocell.v\");\nmy $status = read_library(\"-f\", \"lib_files.list\");\nmy $status = read_library(\"-top\", \"abs_control_top\", \"abs_control_top_post.v\");\nmy $status = read_library(\"ref_special.lib\", \"-ref\"); # The library is only for the Reference Netlist \n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_rtl.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_rtl.txt", "chroma:document": "read_rtl\nRead RTL files\nSupport SystemVerilog (IEEE 1800-2017)\nUsage: read_rtl(@files, @options);\n@options:\n    -imp: The RTL files are for Implementation\n    -ref: The RTL files are for Reference\n\nNote: It can only run on Centos7 and above, Centos6 is not supported.\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_rtlpatch.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_rtlpatch.txt", "chroma:document": "read_rtlpatch\nRead RTL Patch file \nUsage: my $status = read_rtlpatch($file, @options);\n$file: RTL file for ECO \n$status: If zero, the file is read in successfully\n         if one, failed in reading the file\n\nExamples:\n\n#1. Read in RTL Patch verilog file\nmy $status = read_rtlpatch(\"rtlpatch_change.v\");\n\n#2. Multiple RTL Patch files are read in one by one\nmy $status1 = read_rtlpatch(\"rtlpatch_change1.v\");\nmy $status2 = read_rtlpatch(\"rtlpatch_change2.v\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_sdf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_sdf.txt", "chroma:document": "read_sdf\nRead SDF Standard Delay Format file (LLM: sdf)\nUsage: my $status = read_sdf(@options, @files);\n@files: SDF files, can be in gzip format\n\n$status: If zero, the files have been read in successfully\n         if non-zero, failed to read in the files\n\nExamples:\n#1. Read in slow corner top level SDF file for design TM_QCIF\nread_sdf(\"TM_QCIF_slow.sdf.gz\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_sub_module_netlist.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_sub_module_netlist.txt", "chroma:document": "read_sub_module_netlist\nRead in new synthesized netlist file\nUsage: read_sub_module_netlist($sub_module_file, @options);\n$sub_module_file: Netlist file name\n@options:\n    -sub_only: The netlist is one module file, it may have sub-instances as black boxes\n    -module module_name: The sub-module name in the original top netlist to be replaced\n    -syn_module syn_module_name: The sub-module name in the new synthesized netlist\n    -suffix suffix_name: Add suffix string to all modules in the module_name defined in 'module' option\n\nExamples:\n\n#1. Reads in mem_controller module and its sub-modules, ahb_arb module and its sub-modules, and mem_ahb_top module only\n\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller\");\nread_sub_module_netlist(\"new_ahb_arb.gv\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_ahb_top.v\", \"-module\", \"mem_ahb_top\", \"-sub_only\");\n\n#2. Reads in new synthesized netlist files, new_mem_controller.gv and new_ahb_arb.gv, and modified parent module new_mem_ahb_top.v.\n    The new sub-module netlist new_mem_controller.gv is to replace two uniquified modules in the original top netlist,\n    mem_controller_1 and mem_controller_2 and their hierarchical sub-modules.\n    The new sub-module netlist new_ahb_arg.gv is to replace ahb_arb and its hierarchical sub-modules in the original top netlist. \n    And the new modified new_mem_ahb_top.v is to replace the sub-parent module mem_ahb_top only.\n\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller_1\", \"-syn_module\", \"mem_controller\", \"-suffix\", \"_1\");\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller_2\", \"-syn_module\", \"mem_controller\", \"-suffix\", \"_2\");\nread_sub_module_netlist(\"new_ahb_arb.gv\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_ahb_top.v\", \"-module\", \"mem_ahb_top\", \"-sub_only\");\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_sub_module_svf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_sub_module_svf.txt", "chroma:document": "read_sub_module_svf\nRead in new synthesized design SVF file\nUsage: read_sub_module_svf($sub_module_svf, @options);\n$sub_module_svf: Sub-module SVF file name\n@options:\n    -module module_name: The sub-module name in the original top netlist that will be replaced\n    -syn_module syn_module_name: The sub-module name in the new synthesized netlist\n    -suffix suffix_string: Add suffix to all modules under the module_name defined by 'module' option, s\nNotes: The command can be run several times\n\nExamples:\n\n#1. Reads in mem_controller module and its sub-modules, ahb_arb module and its sub-modules SVF files\nread_sub_module_svf(\"new_mem_controller.svf\", \"-module\", \"mem_controller_1\", \"-syn_module\", \"mem_controller\");\nread_sub_module_svf(\"new_ahb_arb.svf\", \"-module\", \"ahb_arb\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_svf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_svf.txt", "chroma:document": "read_svf\nRead  SVF text files (LLM: svf)\nUsage: my $status = read_svf(@options, @files);\n@files: SVF text files\n@options:\n    -imp: The SVF file is for the Implementation netlist\n    -ref: The SVF file is for the Reference Netlist\n    -Top_1: The SVF file is for Top_1 tree database\n    -Top_2: The SVF file is for Top_2 tree database\n\n$status: If zero, the files have been read in successfully\n         if non-zero, failed to read in the files\n\nNote: This command must be run before read_design \n      SVF should be in text format\n\nExamples:\n#1. Read in both SVF files for IMP/REF\nread_svf(\"-ref\", \"ref_design.svf.txt\");\nread_svf(\"-imp\", \"imp_design.svf.txt\");\nread_design(\"-ref\", \"ref_design.v\");\nread_design(\"-imp\", \"imp_design.v\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_read_vcd.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.read_vcd.txt", "chroma:document": "read_vcd\nRead VCD file\nUsage: read_vcd($vcd_file);\n$vcd_file: VCD file name to be read in\n\nExamples:\n\n#1. Read in VCD generated in verify_faults\nread_vcd(\"fault_seu.vcd\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_rename_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.rename_net.txt", "chroma:document": "rename_net\nECO command. Rename a net name\nUsage: rename_net($oldname, $newname);\n$oldname: Old net name\n$newname: New net name\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_replace_sub_module_netlist.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.replace_sub_module_netlist.txt", "chroma:document": "replace_sub_module_netlist\nReplace sub-module in the design by a new re-synthesized sub-module netlist and write to a new top netlist\nUsage: replace_sub_module_netlist($new_top_netlist_file);\n$new_top_netlist_file: The replaced and new top level full netlist to be written out\n\nExamples:\n\n#1. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically, and 'mem_ahb_top' module, and write out to a new full netlist\nread_library(\"tsmc.lib\");\nread_design(\"-imp\", \"top_ref.gv\");\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller\");\nread_sub_module_netlist(\"new_ahb_arb.gv\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_ahb_top.v\", \"-module\", \"mem_ahb_top\", \"-sub_only\");\nreplace_sub_module_netlist(\"new_top_ref.gv\");\n\n\n#2. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically in netlist and SVF, replace 'mem_ahb_top' module only,\n    and write out to a new full SVF file and a new netlist\n\nread_library(\"tsmc.lib\");\nread_svf(\"-imp\", \"top_ref.svf\");\nread_design(\"-imp\", \"top_ref.gv\");\nread_sub_module_svf(\"new_mem_controller.svf\", \"-module\", \"mem_controller\");\nread_sub_module_svf(\"new_ahb_arb.svf\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller\");\nread_sub_module_netlist(\"new_ahb_arb.gv\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_ahb_top.v\", \"-module\", \"mem_ahb_top\", \"-sub_only\"); # This module is parent module with instantiation only\n\nreplace_sub_module_netlist(\"new_top_ref.gv\"); # Run netlist replacement first \nreplace_sub_module_svf(\"new_top_ref.svf\");    # Then SVF replacement\n\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_replace_sub_module_svf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.replace_sub_module_svf.txt", "chroma:document": "replace_sub_module_svf\nReplace sub-module SVF in the design by a new re-synthesized sub-module SVF file content\nUsage: replace_sub_module_svf($new_top_design_svf);\n$new_top_design_svf: The replaced and new top level full SVF file to be written out\n\nExamples:\n\n#1. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically in netlist and SVF, replace 'mem_ahb_top' module only,\n    and write out to a new full SVF file and a new netlist\n\nread_library(\"tsmc.lib\");\nread_svf(\"-imp\", \"top_ref.svf\");\nread_design(\"-imp\", \"top_ref.gv\");\nread_sub_module_svf(\"new_mem_controller.svf\", \"-module\", \"mem_controller\");\nread_sub_module_svf(\"new_ahb_arb.svf\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_controller.gv\", \"-module\", \"mem_controller\");\nread_sub_module_netlist(\"new_ahb_arb.gv\", \"-module\", \"ahb_arb\");\nread_sub_module_netlist(\"new_mem_ahb_top.v\", \"-module\", \"mem_ahb_top\", \"-sub_only\"); # This module is parent module with instantiation only\n\nreplace_sub_module_netlist(\"new_top_ref.gv\"); # Run netlist replacement first \nreplace_sub_module_svf(\"new_top_ref.svf\");    # Then SVF replacement\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_report_eco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.report_eco.txt", "chroma:document": "report_eco\nReport ECO\nUsage: report_eco($filename, @options);\n$filename: Write report to the file name. If $filename is not present, print to screen\n@options:\n    -help: Print this information\n    -simple: Print in simple format\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_report_spares.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.report_spares.txt", "chroma:document": "report_spares\nReport Spare cells\nUsage: report_spares;\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_report_timing.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.report_timing.txt", "chroma:document": "report_timing\nTiming command. Report timing\nUsage: report_timing(@options);\n@options:\n    -help: Prints this information\n    -delay_type $delay_type: Specifies the type of path delay: max (default) or min\n    -from: $startpoint, Starting point of the timing report\n    -to:   $endpoint, Ending point of the timing report\n    -through: $through_points, Through points, the value can be an array point\n    -thr_and: Through points should all present \n    -max_paths number: Max path number to report, if it is not set, only report one path\n    -all: Reports all timing paths\n    -input_pins: Displays input pins of instances\n    -nosplit: Prevents line splitting\nNote: If none of the 'from' or 'to' or 'through' option is present, the timing report is on the paths that go through the ECO instances\n\nExamples:\n\n#1. Report timing on the paths that go through the ECO instances\nreport_timing();\n\n#2. Report timing on the instances that in through option\nmy $thr_instances = [\"u_control/u_clk/U120\", \"u_control/u_mbist/U117\"];\nreport_timing(\"-through\", $thr_instances);\n\n#3. Report timing on the instances that in through option and they should all appear in the report path\nmy $thr_instances = [\"u_control/u_clk/U120\", \"u_control/u_mbist/U117\"];\nreport_timing(\"-through\", $thr_instances, \"-thr_and\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_restore_session.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.restore_session.txt", "chroma:document": "restore_session\nRestore ECO session\nUsage: restore_session(\"$directory/$session_name\");\n$directory: The directory that the session has been saved\n$session_name: The session name\n\nExamples:\n\n# To restore the session \"myeco\" in sub-directory \"mach_ai\"\nrestore_session(\"mach_ai/myeco\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_rtl_compare.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.rtl_compare.txt", "chroma:document": "rtl_compare\nRTL to RTL compare\nThe compare result is used in fix_design, so that Gate to Gate comparing can be skipped\nUsage: rtl_compare(@options);\n@options:\n   \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_run.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.run.txt", "chroma:document": "run\nRun Netlist processing script\nUsage: run($script_name);\n\nExamples:\n\nrun(\"eco2.pl\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_run_lec.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.run_lec.txt", "chroma:document": "run_lec\nRun Logic Equivalence Check of the Implementation Netlist vs the Reference Netlist (LLM: lec)\nUsage: run_lec(@options);\n@options:\n    -list_file the_list_file: The LEC point list file \n             The list file format:\n                inst: u_def/u_sdef/state_reg_1_\n                pin:  u_control/u_sreg/u_mem_128x24/A[0]\n                port: PORT_READY_OUT\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_save_session.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.save_session.txt", "chroma:document": "save_session\nSave ECO session\nUsage: save_session(\"$directory/$session_name\");\n$directory: The directory that the session should be saved\n$session_name: The session name\n\nExamples:\n\n# To save a session \"my_eco\" in sub-directory \"mach_ai\"\nsave_session(\"mach_ai/my_eco\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_sch.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.sch.txt", "chroma:document": "sch\nLaunch schematic to verify ECO\nUsage: sch(@instances, @options);\n@instances: Instances or nets in the current module to be displayed on the schematic\n@options:\n    -set value: Set a value when launch the schematic\n    -to value: To existing schematic\n    -both: Load the item in both implementation and reference netlist\n\nExamples:\n\nsch(\"U123\", \"U456\", \"inst0\");\nsch(\"clk\")\nsch(\"in1\", \"-set\", \"1\");\nsch(\"in1\", \"-to\", \"1\"); # No action if schematic 1 doesn't exist\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_setup_eco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.setup_eco.txt", "chroma:document": "setup_eco\nECO command. Setup ECO\nUsage: setup_eco($eco_name, @options);\n$eco_name: ECO name, like eco01234\n@options:\n    -help: Print this information.\n    -comments comments: Comments to appear at the beginning of ECO netlist.\n\nExamples:\n\n#1. Setup ECO name \nsetup_eco('eco1234')\n\n#2. Setup ECO name with comments\nsetup_eco('eco1234', '-comments', 'Fix abc_state state machine');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_auto_fix_floating.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_auto_fix_floating.txt", "chroma:document": "set_auto_fix_floating\nECO setting. Enable automatic fixing floating input ports after fix_modules\nBy default, it is enabled.\nUsage: set_auto_fix_floating(0);  --- Disable automatic fixing floating input ports.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_bfix.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_bfix.txt", "chroma:document": "set_bfix\nEnable or disable BFIX features which is for precise combinational logic fix (LLM: precise combinational) \nUsage: set_bfix($val);\n$val: Default 0x3\n      Bit 0, Set one to enable Reorder Method\n      Bit 1, Set one to enable Cutpoint Method\n      bit 2, Set one to force using Reorder/Cutpoint Method instead of Structure Method\n\nNote: It should run before fix_design\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_blackbox.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_blackbox.txt", "chroma:document": "set_blackbox\nSet Blackbox on Modules\nUsage: set_blackbox(@modules, @options);\n@module: Module names to be set as blackbox, accept wild card '*'\n@options:\n   -hier: Set blackbox on the module and its sub-hierarchical modules\n          Only valid on module name without '*'\n\nNote: This command can be used multiple times\n\nExamples:\n\n#1. Set Blackbox on DW modules\nset_blackbox(\"*DW_pipe*\");\n\n#2. Set Blackbox on 'ABC' and 'DEF' modules\nset_blackbox(\"ABC\", \"DEF\");\n\n#3. Set Blackbox on memory_control and its sub-hierarchical modules. Set Blackbox on one DW as well\nset_blackbox(\"memory_control\", \"-hier\");\nset_blackbox(\"DW_adder_123\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_bound_opti.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_bound_opti.txt", "chroma:document": "set_bound_opti\nSet boundary optimization checking \nUsage: set_bound_opti($val);\n$val: 0, disable boundary optimization checking\n      1, enable boundary optimization checking (default)\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_buffer.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_buffer.txt", "chroma:document": "set_buffer\nSet buffer type. The tool automatically picks one if the command is not called (LLM: buffer name)\nUsage: set_buffer($buffer);\n$buffer: Lib cell name for buffer\n\nExamples:\n\nset_buffer(\"BUFX2\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_buffer_distance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_buffer_distance.txt", "chroma:document": "set_buffer_distance\nSet distance limit for inserting buffer\nUsage: set_buffer_distance($distance_val);\n$distance_val: distance to insert buffer, in um\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_clock_uncertainty.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_clock_uncertainty.txt", "chroma:document": "set_clock_uncertainty\nTiming command. Set clock uncertainty\nUsage: set_clock_uncertainty($value);\n$value: Uncertainty value\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_cluster_command.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_cluster_command.txt", "chroma:document": "set_cluster_command\nSet cluster command in parallel fault verification\nUsage: set_cluster_command($cluster_command);\n$cluster_command: Command to submit jobs to cluster computers\n\nExamples:\n\n#1. Set cluster command \nset_cluster_command(\"bsub_lsf -queue\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_cluster_timeout.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_cluster_timeout.txt", "chroma:document": "set_cluster_timeout\nSet time out for cluster command\nUsage: set_cluster_timeout($time_in_seconds);\n$time_in_seconds: An integer number in seconds\n\nNote: cluster time out number should be large than solver time out\n\nExamples:\n\n#1. Set solver time out to ~12 hours\nset_cluster_timeout(43200);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_constraints.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_constraints.txt", "chroma:document": "set_constraints\nSet constraints for map_spare_cells command\nUsage: set_constraints(@options);\n@options:;\n   -type type_constraint : Set spare cell type constraint, type_constraint is a string \n                           listing spare cells separated by ',', get_spare_cells should not be used if -type is present\n   -num num_constraint   : Set spare cell number constraint, num_constraint is a string \n                           in the format of 'mux<16,nand<18'\n   -type_limit limit_string : Set cell type limit to be less than a number, for example A9TR type less than 10, 'A9TR<10'\n                             All constraints is separated by ',' in the format of 'X8B<9,X0P5A<1'\nNote: The number constraint only controls the number of spare types to be used. The spare gates list should have \n      'nand/and', 'nor/or' and 'inv' types of leaf cells for synthesis mapping, and have spare flops for direct mapping, 'mux' is optional. \n      If used with get_spare_cells command, this command should be used after get_spare_cells, check example #3 \n\nExamples:\n\n#1. Use less than 16 'mux' and less than 18 'nand' spare gates in map_spare_cells\nget_spare_cells(\"u_Spare*/*spr_gate*\");\nset_constraints('-num', 'mux<16,nand<18');\nmap_spare_cells;\n\n\n#2. Use NAD2X1 NOR2X1 INVX1 and MUX2X1 as spare type gates\nset_constraints('-type', 'NAND2X1,NOR2X1,INVX1,MUX2X1');\nmap_spare_cells;\n\n#3. Set constraint after spare list created \nget_spare_cells(\"u_Spare*/*spr_gate*\");\nset_constraints('-num', 'and<1'); # So that no AND spare gate will be used\nmap_spare_cells;\n\n#4. Set type limit after spare list created\nget_spare_cells(\"u_Spare*/*spr_gate*\");\nset_constraints('-type_limit', 'ULVT<5,ELVT<6'); \nmap_spare_cells;\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_cutpoint_thresh.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_cutpoint_thresh.txt", "chroma:document": "set_cutpoint_thresh\nSet Cutpoint Threshold\nUsage: set_cutpoint_thresh($val);\n$val: Threshold value, default 100 \n     "}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_cutpoint_ultra.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_cutpoint_ultra.txt", "chroma:document": "set_cutpoint_ultra\nSet the level in doing CutPoint Ultra (LLM: cutpoint ultra)\nUsage: set_cutpoint_ultra($val);\n$val: 0, Disable cutpoint ultra\n      1, Enable cutpoint ultra (default)\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_define.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_define.txt", "chroma:document": "set_define\nSet define (LLM: define variable)\nUsage: set_define($define, $value, @options);\n@options:\n    -imp: The define is for Implementation only\n    -ref: The define is for Reference only\n$define: The define item\n$value: The value, optional\n\nExamples:\n\n#1. Set define SYNTHESIS for both netlists\nset_define(\"SYNTHESIS\");\n\n#2. Set define NO_DFT_LOGIC for Reference only\nset_define(\"NO_DFT_LOGIC\", \"-ref\");\n\n#3. Set define SIMULATION to 0\nset_define(\"SIMULATION\", 0);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_detect_points.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_detect_points.txt", "chroma:document": "set_detect_points\nset detect points\nUsage: set_detect_points(@points, @options);\n@points: Detect points \n@options:\n   -help: Print this info\n\nNote: The command can be run multiple times\n\nExamples:\n\n#1. Set data_error_ml as detect points\nset_detect_points(\"data_error_ml\");\n\n#2. Set data_error_ml and u_cpu/err_det_reg as detect points\nset_detect_points(\"data_error_ml\");\nset_detect_points(\"u_cpu/err_det_reg\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_disable_cross_hierarchy_merge.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_disable_cross_hierarchy_merge.txt", "chroma:document": "set_disable_cross_hierarchy_merge\nSet this variable to disable cross hierarchy register merging\nUsage: set_disable_cross_hierarchy_merge($value);\n$value: 0, disable\n        1, enable. Default\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_disable_lib_cache.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_disable_lib_cache.txt", "chroma:document": "set_disable_lib_cache\nDisable liberty file cache\nUsage: set_disable_lib_cache($value);\n$value: 0, enable liberty file cache (default)\n        1, disable liberty file cache\n   \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_dont_fix_modules.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_dont_fix_modules.txt", "chroma:document": "set_dont_fix_modules\nSet dont fix property on modules\nUsage: set_dont_fix_modules(@modules);\n@module: Module names not to be fixed\n\nExample:\n\n#1. Set dont fix on pcie_ctrl and pcie_top module\nset_dont_fix_modules(\"pcie_ctrl\", \"pcie_top\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_dont_use.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_dont_use.txt", "chroma:document": "set_dont_use\nSet dont use property on library cells\nUsage: set_dont_use(@cell_list);\n@cell_list: List of the dont use cells which is not used in automatic ECO. Wild card '*' is supported\n\nNote: If the command is used multiple times, the latest command overrides the previous ones\n\nExamples:\n\n#1. Don't use these two cells\nset_dont_use(\"INVX30\",\"AND2X24\");\n\n#2. Don't use power cell matching PWR_\nset_dont_use(\"PWR_*\");\n\n#2. If run two times, the second one has effect, set dont use on \"CINV_*\"\nset_dont_use(\"SINV_*\");\nset_dont_use(\"CINV_*\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_eco_effort.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_eco_effort.txt", "chroma:document": "set_eco_effort\nECO setting. Set ECO effort\nUsage: set_eco_effort($effort);\n$effort: One of the three choices, high, medium and low. By default, high effort is used\n\nExamples:\n\n#1. Change ECO effort to medium\nset_eco_effort(\"medium\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_eco_point_json.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_eco_point_json.txt", "chroma:document": "set_eco_point_json\nSet a JSON file name for saving the ECO point data. \nThe JSON file can be applied to another netlist ECO, so that the full LEC has no need to be rerun\nUsage: set_eco_point_json($json_name);\n$json_name: The JSON file name\n\nNote: This command should be run before fix_design\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_equal.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_equal.txt", "chroma:document": "set_equal\nECO setting. Set two points to be equivalent in the Reference and Implementation Netlists\n             The points can be input port, flop instance or output pin of black-box.\n             The point names should have 'i:' or 'r:' as prefix to indicate they are for the Reference or Implementation, or\n             the first point is assumed as Reference and the second Implementation.\n             Both of the points can be from Reference or Implementation\nUsage: set_equal($ref_point, $imp_point);\n$ref_point: The point in the Reference Netlist. It should be the first argument if it doesn't have 'i:' or 'r:' as prefix\n$imp_point: The point in the Implementation Netlist. It should be the second argument if it doesn't have 'i:' or 'r:' as prefix\n\nExamples:\n\n#1. Input port 'in_a' in Reference Netlist is equivalent to input port 'in_b' in Implementation Netlist in top module\nset_top('top_module');\nset_equal('r:in_a', 'i:in_b');\n \n#2. Flop instance 'subinst/flopa_reg' is equivalent to input port 'IN0' in the Implementation Netlist\nset_top('top_module');\nset_equal('i:subinst/flopa_reg', 'i:IN0');\nfix_design();\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_error_out.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_error_out.txt", "chroma:document": "set_error_out\nSet error out setting\nUsage: set_error_out($value);\n$value: 1, Abort the program when APIs have run error, default setting\n        0, Ignore the error and continue the program\n\nExamples:\n\n# Program continues when there is error in change_pin\nset_error_out(0);\nchange_pin(\"nonexisting_instance/A\", \"1'b0\"); # It will continue, even though nonexisting_instance is not in the database\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_exit_on_error.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_exit_on_error.txt", "chroma:document": "set_exit_on_error\nWhether the tool should exit when the script runs into an error\nUsage: set_exit_on_error($error, $bit);\n$error: Error pattern, wild card support. 'E-001', 'E-*'\n$bit: 1, Exit on the error, default\n      0, Don't exit on the error\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_exit_on_warning.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_exit_on_warning.txt", "chroma:document": "set_exit_on_warning\nWhether the tool should exit when the script runs into a warning\nUsage: set_exit_on_warning($warning, $bit);\n$warning: Warning pattern, wild card support. 'W-001', 'W-*'\n$bit: 1, Exit on the warning\n      0, Don't exit on the warning, default\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_false_path.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_false_path.txt", "chroma:document": "set_false_path\nTiming command. Set false path\nUsage: set_false_path(@options);\n@options:\n    -help: Print this information\n    -from: $startpoint, set false path on the starting point\n    -to:   $endpoint, set false path on the ending point\n    -through: $through_point, set false path on the through point\n\nExamples:\n\n#1. Set false path on u_control/u_subsm/state_reg_* as from points\nset_false_path(\"-from\", \"u_control/u_subsm/state_reg_*\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_floating_as_zero.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_floating_as_zero.txt", "chroma:document": "set_floating_as_zero\nSet floating net as constant zero (LLM: floating zero)\nUsage: set_floating_as_zero($value);\n$value: 0, disable floating net as constant zero\n        1, enable floating net as constant zero (default)\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_flop_default_eco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_flop_default_eco.txt", "chroma:document": "set_flop_default_eco\nSet flop default eco by inverting input pin and output pin\nUsage: set_flop_default_eco($value);\n$value: 1 to enable flop default eco by inverting input pin and output pin\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_flop_merge_enable.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_flop_merge_enable.txt", "chroma:document": "set_flop_merge_enable\nInside module flop merge enable\nUsage: set_flop_merge_enable($setting,@options);\n$setting: 0, disable inside module flop merge \n          1, enable inside module flop merge (default)\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_high_effort.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_high_effort.txt", "chroma:document": "set_high_effort\nSet high ECO effort on modules (LLM: effort high)\nUsage: set_high_effort(@options);\n@options:\n    -help: Print this information\n    -include module_list: Only set high ECO effort on the modules listed,\n                         module_list has format of module names separated by ',', wild card is acceptable\n                         For example, 'mem_control,dma_*'\n    -exclude module_list: Exclude high ECO effort on the modules listed\n                         module_list has format of module names separated by ',', wild card is acceptable\n                         For example, 'mem_control,dma_*'\n    -timeout time_in_seconds: Set time out for each run, default to time out in 900 seconds\n                         time_in_seconds is an integer indicating time out in seconds\n\nExamples:\n\n#1. Set ECO high effort on all modules under ECO\nset_high_effort();\n\n#2. Set ECO high effort on module 'mem_control_1'\nset_high_effort('-include', 'mem_control_1');\n\n#3. Set ECO high effort on modules matching 'mem_control_*' and modules matching 'dma_*'\nset_high_effort('-include', 'mem_control_*,dma_*');\n\n#4. Enable ECO high effort, but excluding module 'mem_control_1  '\nset_high_effort('-exclude', 'mem_control_1');\n\n#5. Enable ECO high effort with time out in 600 seconds\nset_high_effort('-timeout', 600);\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_ignore_instance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_ignore_instance.txt", "chroma:document": "set_ignore_instance\nECO setting. Set ignored sequential or blackbox instances in ECO\nUsage: set_ignore_instnace(@ignored_instances)\n@ignored_instances: Instances to be ignored in ECO, accept wild card '*'\n\nExamples:\n \n#1. Ignore instances matching RAND_CNT_reg* in ECO\nset_top('VIDEO_TOP');\nset_ignore_instance('RAND_CNT_reg*');\nset_top('DESIGN_TOP');\nfix_design();\n\n#2. Ignore instances matching current_state_reg* in instance u_video\nset_top('DESIGN_TOP');\nset_ignore_instance('u_video/current_state_reg*');\nfix_design();\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_ignore_network.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_ignore_network.txt", "chroma:document": "set_ignore_network\nECO setting. Set ignore network in ECO\nUsage: set_ignore_network(@ignored_nets, @options)\n@ignored_nets: Net and its network to be ignored in ECO, accept wild card '*'\n@options:\n   -help: Print this information\n   -pin:  @ignored_nets are in pin format, for example, 'DONT_mux_clk/PIN_Y'\n\nExamples:\n\n#1. Ignore scan_en and scan_in\nset_ignore_network('scan_en*', 'scan_in*'); \n\n#2. Ignore PAD PAD_SCAN_EN's output pin 'core' and its network\nset_ignore_network('PAD_SCAN_EN/core', '-pin'); \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_ignore_output.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_ignore_output.txt", "chroma:document": "set_ignore_output\nECO setting. Set ignore output ports\nUsage: set_ignore_output(@ignored_ports, @options)\n@ignored_ports: Output ports to be ignored, accept wild card '*'\n@options:\n   -help: Print this information\n   -both: Apply to both Reference and Implementation Netlist. Enabled by default\n   -ref:  Apply to Reference Netlist\n   -imp:  Apply to Implementation Netlist\n \nExamples:\n\n#1. Ignore output ports matching *scan_out* in ECO\nset_top('design_top');\nset_ignore_output('*scan_out*');\nset_pin_constant('scan_en', 0);\nfix_design();\n\n#2. Ignore output ports matching *TSTCON* in Implementation Netlist\nset_top('CHIP_TOP');\nset_ignore_output('*TSTCON*', '-imp');\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_ignore_pin.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_ignore_pin.txt", "chroma:document": "set_ignore_pin\nset ignore on the pin of black box like memory in logic equivalence checking (LLM: ignore black box pin)\nUsage: set_ignore_pin(\"$cell_name/$pin_name\");\n$cell_name: The black box cell name (Not instance name)\n$pin_name: The cell pin name, wildcard is supported, for example \"TM*\" to match TM[0] TM[1] ...\n\nExamples:\nset_ignore_pin(\"TSMC_MEM_256X29/TCEN\");\nset_ignore_pin(\"TSMC_MEM_256X29/TA*\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_inc_dirs.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_inc_dirs.txt", "chroma:document": "set_inc_dirs\nSet include directories\nUsage: set_inc_dirs(@include_directory_list, @options);\n@options:\n    -imp: The include directories are for Implementation only\n    -ref: The include directories are for Reference only\n@include_directory_list: List of all include directories\n\nExamples:\n\n#1. Set include directories for Reference only\nset_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\", \"-ref\");\n\n#2. Set include directories for Implementation only\nset_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\", \"-imp\");\n\n#3. Set include directories for both\nset_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_initial_trans.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_initial_trans.txt", "chroma:document": "set_initial_trans\nTiming command. Set initial transition for clock\nUsage: set_initial_trans($value);\n$value: Transition value\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_input_delay.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_input_delay.txt", "chroma:document": "set_input_delay\nTiming command. Set input delay\nUsage: set_input_delay($port_name, $delay_value, @options);\n@options:\n    -clock clock_name: Specifies the clock that relates to the delay\n$port_name: Input port name, accept wild card '*'\n$delay_value: Delay value in ns\n\nExamples:\n\n#1. Set input port to all APB bus input\nset_input_delay(\"port_apb_*\"\", 0.1);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_input_transition.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_input_transition.txt", "chroma:document": "set_input_transition\nTiming command. Set input transition to all input ports\nUsage: set_input_transition($value);\n$value: Transition value\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_inside_mod.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_inside_mod.txt", "chroma:document": "set_inside_mod\nSet fix scope inside the current module\nIf set to 1, the tool only use resource inside the current module to fix the non-eq points.\nBy default, it is disabled.\nUsage: set_inside_mod($val);\n$val: 0, disable 1, enable\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_inst.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_inst.txt", "chroma:document": "set_inst\nSet the current instance, alias of 'current_instance'\nUsage: set_inst($instance);\n$instance: Set $instance as the current instance.\n         If the argument is missing, return the current setting\n         \"..\" set to parent, \"~\" set to the most top level module \nNote: It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_inv.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_inv.txt", "chroma:document": "set_inv\nECO setting. Set two points to be inverted in the Reference and Implementation Netlists\n             The points can be input port, flop instance or black-box's output pin.\n             The point names should have 'i:' or 'r:' as prefix to indicate they are for Reference or Implementation, or\n             the first point is assumed as Reference and the second Implementation.\n             Both of the points can be from Reference or Implementation by using 'i:' or 'r:' on both point names.\nUsage: set_inv($ref_point, $imp_point);\n$ref_point: The point in the Reference Netlist. It should be the first argument if it doesn't have 'i:' or 'r:' as prefix\n$imp_point: The point in the Implementation Netlist. It should be the second argument if it doesn't have 'i:' or 'r:' as prefix\n\nExamples:\n\n#1. Input port 'in_a' in the Reference Netlist is inverted to input port 'in_a_BAR' in the Implementation Netlist in top module\nset_top('top_module');\nset_inv('r:in_a', 'i:in_a_BAR');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_invert.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_invert.txt", "chroma:document": "set_invert\nSet invert type. The tool automatically picks one if the command is not called (LLM: invert name)\nUsage: set_invert($invert);\n$invert: Lib cell name for invert\n\nExamples:\n\nset_invert(\"INVX2\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_keep_format.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_keep_format.txt", "chroma:document": "set_keep_format\nKeep the format of the original verilog when ECO is done (Keep original netlist format)\nUsage: set_keep_format($value);\n$value: 0, disable format keeping (default)\n        1, enable format keeping.\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_keep_tree.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_keep_tree.txt", "chroma:document": "set_keep_tree\nSet keeping buffer tree, so that buffer tree won't be removed in ECO\nBy default , it is disabled.\nUsage: set_keep_tree($val);\n$val: 0, disable 1, enable\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_keypoints_rep_in_ref.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_keypoints_rep_in_ref.txt", "chroma:document": "set_keypoints_rep_in_ref\nECO setting. Replace keypoints naming in Reference Netlist.\nKeypoints naming matching the first argument, and replace the matched string by the second argument\nUsage: set_keypoints_rep_in_ref($match_string, $rep_string);\n$match_string: Keypoints naming matching this string\n$rep_string: To replace the matched string by this string\n\nNote: The command only apply to Reference Netlist\n\nExamples:\n\n#1. Replace the last '_' in Keypoints naming in Reference Netlist\nset_keypoints_rep_in_ref('_$', '');\n\n#2. Replace the last '0' in Keypoints naming in Reference Netlist\nset_keypoints_rep_in_ref('0$', '');\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_leaf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_leaf.txt", "chroma:document": "set_leaf\nSet a hierarchical module to be leaf. Useful to stub hierarchical instances\nUsage: set_leaf($module_name, $value);\n$module_name: The module to be set leaf or not set to leaf\n$value: 1 or larger than 1, set the module as leaf. 0 not set to leaf. \n        If $value is not present, the default value is 1.\n\nExamples:\n\nset_leaf($module_a); # set $module_a as a leaf\nset_leaf($module_a, 1); # same as the above\nset_leaf($module_a, 0); # remove the leaf setting\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_log_file.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_log_file.txt", "chroma:document": "set_log_file\nSet log file name\nUsage: set_log_file($filename);\n$filename: Log file name\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_low_effort.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_low_effort.txt", "chroma:document": "set_low_effort\nSet low ECO effort to speed up ECO process (LLM: speed up)\nUsage: set_low_effort(@options);\n@options:\n    -help: Print this information\n\nExamples:\n\n#1. Set ECO low effort on all modules under ECO\nset_low_effort();\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_mapped_point.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_mapped_point.txt", "chroma:document": "set_mapped_point\nECO setting. Set two points mapped in Reference and Implementation Netlists\nUsage: set_mapped_point($ref_point, $imp_point, @options);\n$ref_point: Register instance or output port in Reference Netlist\n$imp_point: Register instance or output port in Implementation Netlist\n@options:\n    -invert: The two points are expected to be inverted\n\nExamples:\n\n#1. Two outputs are mapped key points\nset_mapped_point(\"ref_sync\", \"imp_sync\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_mapping_method.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_mapping_method.txt", "chroma:document": "set_mapping_method\nLEC setting. Detecting flop phase inversion.\nUsage: set_mapping_method(\"-phase\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_max_lines.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_max_lines.txt", "chroma:document": "set_max_lines\nSet max output lines\nUsage: set_max_lines($num);\n$num: New max lines number. Default to be 500\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_max_loop.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_max_loop.txt", "chroma:document": "set_max_loop\nSetup max loop, the tool stops logic optimization when max loop number is reached\nUsage: set_max_loop($value);\n\n$value: Setup BDD threshold, default 40000\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_mod2mod.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_mod2mod.txt", "chroma:document": "set_mod2mod\nSet reference module mapping to implementation module\nUsage: set_mod2mod($refmod, $impmod);\n$refmod: The reference module name\n$impmod: The implementation module name\nNote: \n  The command is used when reference netlist is partial\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_mu.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_mu.txt", "chroma:document": "set_mu\nMU configuration, setup MU value for BDD threshold\nUsage: set_mu($value);\n$value: Setup BDD threshold, default 12000\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_multibit_blasting.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_multibit_blasting.txt", "chroma:document": "set_multibit_blasting\nSet blasting on multibit flops \nset_multibit_blasting($enable);\n$enable: 0, disable multibit flop blasting\n         1, enable multibit flop blasting (default)\nNote: This command should run before read_design\n\nExamples:\n\nset_multibit_blasting(1);\nread_design(\"-ref\", \"ref.v\");\nread_design(\"-imp\", \"imp.v\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_multibit_output.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_multibit_output.txt", "chroma:document": "set_multibit_output\nSet multibit flops output in ECO results \nset_multibit_output($enable);\n$enable: 0, disable multibit flops output (default)\n         1, enable multibit flops output \n\nExamples:\n\nset_multibit_output(1);\nwrite_verilog(\"eco_result.v\");\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_net_constant.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_net_constant.txt", "chroma:document": "set_net_constant\nSet net to a constant value in DFT constraint (LLM: constant)\nUsage: set_net_constant($net, $value, @options);\n$net: Net name. It can be a bus.\n$value: Decimal value that the pin should be set\n@options:\n    -help: Print this information\n    -both: Set the net to the constant value on both Implementation and Reference. Enabled by default.\n    -imp:  Set the net to the constant only on Implementation\n    -ref:  Set the net to the constant only on Reference\n\nExamples:\n\n#1. Set all_test net to zero in Implementation Netlist\nset_top('DESIGN_TOP_DFT_WRAPPER');\nset_net_constant('all_test', 0, '-imp');\nset_ignore_output('PIN_EDT_CHANNEL_OUT*', '-imp');\nfix_design();\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_noexact_pin_match.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_noexact_pin_match.txt", "chroma:document": "set_noexact_pin_match\nECO setting. Don't match some special pins\nThese pins normally don't exist in RTL but added by Synthesis, DFT or other tools.\nUsage: set_noexact_pin_match($pattern);\n$pattern: Pin pattern in regular expression, '\\bIN\\d+\\b'\n\nNote: The command only apply to Reference Netlist. It should be run before reading reference netlist\n\nExamples:\n\n#1. Don't match pins like IN0, IN1, IN2\nset_noexact_pin_match('\\bIN\\d+\\b');\nread_design('-ref', 'ref_netlist.v');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_no_patch_opt.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_no_patch_opt.txt", "chroma:document": "set_no_patch_opt\nDisable patch optimization\nUsage: set_no_patch_opt($value);\n$value: 0, Enable patch optimization in fix_design (default).\n        1, Disable patch optimization in fix_design \n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_observe_points.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_observe_points.txt", "chroma:document": "set_observe_points\nset observe points\nUsage: set_observe_points(@points, @options);\n@points: Observation points \n@options:\n   -help: Print this info\n   -comb: The points are input pins of combinational gates\n\nNote: The command can be run multiple times\n\nExamples:\n\n#1. Set data_out_ml bus as observe points\nset_observe_points(\"data_out_ml*\");\n\n#2. Set data_out_ml bus and u_cpu/valid_status_regas observe points\nset_observe_points(\"data_out_ml*\");\nset_observe_points(\"u_cpu/valid_status_reg\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_one_fault.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_one_fault.txt", "chroma:document": "set_one_fault\nSet one fault for verify_state command\nUsage: set_one_fault($fault_name);\n$fault_name: Fault name \n\nExamples:\n\n#1. Set stuck-at 0 fault to a NAND gate input \nset_one_fault(\"u_top/u_ctrl/U123/A:SA0\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_only_use.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_only_use.txt", "chroma:document": "set_only_use\nIn optimize_patch, Only use these cells listed \nUsage: set_only_use(@cell_list);\n@cell_list: List of the cells that are used in optimize_patch. Wild card '*' is supported\n\nExamples:\n\n#1. Use these two cells\nset_only_use(\"INVX30\",\"AND2X24\");\n\n#2. Use any type of invert and nand gate\nset_only_use(\"INV*\", \"NAND*\");\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_output_delay.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_output_delay.txt", "chroma:document": "set_output_delay\nTiming command. Set output delay\nUsage: set_output_delay($port_name, $delay_value, @options);\n@options:\n    -clock clock_name: Specifies the clock that relates to the delay\n$port_name: Output port name, accept wild card '*'\n$delay_value: Delay value in ns\n\nExamples:\n\n#1. Set output delay to all memory output\nset_output_delay(\"mem_out_*\"\", 2.1);\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_output_load.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_output_load.txt", "chroma:document": "set_output_load\nTiming command. Set output load to all output ports\nUsage: set_output_load($value);\n$value: Output load value\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_phase_adjust_en.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_phase_adjust_en.txt", "chroma:document": "set_phase_adjust_en\nEnable phase adjusting (LLM: phase adjusting)\nUsage: set_phase_adjust_en($val);\n$val: 0, disable phase adjusting\n      1, enable phase adjusting (default)\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_phase_inv.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_phase_inv.txt", "chroma:document": "set_phase_inv\nECO setting. Set flops invert phase in the Reference and Implementation Netlists\nUsage: set_phase_inv($flop1, $flop2 ...);\n$flop1, $flop2: Flop instance list in full path\n\nExamples:\n\n#1. Set flop instance u_ip/u_control/a_reg to have invert phase\nset_top('top_module');\nset_phase_inv('u_ip/u_control/a_reg');\n\n#2. Set flop instances u_ip/u_control/a_reg and u_ip/u_control_b/b_reg to have invert phase\nset_top('top_module');\nset_phase_inv('u_ip/u_control/a_reg', 'u_ip/u_control_b/b_reg');\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_physical_aware.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_physical_aware.txt", "chroma:document": "set_physical_aware\nEnable physical aware ECO \nUsage: set_physical_aware($value);\n$value: 0, disable physical aware ECO \n        1, enable physical aware ECO (default)\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_pin_constant.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_pin_constant.txt", "chroma:document": "set_pin_constant\nSet pin to a constant value in DFT constraint (LLM: constant)\nUsage: set_pin_constant($pin, $value, @options);\n$pin: Input pin name. It can be a bus, or an instance pin.\n$value: Decimal value that the pin should be set\n@options:\n    -help: Print this information\n    -both: Set the pin to the constant value on both Implementation and Reference. Enabled by default.\n    -imp:  Set the pin to the constant only on Implementation\n    -ref:  Set the pin to the constant only on Reference\n\nExamples:\n\n#1. Set test scan test pin to zero\nset_top('DESING_TOP');\nset_pin_constant('PIN_SCAN_TEST', 0);\nset_ignore_output('PIN_SCAN_SO*');\nfix_design();\n\n#2. Set one bus port to all ones on Implementation\nset_top('DESING_TOP');\nset_pin_constant('PIN_CONTROL[3:0]', 15, '-imp');\nfix_design();\n\n"}


created_at: 2024-03-31 01:11:21
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_power.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_power.txt", "chroma:document": "set_power\nSet power pins connections for leaf cell\nUsage: set_power($leaf_cell, $connections);\n$leaf_cell: Leaf cell name. Like NAND2X4\n$connections: Power pins connections, like \".GND(GND),.VDD(VDD)\"\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_preserve.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_preserve.txt", "chroma:document": "set_preserve\nSet preserve property on instances. The tool does not remove them in ECO (LLM: preserve)\nUsage: set_preserve(@instances, @options);\n@options:\n   -hier: Set preserve globally, the specified instances will be preserved in all modules\n@instances: Instances to be preserved in the current module\n            Accept wild card '*'\n\nExamples:\n\n#1. Preserver two instances in mcu_top \npush_top(\"mcu_top\");\nset_preserve(\"u_donttouch0\", \"u_1000\");\npop_top;\n\n#2. Preserve all DONT* instances in abc_mod\npush_top(\"abc_mod\");\nset_preserve(\"DONT*\");\npop_top;\n\n#3. Preserve clock_tree_* instance in all modules, push_top/set_top are ignored\nset_preserve(\"clock_tree_*\", \"-hier\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_quiet.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_quiet.txt", "chroma:document": "set_quiet\nRun script in quiet mode\nUsage: set_quiet;\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_recovery_distance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_recovery_distance.txt", "chroma:document": "set_recovery_distance\nSet distance limit for gates recovery in ECO\nUsage: set_recovery_distance($distance);\n$distance: Distance to recover deleted gate, in unit of 'um'\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_remove_undsc_in_ref.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_remove_undsc_in_ref.txt", "chroma:document": "set_remove_undsc_in_ref\nECO setting. Remove last '_' in flop instance in Reference Netlist\nIt's a special command to remove the last '_' in flop instance in Reference Netlist \n   to match Implementation Netlist.\nUsage: set_remove_undsc_in_ref($value);\n$value: 1, enable. 0, disable\n\nNote: The command only apply to Reference Netlist\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_rtl_eco_full_hier_fan.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_rtl_eco_full_hier_fan.txt", "chroma:document": "set_rtl_eco_full_hier_fan\nRTL ECO has full hierarchical fanout\nUsage: set_rtl_eco_full_hier_fan($val);\n$value: 0, disable full hierarchical fanout (default)\n        1, enable full hierarchical fanout\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_save_mapped_instance.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_save_mapped_instance.txt", "chroma:document": "set_save_mapped_instance\nDump key points mapping information for LEC\nUsage: set_save_mapped_instance(1);\n\nNote: The command should be run before fix_design\n\nExample:\n\nset_save_mapped_instance(1);\nfix_design();\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_scan_pairs.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_scan_pairs.txt", "chroma:document": "set_scan_pairs\nSet scan output ports, the command is used with dft_drc\nUsage: set_scan_pairs(@scan_in_out_pairs);\n@scan_in_out_pairs: List of pairs of scan in and scan out pins\n\nNote: The command can run multiple times\n\nExamples:\n\n#1. Set all scan_si[100:0] scan_so[100:0] as scan in/out ports\nset_top(\"THE_DESIGN\");\nfor(my $i=0;$i<=100;$i++){\n  set_scan_pairs(\"scan_si[$i]\", \"scan_so[$i]\");\n}\nset_top(\"THE_DFT_TOP\"); # THE_DFT_TOP has THE_DESIGN as an instance\ndft_drc;\n\n#2. Check DFT DRC on a_scan_si[6]/a_scan_so[6] and b_scan_in[7]/b_scan_out[7]\nset_scan_pairs(\"a_scan_si[6]\", \"a_scan_so[6]\", \"b_scan_in[7]\", \"b_scan_out[7]\");\ndft_drc;\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_sn_vs_rn.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_sn_vs_rn.txt", "chroma:document": "set_sn_vs_rn\nCheck set pin and reset pin priority\nUsage: set_sn_vs_rn($val);\n$val: 1, Check set/reset pins priority, default\n      0, Don't check set/reset pins priority\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_solver_timeout.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_solver_timeout.txt", "chroma:document": "set_solver_timeout\nSet time out for solver\nUsage: set_solver_timeout($time_in_seconds);\n$time_in_seconds: An integer number in seconds\n\nExamples:\n\n#1. Set solver time out to ~10 hours\nset_solver_timeout(36000);\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_tiehi_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_tiehi_net.txt", "chroma:document": "set_tiehi_net\nSet tiehi net name, it is used if tiehi net is needed in ECO (LLM: tiehi)\nUsage: set_tiehi_net($netname);\n$netname: Tiehi net name, default to be 1'b1\n\nNote: If Tie High Cell is preferred, the value should be set to empty\n      set_tiehi_net(\"\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_tielo_net.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_tielo_net.txt", "chroma:document": "set_tielo_net\nSet tielo net name, it is used if tielo net is needed in ECO (LLM: tielo)\nUsage: set_tielo_net($netname);\n$netname: Tielo net name, default to be 1'b0\n\nNote: If Tie Low Cell is preferred, the value should be set to empty\n      set_tielo_net(\"\");\n\nExamples:\n\nset_tielo_net(\"___logic0___\"); \nset_tielo_net(\"TIE_HILO_TIELO_NET\");\nset_tielo_net(\"\"); # Use Tie Cell\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_time_frame_limit.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_time_frame_limit.txt", "chroma:document": "set_time_frame_limit\nGOF Formal only. Set limitation for time frame in fault verification, default 35\nUsage: set_time_frame_limit($frame_number);\n$frame_number: An integer number\n\nExamples:\n\n#1. Set time frame limit to 256\nset_time_frame_limit(256);\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_top.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_top.txt", "chroma:document": "set_top\nSet the current top level module (LLM: current top design)\nUsage: set_top($module);\n$module: Set $module as the current top level module.\n         If the argument is missing, return the current setting\n         \"..\" set to the parent module, \"~\" set to the most top level module \nNote: It can be reset to the root top module by 'undo_eco'\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_top_ref.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_top_ref.txt", "chroma:document": "set_top_ref\nSet the top level module for the Reference design (LLM: unmatched hierarchy reference)\nUsage set_top_ref($module);\nNotes:\nSet top module for the Reference Netlist due to unmatched hierarchy. \n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_tree.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_tree.txt", "chroma:document": "set_tree\nSet the current tree, if there are more than one sets of databases (LLM: tree)\nUsage: set_tree($tree);\n$tree: It can be Top, Top_ref, Top_1 or Top_2\n       Top: The Implementation Netlist\n       Top_ref: The Reference Netlist\n       Top_1: The netlist loaded by -Top_1 option\n       Top_2: The netlist loaded by -Top_2 option\n       If $tree is not defined, the current database name is returned\n\nNote: Implementation tree 'Top' has aliases of 'imp', 'IMP'\n      Reference tree 'Top_ref' has aliases of 'ref', 'REF'\n\nExamples:\n\nset_tree(\"Top\"); # Set to the Implementation Netlist tree\nset_tree(\"Top_ref\"); # Set to the Reference Netlist tree\nset_tree();  # Return the current database name. E.G. 'Top_ref'\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_user_match.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_user_match.txt", "chroma:document": "set_user_match\nSet match between multi-bit flops to multi-bit flops, and between multi-bit flops to single bit flop\nUsage: set_user_match($inst1, $inst2);\n$inst1: The first flop instance, in the format of 'r:reg_1_0A/\\*dff.00.0\\*' if it is multibit \n           or 'r:reg_1A' if it is single bit\n$inst2: The second flop instance, in the format of 'i:reg_1_0A/\\*dff.00.0\\*' if it is multibit \n           or 'i:reg_1A' if it is single bit\n\nExamples:\n\nset_user_match('r:reg_1_0A/\\*dff.00.0\\*', 'i:reg_0A');\nset_user_match('r:reg_1_0A/\\*dff.00.1\\*', 'i:reg_1A');\nset_user_match('r:reg_2_1A/\\*dff.00.1\\*', 'i:reg_1_0A/\\*dff.00.0\\*');\n\nNote: It is recommended to use SVF file, guide_multibit in SVF file has the same effect of this command\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_verbose.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_verbose.txt", "chroma:document": "set_verbose\nRun script in verbose mode\nUsage: set_verbose($num);\n$num: Verbose level, higher to be more verbose\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_wireload.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_wireload.txt", "chroma:document": "set_wireload\nCommand for Timing Report. Set wireload for one liberty library\nUsage: set_wireload($library, $wireload);\n$library: Library name\n$wireload: Wireload name\n\nExamples:\n\n#1. Set wireload for one library\nset_wireload(\"TMC18VGB15ELV16S_1P8V_25C\", \"zero-wire-load-model\");\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_write_verilog_remove_backslash.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_write_verilog_remove_backslash.txt", "chroma:document": "set_write_verilog_remove_backslash\nEnable write out verilog with backslash removal\nUsage: set_write_verilog_remove_backslash($value);\n$value: 0, Disable by default\n        1, Enable backslash removal in write_verilog\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_write_verilog_uniquify.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_write_verilog_uniquify.txt", "chroma:document": "set_write_verilog_uniquify\nEnable write out verilog in uniquified mode\nUsage: set_write_verilog_uniquify($value);\n$value: 0, Disable by default\n        1, Enable uniquify mode\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_set_xm_flop_merge_enable.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.set_xm_flop_merge_enable.txt", "chroma:document": "set_xm_flop_merge_enable\nCross module flop mapping and merging enable. \nUsage: set_xm_flop_merge_enable($setting,@options);\n$setting: 0, disable cross module flop merge (default)\n          1, enable cross module flop merge\n@options:\n   -parallel: Run merge process in parallel \nNote: Flop merge inside module command set_flop_merge_enable is enabled by default\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_source.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.source.txt", "chroma:document": "source\nRun Netlist processing script. \nUsage: source($script_name);\n\nExamples:\n\nsource(\"eco2.pl\");\n\nNote:\nIt has the same behavior as 'run' command\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_start_gui.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.start_gui.txt", "chroma:document": "start_gui\nStart GUI windows\nUsage: start_gui(@options);\n@options:\n   -source: Read in Reference RTL file if it exists\n   -noblock: The process is not blocked by start_gui, by default the process is blocked by the GUI window\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_stitch_scan_chain.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.stitch_scan_chain.txt", "chroma:document": "stitch_scan_chain\nECO command. Stitch scan chain\nUsage: stitch_scan_chain(@options);\n@options:\n   -to $flop_inst: Stitch all new flops into the flop_inst or stitch each module's new flops into one flop in this module \nNote: If -to option doesn't exist, the new flops in each module are connected up in one chain and stitched into one existing scan flop \n  \nExamples:\n\nstitch_scan_chain(\"-to\", \"abc_reg\"); # Insert new flops' scan chain into the existing flop 'abc_reg'\nstitch_scan_chain();                 # Stitch the new flops into local scan chains\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_suppress_errors.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.suppress_errors.txt", "chroma:document": "suppress_errors\nSuppress error messages\nUsage: suppress_errors(@messages)\n@messages: Error messages. 'E-001', 'E-132'\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_suppress_warnings.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.suppress_warnings.txt", "chroma:document": "suppress_warnings\nSuppress warning messages\nUsage: suppress_warnings(@messages)\n@messages: Warning messages. 'W-001', 'W-002'\n\nExamples:\n   suppress_warnings(\"W-001\", \"W-002\", \"W-003\"); # Suppress these three warnings\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_swap_inst.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.swap_inst.txt", "chroma:document": "swap_inst\nECO command. Swap two instances with same input/output pins.\nUsage: swap_inst($inst1, $inst2);\n$inst1,$inst2: Swap these two instances.\nNote: $inst1 and $inst2 should have the same input/output pins.\n\nExamples:\n\nswap_inst(\"spare1/spr_and0\", \"spare2/spr_and1\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_undo_eco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.undo_eco.txt", "chroma:document": "undo_eco\nECO command. Undo eco operations, restore the database to the original state.\nUsage: undo_eco();\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_verify_faults.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.verify_faults.txt", "chroma:document": "verify_faults\nGOF Formal only. Verify fault in stuck-0 or stuck-1 mode\nUsage: my $status = verify_faults($one_fault, @options);\n$one_fault: Optional, to test one fault only \n@options:\n   -help: Print this info\n   -rough: Calculate SPFM/LFM only by structural COI analysis\n   -full: Run full formal process in calculating SPFM/LFM\n   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined\n$status: Return 1 if a sequence exists\n\nExamples:\n\n#1. Check all fault in the whole design\nverify_faults(\"-full\");\n\n#2. Check one fault stuck-0 and dump the sequence to the VCD file\nverify_faults(\"u_master/U12/Y:0\", \"-vcd\", \"seq_u12.vcd\");\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_verify_state.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.verify_state.txt", "chroma:document": "verify_state\nGOF Formal only. Verify if a sequence exists to set the signal\nUsage: my $status = verify_state(@sig_seq, @options);\n@sig_seq: Signals and its value \n@options:\n   -help: Print this info\n   -or:  The signals are 'or' relationship, default 'and' relationship\n   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined\n$status: Return 1 if a sequence exists\n\nExamples:\n\n#1. Check one instance input A can be set to 0, dump to VCD file dump_seq.vcd \nverify_state(\"u_spi/U10/A:0\", \"-vcd\", \"dump_seq.vcd\");\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_compare_points.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_compare_points.txt", "chroma:document": "write_compare_points\nWrite all compare points to a report file\nUsage: write_compare_points($file_name, @options);\n$file_name: The report file name\n@options:\n    -all:  Include name matching instances\n\nExamples:\n\nwrite_Compare_points(\"compare_points.rep\"); # Write compare points with different naming\nwrite_Compare_points(\"-all\", \"all_compare_points.rep\"); # Write all compare points\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_dcsh.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_dcsh.txt", "chroma:document": "write_dcsh\nECO command. Write ECO result in Design Compiler dcsh script format\nUsage: write_dcsh($dc_script_name);\n$dc_script_name:  Design Compiler dcsh script name.\n\nExamples:\n\nwrite_dcsh(\"eco12345.dcsh\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_formality_help_files.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_formality_help_files.txt", "chroma:document": "write_formality_help_files\nWrite formality help files including mapped instance list and modified netlist files if necessary\nUsage: write_formality_help_files($help_name);\n$help_name: Help name which can have directory specified\n\nNote: \n\nExamples:\n\n#1. Write out Formality help files into directory fm_help with the base name eco_1225\nwrite_formality_help_files(\"fm_help/eco_1225\"); \n \n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_perl.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_perl.txt", "chroma:document": "write_perl\nECO command to write ECO result in Perl script (LLM: result in perl)\nUsage: write_perl($eco_script_name);\n$eco_script_name: ECO script name\nNote: The command can be used after 'fix_design' API. Detail ECO operations are written out.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_soce.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_soce.txt", "chroma:document": "write_soce\nECO command. Write ECO result in  SOC Encounter script format\nUsage: write_soce($soc_encounter_script_name, @options);\n$soc_encounter_script_name:  SOC Encounter script name.\n@options:\n    -type1: Alternate SOC Encounter script type\n\nExamples:\n\nwrite_soce(\"eco12345.soce\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_spare_file.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_spare_file.txt", "chroma:document": "write_spare_file\nECO command. Write spare cells list to a file\nUsage: write_spare_file($filename);\n$filename: Spare cells file name to be written out\n\nNote: Any used spare cell has '#' in the start of the line\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_tcl.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_tcl.txt", "chroma:document": "write_tcl\nECO command to write ECO result in Design Compiler tcl script format (LLM: result in tcl)\nUsage: write_tcl($tcl_script_name);\n$tcl_script_name:  Design Compiler tcl script name.\n\nExamples:\n\nwrite_tcl(\"eco12345.tcl\");\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: api_write_verilog.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\api.write_verilog.txt", "chroma:document": "write_verilog\nECO command to write ECO result in Verilog netlist (LLM: result in verilog)\nUsage: write_verilog($verilog_file, @options);\n@options:\n    -help: Print this information\n    -all:  Keep the modules in the netlist file even they are not the sub-modules of the top module\n$verilog_file: The Verilog netlist file name, should be different from the existing Implementation Netlist file name.\n\nNote: When the Implementation design is read in by multiple netlist files, set_top command should be used to \n      make the correct file saved\n      \nExamples: \n\n#1. Write out ECOed netlist to imp_eco.v\nread_design(\"-ref\", \"reference.v\");\nread_design(\"-imp\", \"implementation.v\");\nfix_design;\nwrite_verilog(\"imp_eco.v\");\n\n#2. The design is read in by command line 'gof -lib tsmc.lib ethernet_top.v'\n#   After ECO, to write ECO netlist use command \nwrite_verilog(\"ethernet_top_eco.v\");\n\n#3. The design is read in by multiple netlist files in command line, \n#   'gof -lib tsmc.lib mem_control.v dsp.v ethernet_top.v'\n#   The ECO is done on 'mem_control' module, to save the netlist\nset_top(\"mem_control\");\nwrite_verilog(\"mem_control_eco.v\");\n\n \n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_addmewmodule.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_addmewmodule.txt", "chroma:document": "2.2.15 Add a new module\nThe module mentioned in the section above can have hierarchy kept instead of flatten, and being written into ECO netlist as whole. This flow needs the module and its sub-modules written out in a separate verilog file, then uses read_library to load the file with '-vmacro' option. GOF treats the module as a leaf cell.\nAn example for adding a new module:\n\n# GOF ECO script, run_new_module_example.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_hier_example\");# Setup ECO name\nread_library(\"tsmc.lib\");# Read in standard library\nread_library(\"-vmicro\", \"syn_macro.v\"); # The syn_macro module is added into the netlist\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in the Reference Netlist\n# Read in the implementation netlist which is under ECO\nread_design(\"-imp\", \"implementation.gv\");\nset_top('top');# Set the top module\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"scan_enable\", 0); \nset_pin_constant(\"scan_mode\", 0); \nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco();# ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\n\n\nThe content in file syn_macro.v is&nbsp;written into the ECO file eco_verilo.v as a whole. The corresponding instance is&nbsp;created as well with ports connected correctly according to Reference Netlist.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_autoecoscript.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_autoecoscript.txt", "chroma:document": "2.2.3 Automatic Functional ECO example script\nThe ECO script employs the exact syntax of a Perl script. It executes exported APIs that interact with the netlist database, facilitating modifications to the netlist.\nThe following is the example script for automatic functional ECO:\n# GOF ECO script, run_example.pl\nuse strict;\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"tsmc.5nm.lib\");# Read in standard library\n# SVF files are optional, best to be used when the design involves multibit flops\n#read_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\n#read_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module\n# Preserve DFT Test Logic\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nfix_design();\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nrun_lec(); # Run GOF LEC to generate Formality help files\nwrite_compare_points(\"compare_points.report\");\nwrite_formality_help_files(\"fm_dir/formality_help\"); # formality_help files are generated in fm_dir folder\n# fm_dir/formality_help.config.tcl can be used in Formality script to pass logic equivalence checking\nexit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_autofullfuneco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_autofullfuneco.txt", "chroma:document": "2.2 Automatic Full-Layers Functional ECO Flow\nThe Full Layers Functional ECO allows for the addition or removal of gates in a flexible manner. The ECO operations are performed using a script in Perl syntax, which accesses, modifies, and saves the netlist database using exported APIs. GOF ECO reads in two netlist files: the Implementation Netlist (which is under ECO) and the Reference Netlist (which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist). In the ECO script, the 'fix_design' API is used to fix the top-level module and its sub-modules in global mode. GOF utilizes its built-in Logic Equivalent Check Engine to identify non-equivalent points and applies optimized minimum size gate patches to fix the non-equivalent modules.\nFigure 2 shows that two logic cones are extracted from the Implementation and Reference Netlist for the same comparison point. Initially, the implementation point does not match the reference point. GOF compares the two points and generates a patch from the Reference logic cone, which it applies to the Implementation Netlist. After patching, the two points become equivalent.\n\n\n\nFigure 2: Logic Cone Optimization\nGOF performs logic cone analysis and optimization for each failing point discovered during top-down logic equivalence checks. The failing point takes the form of an output port or input pin of a sequential element, such as a flip-flop's D input. The final patch contains the fewest number of gates required to ensure that the implementation logic cone matches the reference logic cone.\nFigure 3 depicts the flow chart of the process.\n\nFigure 3: Automatic functional ECO flow\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_checkdesignaftereco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_checkdesignaftereco.txt", "chroma:document": "2.2.18 Check design after ECO\nIt is highly recommended to run 'check_design' after ECO, to speed up, users can specify '-eco' option,\n\ncheck_design('-eco')\n\nIt can detect if there is any floating or multiple drivers after ECO.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_debugnoneqinlargeeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_debugnoneqinlargeeco.txt", "chroma:document": "2.2.17 Debug non-equivalence in large ECO\nIt happens that an ECO doesn't pass logic equivalence checker, especially for a large ECO. GOF can run individual logic equivalence checking for flop pairs, output port pairs or any two nets. Check  annotating to schematic for more detail.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_dftconstraints.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_dftconstraints.txt", "chroma:document": "2.2.9 DFT Constraints\nTo prevent false non-equivalence in LEC and ECO, constraints must be placed on the DFT logic. In the traditional DFT flow, the DFT logic is typically incorporated into the RTL design, which appears in both the Reference Netlist and the Implementation Netlist. In contrast, the modern DFT flow, which supports IEEE1687 and IEEE1500 standards, inserts the DFT logic into the Implementation Netlist using a DFT tool like  Tessent. To ensure that the Implementation Netlist, which contains DFT logic inserted by the DFT tool, matches the Reference Netlist, which lacks DFT logic, a Logic Equivalence Check must be performed. To prevent redundant or false ECO fixes, the DFT logic must be correctly constrained in the automatic functional ECO process.In the traditional DFT flow, as illustrated in the left side of Figure 7, constraints are placed on the ports. For instance, DFT control signals such as TEST_EN are set to zero, while the normal functional ports are left unconstrained.\n# Set DFT Constraints\nset_pin_constant(\"TEST_EN\", 0); \nset_pin_constant(\"scan_mode\", 0); \nset_ignore_output(\"scan_out*\");  \n\n\n\nFigure 7: DFT Constraints in Automatic Functional ECO\nIn the modern DFT flow, these inserted DFT logic by the DFT tool as shown in the right side of Figure 7 should be constrained to be in inactive state. The control signals driven by TDR registers should be constrained to zeros.\nGOF provides several APIs to constrain the DFT logic, set_ignore_output, set_pin_constant and set_net_constant. The API set_net_constant can be used to constrain the TDR registers signals. Since TDR registers are not ports, so they have be treated as nets.\n\n# Set DFT Constraints for the modern DFT flow\nset_pin_constant(\"TEST_EN\", 0); \nset_pin_constant(\"scan_mode\", 0); \nset_ignore_output(\"scan_out*\");  \nset_net_constant(\"TDR_SEL0\", 0, \"-imp\"); # TDR register net only exists in Implementation Netlist\nset_net_constant(\"TDR_SEL1\", 0, \"-imp\"); \nset_net_constant(\"all_test\", 0, \"-imp\"); \n# For memories that have pins directly controlled by TDRs\nset_ignore_pin(\"TSMC_MEM_256X29/TCEN*\");\n\n\n\nThe full script with constraints on the traditional DFT flow is shown below:\n# GOF ECO script, run_example_exclude_test_logic.pl\n# The SOC_TOP design should have scan insertion test logic excluded in ECO. \n# The scan out bus pin has naming of scan_out[199:0] and API set_ignore_output can be used to exclude LEC check on scan_out in ECO.\n# And TEST_EN and scan_mode are two scan set up signals which can be forced to zeros by API set_pin_constant.\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"tsmc.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"SOC_TOP\"); # Set the top to&nbsp;the most top module SOC_TOP\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"TEST_EN\", 0); \nset_pin_constant(\"scan_mode\", 0); \nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\nThe full script with constraints on the modern DFT flow is shown below: \n# GOF ECO script, dft_constraints_on_inserted_test_logic.pl\n# set_net_constant is used to constrain TDR register nets to zeros\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"tsmc.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"SOC_TOP\"); # Set the top to&nbsp;the most top module SOC_TOP\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"TEST_EN\", 0); \nset_pin_constant(\"scan_mode\", 0); \nset_net_constant(\"TDR_SEL0\", 0, \"-imp\"); # TDR register net only exists in Implementation Netlist\nset_net_constant(\"TDR_SEL1\", 0, \"-imp\"); \nset_net_constant(\"all_test\", 0, \"-imp\"); \nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_dftdrc.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_dftdrc.txt", "chroma:document": "2.2.10 DFT Design Rule Checker\nIt's common for DFT logic to be broken during functional ECO processes, which involve modifying a design for functional reasons after it has already been verified. Since DFT control signals are disabled during functional ECO, the ECO tool is not aware that DFT logic has been modified and cannot verify its functionality. When the modified netlist is ready to be tested using DFT tool, it can take a long time to identify issues. GOF provides a fast DFT Design Rule Checker that can quickly identify issues with DFT logic. A fundamental design rule for DFT is to ensure that the scan chain is complete, meaning that it can be used to capture and output test patterns during testing. Additionally, clock and reset signals should be controllable during test mode to enable proper test pattern application.\n\nFigure 8: DFT Design Rule Checker\nThe script to do DFT Design Rule Check:\n\nset_log_file(\"dft_drc.log\");      # Set log file name\nread_library(\"art.5nm.lib\");      # Read in liberty file\nread_design('-imp', 'dft_top.v'); # Read in the design with DFT implemented\nset_top(\"DFT_TOP\");               # Set the top module name\nset_pin_constant(\"test_scan_shift\", 1); # Set scan shift pin to 1\nset_pin_constant(\"all_test_reg/Q\", 1);  # Set TDR all_test register Q to 1\nset_pin_constant(\"test_mode_reg/Q\", 1);  # Set TDR test_mode register Q to 1\ncreate_clock(\"occ_add_1_inst/U0/Z\", 10); # Set clock on OCC drivers, maybe multiple\ncreate_clock(\"occ_add_2_inst/U0/Z\", 10); # Set clock on OCC drivers, maybe multiple\ncreate_reset(\"power_on_reset\", 0);       # Set reset pin\nset_top(\"DESIGN_TOP\");                   # pin_si/pin_so is internal pins of DFT_TOP\nset_scan_pairs(\"pin_si[0]\", \"pin_so[0]\"); # Add scan chain pair 0\nset_scan_pairs(\"pin_si[1]\", \"pin_so[1]\"); # Add scan chain pair 1\n# More scan chain can be added. These codes can be handled by a for loop command\nset_top(\"DFT_TOP\"); \nmy $err = dft_drc;\nif($err){\n  gprint(\"DFT DRC found $err errors\\n\");\n}\n\nThe Design Rule Checker can catch these issues by error codes:\n\nERROR_CLOSE_LOOP: A flop driving its own SI by Q pin\nERROR_CLOCK: A flop having clock that cannot be controllable in DFT mode\nERROR_CLOCK_UNDEFINED: A flop driven by a clock not defined as DFT clock\nERROR_MULTI_PATHS: Scan chain having multiple paths\nERROR_SE_NOT_ASSERT: A flop having shift enable pin not asserted\nERROR_RESET_GLITCH: A flop having reset pin with multiple active paths which may cause glitch\nERROR_RESET: A flop having reset pin not controllable in DFT mode\nERROR_SET_GLITCH: A flop having set pin with multiple active paths which may cause glitch\nERROR_SET: A flop having set pin not controllable in DFT mode\nERROR_END_CONST: A scan chain ending with constant\nERROR_END_AT_INST: A scan chain ending with a non-flop, nor EDT logic \n\nFor instance, DFT DRC catches ERROR_MULTI_PATHS error in a functional ECO when an NAND gate is inserted between back-to-back flops.\n\nFigure 9: Broken scan chain in functional ECO\nThere are two solutions to fix the error. The first solution involves changing the drain flop, FLOP_B, to a scan type flop with scan_in and scan_enable pins.\n\nFigure 10: Solution 1 to change the drain flop scan type\nThe second solution involves inserting a MUX before the D input of FLOP_B. The selection signal of the MUX is controlled by the scan_enable signal to select the output of the previous flop, FLOP_A, when scan_enable is asserted.\n\nFigure 11: Solution 2 to insert a MUX to fix the scan chain\nBoth solutions can be implemented using GOF in either GUI mode ECO or script mode ECO. After the necessary fixes have been made, the DFT DRC will be free of errors.\nFor more information on GUI mode ECO, please refer to this page.\nThe commands to fix the logic in script mode:\n\n#Solution 1\nchange_gate(\"FLOP_B\", \"SDFFHQX1\", \".SI(FLOP_A/Q),.SE(FLOP_A/SE)\");\n#Solution 2\nchange_pin(\"FLOP_B/D\", \"MX2X4\", \"u_dft_eco_mux\", \"-,FLOP_A/Q,FLOP_A/SE\");\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_ecoretarget.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_ecoretarget.txt", "chroma:document": "2.2.8 ECO Retargeting\nThe synthesis of a large SOC design is known for its time-intensive nature, often taking several days to complete. In cases where a functional ECO is necessary, particularly concerning a specific sub-module, the design team opts to confine the ECO to that particular sub-module instead of initiating synthesis for the entire design. Following this, the ECO results for the sub-module are retargeted onto the full top-level netlist. This strategy significantly accelerates the turnaround time and ensures the project schedule remains on track.\nHowever, the team must factor in the boundary optimization of the sub-modules during backend processing. A given sub-module may have undergone unique transformations, resulting in the creation of multiple distinct physical modules with diverse backend optimizations. Illustrated in Figure 6, an instance of SUB_MOD_A may exemplify a backend modification, such as a port inversion.\nConsequently, the automatic ECO process must be designed to account for these variations in backend processing, ensuring a comprehensive and accurate adaptation to the specific characteristics of each sub-module.\n\nFigure 6: Instances of one sub-module have different boundary optimization\nThe boundary optimization challenge in GOF is addressed by incorporating the original pre-layout netlist. This is possible because the pre-layout netlist should mirror the state of the netlist before any ECO is implemented, with the boundary remaining unchanged prior to the placement and routing phase.\nTo extract the boundary optimization of sub-modules during ECO, a comparison is made between the pre-layout netlist and the netlist under ECO. As the automatic ECO is applied to individual sub-modules, the relevant boundary optimization information is retroactively annotated. This ensures the precision of the ECO and establishes equivalence when comparing top-level designs.\nThe loading of the pre-layout netlist is facilitated by using the \"-ori_syn\" option in the \"read_design\" command.\nECO retargeting script:\nread_design('-ref', \"new_sub_mode_a.gv\"); # New synthesized sub-module-A\nread_design('-imp', \"post_layout.gv\"); # Full post layout netlist\nread_design('-ori_syn', \"pre_layout.gv\"); # Full prelayout, equal to post_layout.gv\n# Apply ECO to the first instance\nset_top_ref(\"SUB_MOD_A\"); # Must set REF scope\nset_top(\"SUB_MOD_A_0\"); # Uniquified name for the first instance\nfix_design;\n# Apply ECO to the second instance\nset_top_ref(\"SUB_MOD_A\"); # Must set REF scope\nset_top(\"SUB_MOD_A_1\"); # Uniquified name for the second instance\nfix_design;\nset_top(\"SOC_TOP\");\nreport_eco();\nwrite_verilog(\"post_layout.eco.gv\"); # Full post layout netlist after ECO\n\nThis entire retargeting procedure is notably more time-efficient compared to performing a full netlist ECO. With the boundary information being meticulously addressed, the resulting ECO is highly accurate.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_filereq4fullfuneco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_filereq4fullfuneco.txt", "chroma:document": "2.2.1 Files and data requirements in automatic functional ECO\n\n  Liberty files with extension '.lib'\n  Other Verilog libraries files for modules not covered in '.lib' files\n  Implementation SVF and Reference SVF file, required for designs with multibit flops\n  Implementation Netlist on which ECO will be done\n  Reference Netlist synthesized with the same constraints as the pre-layout netlist\n  The top level module name under ECO\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_filereqingatearray.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_filereqingatearray.txt", "chroma:document": "2.4.3 Files and data requirements in Gate Array ECO\n\n  Standard library ( Liberty) files with extension '.lib'\n  Other Verilog libraries if '.lib' files can't cover\n  Implementation Netlist\n  Reference Netlist\n  LEF files\n  DEF (Design Exchange Format) files\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_filereqinmanualeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_filereqinmanualeco.txt", "chroma:document": "2.6.1 Files and data requirements in Manual ECO\n\n\tStandard library ( Liberty) files with extension &lsquo;.lib&rsquo;\n\tOther Verilog libraries\n\tImplementation Netlist\n\tECO locations\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_filereqinmetaleco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_filereqinmetaleco.txt", "chroma:document": "2.3.4 Files and data requirements in Metal Only ECO\n\n  Liberty files with extension '.lib'\n  Other Verilog libraries if '.lib' files can't cover\n  Implementation Netlist\n  Reference Netlist\n  DEF (Design Exchange Format) file. It's optional. If it is not loaded, GOF won&rsquo;t map the spare gate type cells to the exact spare instances\n  Spare gates pattern. It is in 'hierarchical_instance/leaf_instance' format. It has wild card '*' to match the spare gates in Implementation Netlist\n  Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And new spare gates list file must&nbsp;be created every time an ECO is done\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_findequalnetrtlnet.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_findequalnetrtlnet.txt", "chroma:document": "2.5 Find Equal Nets between RTL and Netlist\nFor certain ECO cases, specifically those involving changes to combinational signals, manual ECOs may prove to be quicker and more effective. However, identifying equivalent wires in the netlist for RTL signals can be a challenging aspect of such manual ECOs. This is primarily due to the fact that combinational signals are often optimized during synthesis. To help alleviate this issue, GOF offers an API called 'find_equal_nets' as well as GUI operations to assist in the search for equivalent nets in the netlist for RTL signals.\n2.5.1 Example script to find equal nets\nThe following is the example script for finding equal nets in netlist for RTL:\n# GOF script, find_equal_nets.pl\nuse strict;\nread_library(\"art.5nm.lib\");# Read in standard library\nset_define(\"SYNTHESIS\");\nset_define(\"NO_SIM\");\nset_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\");\nread_rtl('-ref', \"ref0.sv\", \"ref1.sv\", \"ref2.sv\");\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist \nset_top(\"topmod\");# Set the top module\nelab_rtl;\nfind_equal_nets(\"row_full\", \"sync_start\"); # Find row_full and sync_start in the netlist\n\n2.5.2 GUI Mode to find equal nets\nPlease refer to 'Find Equal Nets in Netlist Window' for the detail\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_formalityhelp.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_formalityhelp.txt", "chroma:document": "2.2.19 Formality help files generation\nGOF LEC logic equivalence checking can be performed on any two netlists or on the results after GOF ECO run. Subsequently, Formality help files can be generated for use in Formality, significantly enhancing the success rate of the Formality tool.\nFormality help files generation:\nread_library(\"tsmc.lib\");\nread_design(\"-ref\", \"reference.v\"); # Reference netlist\nread_design(\"-imp\", \"eco_netlist.v\"); # ECOed netlist\nset_top(\"CHIP_TOP\");\nrun_lec(); # Run GOF LEC\nwrite_compare_points(\"compare_points.report\");\nwrite_formality_help_files(\"fm_dir/formality_help\"); # formality_help files are generated in fm_dir folder\n\nIn the above example, the assistance configuration file \"fm_dir/formality_help.config.tcl\" contains a compilation of set_user_match, rewire_connection, and set_constant commands designed to aid Formality in successfully achieving logic equivalence checking.\nIntegrated the file into Formality script:\n# Formality netlist vs netlist script\nread_db -tech tsmc.db\nread_verilog -r reference.v\nread_verilog -i eco_netlist.v\n#Setup constraint\n#Read in the help config file \nsource fm_dir/formality_help.config.tcl\nmatch\nverify\n\n2.2.20 RTL Guided ECO Flow\nRTL-guided ECO employs two approaches: utilizing the built-in RTL logic equivalence checking engine of GOF or incorporating results from third-party LEC tools to pinpoint areas needing ECO adjustments. The advantage of the internal RTL LEC is its speed and efficiency. However, a drawback arises when hierarchies mismatch with synthesized netlists, particularly in designs with extensive SystemVerilog statements. To address this, third-party RTL LEC tool results can be utilized to resolve hierarchy inconsistencies. For example, GOF ECO can process a list file of non-equivalent results from tools like  Formality, allowing it to concentrate ECO efforts solely on identified areas.\n2.2.21 Internal RTL to RTL Guidance\nThe RTL Guided ECO Flow is an additional step in the netlist ECO process, which involves comparing RTL designs to identify any discrepancies. Unlike Gate to Gate comparison, this method is faster and more targeted. The ECO process can be slowed down by the insertion of DFT logic and boundary optimization, making gate-to-gate comparison more complicated. Additionally, the use of RTL comparison can prevent the generation of redundant ECO fixes during patch generation.\nFigure 15 illustrates how RTL to RTL comparison runs parallel to the key-point mapping of two gate-level netlists. If the non-equivalent points identified by RTL comparison have been integrated into the ECO flow successfully, gate-to-gate comparison can be bypassed.\n\nFigure 15: RTL Guided ECO Flow\n2.2.21.1 Files and data requirements in RTL guided ECO\n\n  Liberty files with extension '.lib'\n  Other Verilog libraries files for modules not covered in '.lib' files\n  Implementation SVF and Reference SVF file, required for designs with multibit flops\n  Implementation Netlist on which ECO will be done\n  Reference Netlist synthesized with the same constraints as the pre-layout netlist\n  Implementation RTL which is logically equivalent to the Implementation Netlist\n  Reference RTL which is logically equivalent to the Reference Netlist\n  The top level module name under ECO\n\n2.2.21.2 Steps to do RTL guided ECO\n\n  Modify the original RTL\n  Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist\n  Create GOF ECO script:\n    \n      Specify ECO name in 'setup_eco'\n      Load Liberty files and Verilog libraries\n      Load Reference RTL (the modified RTL) and Implementation RTL (the original RTL)\n      Check non-equivalent points by 'rtl_compare'\n      Load the Reference Netlist and the Implementation Netlist\n      Fix the design by 'fix_design'\n      Report ECO status and write out ECO results\n    \n  \n  Run the above ECO script by \"gof -run eco_script.pl\"\n\n2.2.21.3 RTL guided ECO example script\nGOF script has the exact same syntax as Perl script and runs the exported APIs that access the netlist database and modify the netlist.\nThe following is the example script for RTL guided ECO:\n# GOF ECO script, rtl_guided.pl\nuse strict;\nsetup_eco(\"rtl_guided_eco_example\");# Setup ECO name\nread_library(\"art.5nm.lib\");# Read in standard library\nmy $rtl2rtl = 1;\nif($rtl2rtl){\n  set_define(\"SYNTHESIS\");\n  set_define(\"NO_SIM\");\n  set_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\");\n  read_rtl('-ref', \"ref0.sv\", \"ref1.sv\", \"ref2.sv\");\n  read_rtl('-imp', \"imp0.sv\", \"imp1.sv\", \"imp2.sv\");\n  set_top(\"topmod\");\n  rtl_compare;\n}\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module\n# Preserve DFT Test Logic\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears\n\n2.2.21.4 Synthesize Reference RTL to Reference Netlist\nIf Reference Netlist is not provided, it can be synthesized from Reference RTL by 'synthesize' command.\nAs shown in Figure 16, Reference RTL is directly synthesized into Reference Netlist and used in the ECO.\n\nFigure 16: RTL Guided ECO Flow\nThe following is the example script for Reference RTL synthesis in RTL guided ECO:\n# GOF ECO script, rtl_guided_synthesis.pl\nuse strict;\nsetup_eco(\"rtl_guided_eco_example\");# Setup ECO name\nread_library(\"art.5nm.lib\");# Read in standard library\nset_define(\"SYNTHESIS\");\nset_define(\"NO_SIM\");\nset_inc_dirs(\"/project/nd900/vlib/include\", \"/project/nd900/IPS/include\");\nread_rtl('-ref', \"ref0.sv\", \"ref1.sv\", \"ref2.sv\");\nread_rtl('-imp', \"imp0.sv\", \"imp1.sv\", \"imp2.sv\");\nset_top(\"topmod\");\nrtl_compare;\n\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module\nelaborate; # The command synthesizes the Reference RTL to Reference Netlist \n# Preserve DFT Test Logic\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears\n\n2.2.22 Third Party RTL LEC Result Processing\nGOF ECO has the capability to ingest a list of ECO points, enabling it to concentrate exclusively on the items specified in the list. The format of the list file comprises a type designation followed by one or multiple spaces and then the non-equivalence point.\n\n\ninst yak_zcvg_inst/skip_pix_reg\nport te_coord[5]\ninst yak_hah_inst/x_start_pa_reg_31_\ninst yak_hah_inst/x_end_pa_reg_30_\ninst yak_hah_inst/x_end_pa_reg_29_\ninst yak_hah_inst/x_end_pa_reg_28_\ninst yak_hah_inst/x_end_pa_reg_27_\ninst yak_hah_inst/x_end_pa_reg_26_\npin yak_hah_inst/u_sync_cell/D\n\n\nThe ECO list file is incorporated using the '-list_file' option within the 'read_design' command. It can be generated from a Third Party LEC non-equivalence result file. For instance, in  Formality, the command 'report_failing_points > formality_non_eq.report' generates such a file. In a GOF ECO script, this report file is then read in and converted into the list file.\nBelow is an example script demonstrating the conversion of Third Party LEC results and execution of GOF ECO with the 'list_file' option:\nuse strict;\nmy $list_cont = \"\";\nopen(FIN, \"formality_non_eq.report\");\nwhile(&lt;FIN&gt;){\n  if(m/Ref\\s+(\\w+)\\s+r:\\/\\w+\\/\\w+\\/(.+)/){\n    my $fm_type = $1;\n    my $point = $2;\n    my $gof_type = \"inst\";\n    if($fm_type =~ m/Pin/){\n      $gof_type = \"pin\";\n    }elsif($fm_type =~ m/Port/){\n      $gof_type = \"port\";\n    }else{\n      # For instance type\n      $point =~ s/\\[/_/g; # Mostly abc_reg[0] has name changed to abc_reg_0_ in the netlist\n      $point =~ s/\\]/_/g;\n    }\n    $list_cont .= \"$gof_type $point\\n\";\n  }\n}\nclose(FIN);\nopen(FOUT, \">eco_list.txt\");\nprint FOUT $list_cont;\nsetup_eco(\"eco_list_file\"); # Setup ECO name\nset_log_file(\"eco_list_file.log\");\nread_library(\"tsmc.5nm.lib\");# Read in standard library\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"SOC_TOP\");\nset_pin_constant(\"test_mode\", 0);\nset_pin_constant(\"scan_en\", 0);\nset_ignore_output(\"test_so*\");\nfix_design(\"-list_file\", \"eco_list.txt\"); # -list_file option to read in the ECO list file with the ECO points\nreport_eco();\nwrite_verilog(\"eco_verilog.v\");\nexit;\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_gatearrayautomapping.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_gatearrayautomapping.txt", "chroma:document": "2.4.2 Gate Array Automatic Mapping\nWhen generating a patch, GOF synthesizes it using only gate array functional cell types. These functional cells are then mapped to the most optimal nearby gate array spare cells with the minimum wire connection costs.\n\nFigure 21: Gate Array Spare Cells Mapping to Functional Cells\nOnce the mapping and swapping process is complete, some gate array spare cells may have portions of their tiles being used by several functional cells, as shown in Figure 21. To properly save the ECO results, the type of these gate array spare cells should be changed. For instance, gate array A should have its type changed from GFILL8 to GFILL4. Any completely used up gate array spare cells, such as gate array B with type GFILL4 and all four tiles being used, should be deleted.\nThe mapped gate array functional cells need to be moved to the locations of their corresponding gate array spare cells, with the horizontal location X adjusted based on the starting tile location. For example, the GINVD1 instance should be moved to (Xg+TW, Yg), and the GBUFFD1 instance should be moved to (Xg+TW*6, Yg), as shown in Figure 20.\nGOF writes out an ECO verilog file and backend tools ECO scripts. In the verilog file, the location of the newly added gate array functional cells is written in comments. GOF supports both  ICC script and  Encounter script, both of which have cell location placement support.\nFor example, when saving the result in an ICC TCL script, the cells in Figure 20 would have the following commands:\n\nsize_cell GFILLER_7256 GFILL1 # The original GFILL8 resized\ncreate_cell eco_3821_ubuf GBUFD1\ncreate_cell eco_3821_uan4 GAN4D1\ncreate_cell eco_3821_und2 GND2D1\ncreate_cell eco_3821_uinv GINVD1\nset_cell_location -ignore_fixed -coordinates \"255.02 413.28\" eco_3821_ubuf # Xg+WT*6, Yg\nset_cell_location -ignore_fixed -coordinates \"254.42 413.28\" eco_3821_uan4 # Xg+WT*3, Yg\nset_cell_location -ignore_fixed -coordinates \"254.22 413.28\" eco_3821_und2 # Xg+WT*2, Yg\nset_cell_location -ignore_fixed -coordinates \"254.02 413.28\" eco_3821_uinv # Xg+WT*1, Yg\n\nEncounter script format:\n\necoChangeCell -inst GFILLER_7256 -cell GFILL1 # The original GFILL8 resized\naddInst -loc 255.02 413.28 -inst eco_3821_ubuf -cell GBUFD1 # Xg+WT*6, Yg\naddInst -loc 254.42 413.28 -inst eco_3821_uan4 -cell GAN4D1 # Xg+WT*3, Yg\naddInst -loc 254.22 413.28 -inst eco_3821_und2 -cell GND2D1 # Xg+WT*2, Yg\naddInst -loc 254.02 413.28 -inst eco_3821_uinv -cell GINVD1 # Xg+WT*1, Yg\n\nNote:Tile size assumed to be 0.20 X 0.22; GFILL8 location (Xg, Yg)=(253.82, 413.28)\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_gatearraybasetile.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_gatearraybasetile.txt", "chroma:document": "2.4.1 Gate Array Cell Base Tile\nThe base unit of gate array cell is a tile. Every gate array cell consists of one or more tiles. Use one 5nm standard library as example:\n\n\nTile NumbersSpare CellsFunctional Cells\n\n1GFILL1GTIE GINVD1 GND2D1 GNR2D1\n\n2GFILL2GBUFD1 GAN2D1 GOR2D1 GAOI21D1 GDN3D1\n\n3GFILL3GAO21D1 GAN4D1 GOR4D1\n\n4GFILL4GINVD8 GAN2D4\n\n5GFILL5GMUX2D1 GXOR2D1 GXNOR2D1\n\n6GFILL6GBUFD8 GSDFFRQD1 GSDFFSQD1\n\n8GFILL8GINVD16\n\n12GFILL12GCKLNQD6\n\nTable: Tile Numbers in Gate Array Spare Cells and Functional Cells\nGate array cells have a larger size than normal standard cells. For instance, GFILL1 is four times larger than FILL1, and GND2D1 is 25% larger than ND2D1. However, the power consumption and timing of these cells are similar.\nEach gate array spare cell has a location defined by a DEF file. In Figure 20, the location of one GFILL8 spare cell is defined as (Xg, Yg), with a tile height equivalent to that of GFILL1 and a tile width eight times that of GFILL1.\nGFILL8 tiles can be regrouped and rewired in metal layers to create different functional cells. For example, GBUFD1 requires two tiles and implements a buffer function, while GAN4D1 uses three tiles to create a 4-input AND function.\n\nFigure 20: Gate Array Spare Cell GFILL8 Regrouped Tiles to Form Functional Cells\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_gatearrayeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_gatearrayeco.txt", "chroma:document": "Metal configurable gate array cells are specially developed for Metal Only ECO. These cells come in two types, which are used in different backend stages. The first type is gate array spare cells, which are typical filler or decap cells used in the original flow. During the backend P&R stage, gate array spare cells such as GFILL/GDCAP are incorporated and distributed throughout the design. The second type is gate array functional cells, which are used in post-mask ECO. Gate array spare cells are replaced with gate array functional cells such as GAN2, GND2, and GXOR2.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_gclockinmetaleco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_gclockinmetaleco.txt", "chroma:document": "2.3.8 Gated clocks in Automatic Metal Only ECO\nIf the automatic metal only ECO has new gated clock cells added while the spare gates list doesn't have gated clock cell, \"convert_gated_clocks\" API should be run to convert gated clock cells to 'MUX' type logic. GOF maps the 'MUX' type logic to the spare type gates in 'map_spare_cells' API.\n\nget_spare_cells(\"*/*_SPARE*\");\nconvert_gated_clocks();\nmap_spare_cells();\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_guimodefulllayereco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_guimodefulllayereco.txt", "chroma:document": "2.8 GUI Mode Full Layers ECO Flow\nThe following paragraph demonstrates how to insert buffers and inverters into a circuit in GUI mode.\n\n2.8.1 Start up GOF in GUI Mode\n\nStart up GOF by the command line\n\ngof -lib t65nm.lib -lib io.lib netlist_port.v\n\nFor detail usage, visit this link\nhttps://nandigits.com/usage.htm\nIn GofViewer netlist window, press ctrl-g or menu commands-&gt;&rsquo;Launch GofTrace with gate&rsquo;. Fill in the instance name that needs ECO.\n\nFigure 22: Load gate to schematic\n2.8.2 Create Partial Schematic\nIn GofTrace schematic window, use mouse middle button to expand the schematic. In this case, pin D of the flop should be inserted an invert.\n\nFigure 23: Partial Schematic for GUI ECO\n\n2.8.3 Do ECO on schematic\n\nCheck ECO button to enable ECO mode\n\nFigure 24: Schematic in ECO Mode\nPress mouse-left-button on the wire to select it. Click ECO button &lsquo;Insert gates into connections&rsquo;, select the right invert in the gate type selection window.\n\nFigure 25: Select Gate in GUI ECO\nIn &lsquo;Pin Connections&rsquo; setup window, use default &lsquo;Complete Loop&rsquo; option, so that the gate can be inserted in the net.\n\nFigure 26: New Cell Pin Connection Selections\n\nClick OK and the invert is inserted.\n\nFigure 27: Manual ECO with New Gate Inserted\n2.8.4 Save ECO in GUI Mode\nPress ECO button &lsquo;Save ECO result to file&rsquo;. And select the format to be saved. The supported formats include verilog netlist, SOC Encounter ECO script, GOF script, TCL script and DCShell script.\n\nFigure 28: Save ECO in GUI Mode\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_guimodemetalonlyeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_guimodemetalonlyeco.txt", "chroma:document": "2.9 GUI Mode Metal Only ECO Flow\nMetal ECO can only use existing spare gates on the silicon. GOF controls how to use these spare gates.\n2.9.1 Methods for Metal Only ECO\nFour methods are supported in Metal Only ECO:\n\nUser can add any type of gates and let the tool map to the spare type gates, Place and Route tool should map the spare type gates to the exact spare gate instances\nUser can add any type of gates and let the tool map to the exact spare gate instances\nUser can add only spare type gates and let the tool map to the exact spare gate instances\nUser can pick the exact spare gate instances, and connect and disconnect up the instances in ECO\n\nNote: 'Spare type gate' refers to the gate type, 'INVX2', 'NAND2X2'. 'Exact spare gate instance' refers to the spare instances in the design, E.G. 'spare1/spare_invx2'\n2.9.2 Setup and use cases\nThe detail setup for four method can be found in GOF ECO Metal Only ECO. Use cases can be found in online document.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_handlrepwork.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_handlrepwork.txt", "chroma:document": "2.6.6 Handle repetitive work\nA Perl 'for' or 'foreach' loop can handle repetitive work efficiently. For example, to add a 'AND' isolation gate for every output port of a module.\n\n# GOF ECO script, add_ands.pl\nuse strict;\nundo_eco; # Discard previous ECO operations\nsetup_eco(\"eco_example\"); # Setup ECO name\nread_library(\"tsmc.lib\"); # Read in standard library\nread_design(\"-ref\", \"reference.gv\"); # Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\"); # Read in implementation Netlist which is under ECO\nset_top(\"topmod\"); # Set the top module that ECO is working on\nmy @ports = get_ports(\"-output\"); # Get all output ports of module 'topmod'\n# For each output port of 'topmod', insert an 'AND' gate to enable it only when 'enable_out' is high\nmy $cnt = 0;\nforeach my $port (@ports){\n&nbsp;&nbsp;change_port($port, \"AND2X2\", \"eco_add_and_$cnt\", \"-,enable_out\");\n&nbsp;&nbsp;$cnt++;\n}\nreport_eco();\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_manualecoapilist.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_manualecoapilist.txt", "chroma:document": "2.6.3 Manual ECO APIs list\nThese APIs change Implementation Netlist\n\nbuffer: ECO command. Buffer high fanout ECO nets\nchange_gate: ECO command. Modify an instance in ECO\nchange_net: ECO command. Change a existing net's driver\nchange_pin: ECO command. Modify pin connection of instances by inserting gates, changing connection to other signal (LLM: change pin insert gate)\nchange_port: ECO command. Change an output port's driver, or add gate after input port \ndel_gate: ECO command. Delete gate\ndel_net: ECO command. Delete net\ndel_port: ECO command. Delete port\nnew_gate: ECO command. Create new gate\nnew_net: ECO command. Create a new net\nnew_port: ECO command. Create a new port for the current top level module\n\nFor the full list of the APIs, user can type 'help' in 'GOF &gt;' shell.\nFor the individual API, type 'help api_name' . For example:\n\nGOF > help new_port\nHelp for new_port\nnew_port: ECO command. Create a new port for the current top level module\nECO command. Create a new port for the current top level module\nUsage: new_port($name, @options);\n$name: Port name\n@options:\n-input: New an input port\n-output: New an output port\n-inout: New an inout port\nNote: The port name has to be pure words or with bus bit, like, abc[0], abc[1]\nExamples:\nnew_port('prop_control_en', '-input'); # create an input port naming prop_control_en\nnew_port('prop_state[2]', '-output'); # create an output port with bus bit prop_state[2]\nnew_port('prop_state[3]', '-output'); # create an output port with bus bit prop_state[3]\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_multiflops.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_multiflops.txt", "chroma:document": "2.2.7 Multibit flops in ECO\nMultibit flops can pose a challenge in logic equivalence check and ECO due to the different naming conventions used by various synthesis tools. For example, as depicted in Figure 5, a four-bit multibit flop has a different naming style in  Genus compared to  Design Compiler after name changing. Additionally, backend tools may split some multibit flops into single bit flops to address timing issues. These factors make key point mapping a complex task.\nIn logic equivalence check, multibit flops need to be mapped to single flops. However, the mapping of single flops to multibit flops from the Reference Netlist may differ from the Implementation Netlist. For instance, in Figure 5, the Implementation Netlist has a four-bit multibit flop instance named 'a_reg_0_2_4_', whereas the Reference Netlist after Synthesis may have two-bit multibit flops named 'a_reg_0_1_' and 'a_reg_2_4_'. Depending solely on naming conventions may not lead to the correct multibit to single bit mapping. Although LEC and ECO tools can handle some limited multibit to single bit mapping using comprehensive algorithms, there is no guarantee of complete successful mapping.\n\nFigure 5: Multibit flop naming in synthesis tools\nGOF provides support for accurate and reliable key point mapping through the use of text mode SVF files from Design Compiler. These SVF files are encrypted by default, but can be converted to text mode when using Formality to read the encrypted file. Additionally, GOF can convert backend multibit flop split/merge information into an SVF file. By reading both the synthesis SVF and the converted SVF file, GOF is able to completely resolve the mapping of multibit flops to single bit flops.\nFor instance, Innovus generates a multi_bit_pin_mapping file to store split and merge information. This file can be converted to an SVF text file using a GOF script.\nHere is an example script for converting an Innovus multi_bit_pin_mapping file:\nread_library(\"libdir/art.lib\");\nset_multibit_blasting(0); # Disable multibit blasting\nread_design('-imp', \"imp_net.v\");\nset_top(\"the_top\");\n\nopen(FIN, \"./multi_bit_pin_mapping\");\nmy $mbit_split = {};\nmy $mbit_merge = {};\nwhile(&lt;FIN&gt;){\n  my ($from, $to) = (m/(\\S+)\\s+(\\S+)/);\n  $from =~ s/\\/\\w+$//; # remove the pin\n  $to =~ s/\\/\\w+$//; \n  my ($module, $to_inst) = get_resolved($to);\n  my ($from_inst) = ($from =~ m/([^\\/]+)$/);\n  my $libcell = get_ref($to);\n  gprint(\"get ref of $to as $libcell\\n\");\n  my $is_ff = is_seq($libcell, \"-ff\");\n  if($is_ff){\n    if(is_seq($libcell, \"-bank\")==0){\n      if(!exists $mbit_split->{$module}{$from_inst}){\n\t$mbit_split->{$module}{$from_inst} = [];\n      }\n      if(grep($_ eq $to_inst, @{$mbit_split->{$module}{$from_inst}})==0){\n\tgprint(\"Multibit split in $module $from_inst to $to_inst\\n\");\n\tpush @{$mbit_split->{$module}{$from_inst}}, $to_inst;\n      }\n    }else{\n      # Bank\n      if(!exists $mbit_merge->{$module}{$to_inst}){\n\t$mbit_merge->{$module}{$to_inst} = [];\n      }\n      if(grep($_ eq $from_inst, @{$mbit_merge->{$module}{$to_inst}})==0){\n\tgprint(\"Multibit merge in $module $from_inst to $to_inst\\n\");\n\tpush @{$mbit_merge->{$module}{$to_inst}}, $from_inst;\n      }\n    }\n  }\n}\nclose(FIN);\n\nmy $svf = \"\";\nforeach my $module (keys %$mbit_merge){\n  $svf .= \"guide_multibit -design $module -type { svfMultibitTypeBank } \\\\\\n\";\n  $svf .= \"  -groups { \\\\\\n\";\n  foreach my $mbit_inst (keys %{$mbit_merge->{$module}}){\n    my $i_st = \"\";\n    my $cnt = 0;\n    foreach my $s_bit (@{$mbit_merge->{$module}{$mbit_inst}}){\n      $i_st .= \" $s_bit 1\";\n      $cnt++;\n    }\n    $i_st .= \" $mbit_inst $cnt\";\n    $svf .= \"\\t{ $i_st } \\\\\\n\";\n  }\n  $svf .= \"    }\\n\";\n}\nforeach my $module (keys %$mbit_split){\n  $svf .= \"guide_multibit -design $module -type { svfMultibitTypeSplit } \\\\\\n\";\n  $svf .= \"  -groups { \\\\\\n\";\n  foreach my $mbit_inst (keys %{$mbit_split->{$module}}){\n    my $i_st = \"\";\n    my $cnt = 0;\n    foreach my $s_bit (@{$mbit_split->{$module}{$mbit_inst}}){\n      $i_st .= \" $s_bit 1\";\n      $cnt++;\n    }\n    $i_st = \" $mbit_inst $cnt $i_st\";\n    $svf .= \"\\t{ $i_st } \\\\\\n\";\n  }\n  $svf .= \"    }\\n\";\n}\nopen(FOUT, \">backend_multibit.svf.txt\");\nprint FOUT $svf;\nclose(FOUT);\n\nTwo SVF files for Implementation are loaded in the implementation read_svf:\nread_svf(\"-ref\", \"reference.svf.txt\");       \nread_svf(\"-imp\", \"implementation.svf.txt\", \"backend_multibit.svf.txt\");  # Two SVF files are loaded\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_noexactpinmatch.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_noexactpinmatch.txt", "chroma:document": "2.2.11 No Exact Pin Match\nPhysical Synthesis is more and more popular in logic synthesis. Physical Synthesis tool, Design Compiler Topographical(DCT) or Design Compiler Graphical(DCG) for example, may add hierarchical pins that are not in RTL code and it may cause mapping issue when Implementation Netlist is comparing with Reference Netlist in ECO.\nFor example, DCT may add 'IN0', 'IN1', 'IN2', 'IN2_BAR' ... to hierarchical modules. The new added pins are not necessarily matching to each other in Implementation Netlist and Reference Netlist. That is, IN0 in module A in Reference Netlist maybe a different signal from IN0 in module A in Implementation Netlist.\n\nFigure 12: No Exact Pin Match\nThese pins are randomly named in each run. They won't affect logic equivalence check, but they need to be excluded in pin matching in ECO. Otherwise, the ECO tool would insert redundant logic or wrong logic.\nAPI set_noexact_pin_match can be used to resolve the mapping issue between Implementation Netlist and Reference Netlist.\nBy adding the port naming regular expression in the API argument, set_noexact_pin_match('\\bIN\\d+(_BAR)?\\b'), these ports will be remapped.\nNote: This API should be run before reading designs.\n\n# GOF ECO script, run_example_noexact_pin_match.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"art.90nm.lib\");# Read in standard library\nset_noexact_pin_match('\\bIN\\d+(_BAR)?\\b'); # The argument is in REGEX format to detect IN0/IN0_BAR/IN1...\n# Note: set_noexact_pin_match API should be run before reading designs!\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"SOC_TOP\"); # Set the top to&nbsp;the most top module SOC_TOP\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"scan_enable\", 0); \nset_pin_constant(\"scan_mode\", 0); \nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_noteinrtlmod.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_noteinrtlmod.txt", "chroma:document": "2.2.16 Note in RTL modification and re-synthesis\nWhen modifying RTL and do re-synthesis, care should be taken to maintain the database as much alike Implementation Netlist as possible.\n2.2.16.1 Keep sequential signal name\nA common problem in modifying RTL is having sequential signal name changed, which appears in Reference Netlist as a different flop instance. For example\n\nalways &#64;(posedge clk) abc &lt;= abc_next;\n\nIt creates a flop instance 'abc_reg' in synthesis. If the ECO in RTL change this to\n\nalways &#64;(posedge clk) abc_new &lt;= abc_next;\n\nAfter synthesis, a new flop instance 'abc_new_reg' is created. GOF may fail to find that 'abc_new_reg' being able to merge with 'abc_reg', due to other non-equivalent points present, which brings a redundant fix in the new register creation.\nSo it is highly recommended to keep the sequential signal names in re-synthesis.\n2.2.16.2 Use the same synthesis constraints\nWhen do re-synthesis, the same constraints should be used as what has been used in Implementation Netlist synthesis. If any hierarchy is not present in Implementation Netlist, it's better to flatten the module in synthesis to maintain the same hierarchies.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_phaseinvert.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_phaseinvert.txt", "chroma:document": "2.2.12 Flip-flop Phase Inverted\nDuring the pre-mask design stage, transitioning a flip-flop from resettable to settable type or vice versa is a relatively straightforward task. However, making such changes during the post-mask design stage can be challenging because it can be difficult to locate an available spare flip-flop to replace the original one. To overcome this challenge, a common approach is to add inverters to the input and output pins of the flip-flop while maintaining its original set/reset type.\nAside from resolving the issue of locating spare flip-flops, adding inverters to the flip-flop input and output pins can also address timing or power-related concerns. In some cases, this technique can help with timing closure or reduce power consumption.\nIt is essential to note, however, that implementing such changes can lead to challenges during logic equivalence checking. Incorrectly addressing these changes can result in false non-equivalent points, leading to design uncertainty. As such, appropriate measures should be taken to ensure that the changes made to the flip-flop type do not affect logic equivalence checking.\n\nFigure 13: Flip-flop Phase Inverted\nTo address this issue, the GOF platform provides an API command to configure these cases. The set_mapping_method('-phase') API is utilized to handle such situations and ensure that the changes made to the flop type do not cause false non-equivalent result.\n\n# GOF ECO script, run_example_ff_phase_inverted.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"art.90nm.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"SOC_TOP\"); # Set the top to&nbsp;the most top module SOC_TOP\nset_mapping_method('-phase'); # Check flop phase during LEC\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"scan_enable\", 0); \nset_pin_constant(\"scan_mode\", 0); \nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_reporttimingapi.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_reporttimingapi.txt", "chroma:document": "2.10 Report Timing\nTiming can be reported before or after ECO by report_timing API.\n2.10.1 Report Timing APIs\nTiming report related APIs are these:\n\ncreate_clock: Timing command and GOF Formal command. Create clock for fault verification\nset_initial_trans: Timing command. Set initial transition for clock\nset_input_delay: Timing command. Set input delay\nset_output_delay: Timing command. Set output delay\nset_output_load: Timing command. Set output load to all output ports\nset_input_transition: Timing command. Set input transition to all input ports\nset_false_path: Timing command. Set false path\nset_clock_uncertainty: Timing command. Set clock uncertainty\nreport_timing: Timing command. Report timing\nlist_wireload: Timing command. List all wireload defined in the liberty files\nset_wireload: Command for Timing Report. Set wireload for one liberty library\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_rundebugautoeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_rundebugautoeco.txt", "chroma:document": "2.2.4 Run and debug in automatic functional ECO\nThe ECO Script can be run by '-run' option.\n\ngof -run run_example.pl\n\nCheck Run and debug ECO script section in User Manual for more detail\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_script4gatearray.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_script4gatearray.txt", "chroma:document": "2.4.5 Example GOF script for gate array cells ECO flow\nGOF script has the exact same syntax of Perl script. It runs the exported commands that access the netlist database and modify the netlist.\n\n# GOF ECO script, run_gate_array_cells_eco_example.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\n# Setup ECO name\nsetup_eco(\"eco_gate_array_example\" );\nread_library(\"tsmc.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module that ECO is working on\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nread_lef(\"tsmc.lef\");   # Read LEF\nread_def(\"topmod.def\"); # Read Design Exchange Format file\nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\n# Specify gate array cells, spare and functional\n# set_dont_use command can be used to exclude some gate array cells\nget_spare_cells(\"-gate_array\", \"G*\", \"-gate_array_filler\", \"GFILL*\"); # Gate array cells extraction\nmap_spare_cells();\nreport_eco(); # ECO report\ncheck_design();# Check design\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nwrite_tcl(\"eco_icc.tcl\");# Write out TCL script for ICC\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_script4manualeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_script4manualeco.txt", "chroma:document": "2.6.4 Example GOF script for Manual ECO\n\n# GOF ECO script, run_example.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\nsetup_eco(\"eco_example\");# Setup ECO name\nread_library(\"tsmc.lib\");# Read in standard library\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the scope to the module that ECO is working on\n# The following API adds a mux in flop 'state_reg_0_' D input pin,\n# and connect up the original connection to pin 'A',\n# pin 'B' connect to net 'next_state[7]', and pin 'S' to net 'sel_mode'\n# the net can be replaced by format of 'instance/pin' , E.G. '.S(state_reg_2_/Q)'\nchange_pin(\"state_reg_0_/D\", \"MX2X4\", \"\", \".A(-),.B(next_state[7]),.S0(sel_mode)\");\nreport_eco();\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_script4manualmetalonly.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_script4manualmetalonly.txt", "chroma:document": "2.7.2 Example GOF script for Manual Metal Only ECO\n\n# Manual Metal Only ECO, manual_metal_eco.pl\nuse strict;\nundo_eco;\nsetup_eco(\"metal_eco0123\");\nset_log_file(\"metal_eco0123.log\");\nread_library(\"/prj/lib/tsmc40.lib\");\nread_design(\"-imp\", \"/prj/netlist/imp_net.v\");\nset_top(\"mtop\");\n&nbsp;\nnew_port(\"nout7\", \"-output\");# Create a new port 'nout7'\n# Place the port to 60000, 1000000. It's approximate position, the main purpose is for\n# spare instances selection\nplace_port(\"nout7\", 60000, 100000);\nnew_port(\"nout8\", \"-output\");# Create another port\nplace_port(\"nout8\", 120000, 81000);\n# 'nout8' is driven by an invert first, and the invert's input is driven by pin 'cmpmod/rego/QN'\nchange_port(\"nout8\", \"INV_X1M\", \"\", \"cmpmod/rego/QN\");\n# Drive the 'nout7' by 'INV_X1M' and leave the input unconnected, but the mapped\n# spare instance name is returned.\nmy $inst = change_port(\"nout7\", \"INV_X1M\", \"\", \"\");\n# Drive the new instance's input by a flop, and specify the flop's connection in the 4th argument\nchange_pin(\"$inst/A\", \"SDFFRPQ_X4M\", \"\", \\n\".CK(cmpmod/rego/CK),.D(cmpmod/rego/QN),.R(1'b0),.SE(1'b0),.SI(1'b0)\");\n&nbsp;\nread_def(\"/prj/def/imp_net.def\");\nget_spare_cells(\"Spare_*/*_SPARE_GATE*\");\n# Before mapping to spare gates, set a large number in buffer distance, so that GOF does&nbsp;not\n# add buffers for long connections.\nset_buffer_distance(9999999);\n# The following 'map_spare_cells' command maps the three new ECO instances to the optimal\n# spare instances.\nmap_spare_cells;\n&nbsp;\nreport_eco;\nwrite_verilog(\"imp_eco0123.v\");\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_script4metaleco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_script4metaleco.txt", "chroma:document": "2.3.6 Example GOF script for Metal Only ECO\nGOF script has the exact same syntax of Perl script. It runs the exported commands that access the netlist database and modify the netlist.\nThe following shows an example of an automatic Metal Only ECO:\n\n# GOF ECO script, run_metal_only_example.pl\nuse strict;\nundo_eco;# Discard previous ECO operations\n# Setup ECO name\nsetup_eco(\"eco_metalonly_example \" );\nread_library(\"tsmc.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module that ECO is working on\nset_ignore_output(\"scan_out*\");  \nset_pin_constant(\"scan_enable\", 0); \nset_pin_constant(\"scan_mode\", 0); \nread_def(\"topmod.def\");# Read Design Exchange Format file, optional. Loading DEF file before fix_design makes ECO physical aware\nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\n# The following is metal ECO related\n# Specify spare cell pattern, when 'map_spare_cells' is done, a new spare list file is&nbsp;written out\n# with updated spare list.\nget_spare_cells(\"*/*_SPARE*\");\n# Comment the above line and use the following line to use spare list file\n# if the spare list file has been generated already and gone through other ECOs\n# get_spare_cells(\"-file\", \"spare_list_file.txt\");\n# set_constraints(\"-num\", \"and\nmap_spare_cells();\n# Use one of the following lines if external Synthesis Tool is used\n#map_spare_cells ( \"-syn\", \"rc\" );\n#map_spare_cells ( \"-syn\", \"dc_shell\" );\nreport_eco(); # ECO report\ncheck_design(\"-eco\");# Check if the ECO causes any issue, like floating\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit;# Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_scriptmodemanualeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_scriptmodemanualeco.txt", "chroma:document": "2.7 Script Mode Metal Only Manual ECO Flow\nIn Manual Metal Only ECO, any new added gates are&nbsp;automatically mapped to spare gate instances by 'map_spare_cells' command. A Design Exchange Format file has to be loaded for the tool to find optimal spare instances. If the file is not present, the mapping is skipped.\n2.7.1 Files and data requirements in Metal Only Manual ECO\n\n\tStandard library ( Liberty) files with extension '.'lib'\n\tOther Verilog libraries\n\tImplementation Netlist\n\tDEF (Design Exchange Format) file. If it is not loaded, GOF won&rsquo;t map the spare gate type cells to the exact spare instances\n\tSpare gates pattern. It is in &lsquo;hierarchical_instance/leaf_instance&rsquo; format. It has wild card '*' to match the spare gates in Implementation Netlist\n\tSpare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And a new spare gates list file should be created every time ECO is done\n\tECO locations\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_scriptmodmanulaeco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_scriptmodmanulaeco.txt", "chroma:document": "2.6 Script Mode Full Layers Manual ECO Flow\nIn many cases, the ECO operations are well known by users. They can be inserting buffers to a 128bits bus, or adding isolation AND gates to all outputs of a module. In these cases, manual ECO by scripts is more efficient and resource saving.\nGOF exports many APIs for ECO operations in GOF script.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_sparegatesnumanddis.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_sparegatesnumanddis.txt", "chroma:document": "2.3.3 Spare Gates Number and Distribution\nSpare gates are incorporated into the design and their percentage relative to the entire digital area is usually dependent on the design maturity. For instance, the first version of a design typically requires a higher percentage of spare cells, usually around 8-10% of the entire digital area. As the design progresses to the second version, a lower percentage of spare cells, approximately 4-5% of the total digital area, is sufficient. By the third version, less than 3% additional spare cells may be necessary. Additionally, during the backend placement process, any remaining empty space can be filled with extra spare gates.\nBesides the spare gate area percentage, the proportion of various spare gate types is also crucial. For example, a design with 126K instances may have spare gates in different categories, as depicted in the following figure:\n\n  Red: 126 spare flip-flops\n  Green: 252 spare NAND2 gates\n  Yellow: 252 spare NOR2 gates\n  Blue: 882 spare inverters (INV)\n  Purple: 126 spare multiplexers (MUX)\n  Black: 126 spare tie-lo (TIELO) gates\n\nFigure 19: Spare Gates numbers and distribution\nUsually, spare gates are uniformly distributed on the floor plan, as shown in figure 19. Nevertheless, if accessible, users can adjust the distribution based on historical metal-only ECO data. Blocks that are prone to design changes may require more spare gates, while mature logic may require fewer spare gates.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_sparegatessyn.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_sparegatessyn.txt", "chroma:document": "2.3.2 Spare Gates Synthesis\nGOF ECO utilizes a heuristic method that employs constraints to identify the optimal mapping of spare gates. The process involves setting constraints to restrict the types of NAND/NOR/AND/OR gates to be considered, and then conducting a mapping exercise to identify the nearest available spare gates. The cost of the mapping is determined by adding the distance between the measured location and the actual location of the spare gate. For example, if a NAND gate needs to be mapped in a metal-only ECO, and the measured location is (100, 100), while the closest spare gate (spare_0) is located at (120, 120), then the cost is calculated as (120-100)+(120-100)=40. The method involves multiple iterations, and the optimal solution is selected based on the lowest cost.\nTo ensure that new instances are accurately mapped to the nearest spare gate instances, it is necessary to have a Design Exchange Format (DEF) file. Without loading the DEF file, the GOF process will use spare gate types without precise mapping to exact spare instances. However, P&R tools like SOC Encounter will map new instances in the new netlist to the closest spare gates.\nDuring the 'fix_design' command, GOF examines the top-level module and its sub-modules to identify any non-equivalent points and optimize the logic cone to create a patch circuit with the minimum number of gates.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_specialcharacters.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_specialcharacters.txt", "chroma:document": "2.6.7 Special characters\nThe special character '-' is used to represent existing connection. For example\n\nchange_pin(\"U0/A\", \"BUFFX1\", \"eco_buf\",\"-\");\n\nA buffer is inserted into A pin of instance U0. The old existing net drives the new buffer now.\nThe special character '.' is used in ECO new instance name if the new instance needs to be in the same hierarchy as the ECO spot.\n\nchange_pin(\"u_qcif/u_num2/u_spare1/B\", \"AOI21X2\",\".\", \"net1,net2,net3\");\n\nIf the instance is empty, GOF creates 'AOI21X2' in the current top level. With \".\", GOF creates 'AOI21X2' new instance in hierarchy \"u_qcif/u_num2/u_spare1\".\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_standcellmapping.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_standcellmapping.txt", "chroma:document": "In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design. GOF supports Standard Spare Cells and Metal Configurable Gate Array Spare Cells post-mask metal only ECO.\n\nFigure 17: Metal Only ECO\n2.3.1 Standard Cells Spare Gates Mapping\nGOF employs an internal synthesis engine to map patch logic onto spare gates. These spare gates must consist of the following spare type combinations.\n\n  Two ports 'and/or' gates, 'inv' gates and flops, 'mux' is optional.\n  Two ports 'nand/nor' gates, 'inv' gates and flops, 'mux' is optional.\n  Two ports 'nand/nor/and/or' gates, 'inv' gates and flops, 'mux' is optional.\n\nOut of the three combinations, the second combination has the least area and the third combination has the best performance in metal only EOC. \nIn Figure 18, the circuit produced by ECO on the left-hand side contains arbitrary standard cells. During the mapping process, gates of type MUX and flop are mapped directly onto the spare gates, as they have a one-to-one correspondence with the spare gate list. However, for more complex cell types such as AO32, they must be synthesized and mapped onto three AND gates and one NOR gate.\n\nFigure 18: Standard Cells Spare Gates Mapping\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_stepstodofullfuneco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_stepstodofullfuneco.txt", "chroma:document": "2.2.2 Steps to do automatic functional ECO\nSteps for an automatic functional ECO:\n\n  Modify the original RTL\n  Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist\n  Create GOF ECO script:\n    \n      Specify ECO name in 'setup_eco'\n      Load Liberty files and Verilog libraries\n      Load the Reference Netlist and the Implementation Netlist\n      Fix the design by 'fix_design'\n      Report ECO status and write out ECO results\n    \n  \n  Run the above ECO script by \"gof -run eco_script.pl\"\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_stepstodomanecoscript.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_stepstodomanecoscript.txt", "chroma:document": "2.6.2 Steps to do Manual ECO In Scripts\nA typical situation for a Manual ECO:\n\n\tRun LEC on modified RTL to Implementation Netlist\n\tCollect the failing points in the above run\n    Create a GOF ECO script:\n    \n\t  Define ECO name in &lsquo;setup_eco&rsquo;\n\t  Load Standard Cell libraries and Verilog libraries\n\t  Load Implementation Netlist\n\t  Locate ECO point\n\t  Use ECO APIs to fix the logic\n      Report ECO status and write out ECO results\n    \n\tRun the script\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_stepstorungatearray.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_stepstorungatearray.txt", "chroma:document": "2.4.4 Steps to do gate array spare cells ECO\nA typical process for gate array spare cells ECO:\n\n  Modify the original RTL\n  Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist\n  Create GOF ECO script:\n    \n      Specify ECO name in 'setup_eco'\n      Load Liberty files and Verilog libraries\n      Load the Reference Netlist and the Implementation Netlist\n      Fix the design by 'fix_design'\n      Load LEF files\n      Load DEF files\n      Extract gate array spare cells and functional cells by 'get_spare_cells'\n      Run 'map_spare_cells' to convert the patch all gate array functional cells type and map to optimal gate array spare cells\n      Report ECO status and write out ECO results\n    \n  \n  Run the above ECO script by \"gof -run eco_script.pl\"\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_stepstorunmetaleco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_stepstorunmetaleco.txt", "chroma:document": "2.3.5 Steps to do automatic Metal Only ECO\nA typical process for an automatic Metal Only ECO:\n\n  Modify the original RTL\n  Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist\n  Create GOF ECO script:\n    \n      Specify ECO name in 'setup_eco'\n      Load Liberty files and Verilog libraries\n      Load the Reference Netlist and the Implementation Netlist\n      Fix the design by 'fix_design'\n      Load DEF file, optional\n      Load LEF file, optional. It's useful in LayoutViewer feature\n      Create Spare Gates List by Spare Gates pattern or by reading in spare list file\n      Run 'map_spare_cells' to remap the patch from 'fix_design' command to all spare -type gates patch netlist and select the closest spare instances for each gate in the patch netlist\n      Report ECO status and write out ECO results\n    \n  \n  Run the above ECO script by \"gof -run eco_script.pl\"\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_svffilessupport.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_svffilessupport.txt", "chroma:document": "2.2.6 SVF files support\nWhen working with designs that include multibit flops or significant name changes, SVF files can be a valuable tool for facilitating key point mapping. Although multibit flops are used to reduce silicon area and power consumption, the different combinations of single bit flop instances in each multibit flop instance can create challenges for key point mapping, especially when combined with name changes. Additionally, backend tools may split or merge multibit flops, further complicating the process. To avoid these challenges and ensure accurate key point mapping, it's highly recommended to load SVF files when working with multibit flops. For more information on this topic, please refer to the Multibit Flops in ECO section.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_synsubmod.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_synsubmod.txt", "chroma:document": "2.2.5 Synthesize sub-modules only\nPerforming a complete top-level netlist synthesis can be time-consuming. GOF provides APIs enabling the integration of newly synthesized sub-modules into the original pre-layout netlist, along with updates to the top-level SVF file. This incremental approach allows the generation of the large top-level netlist and the top-level SVF file, resulting in significant time and effort savings. At the RTL level, designers identify modified RTL modules during ECO and synthesize them to create netlist and SVF files. Some altered RTL modules, particularly sub-parent modules with only sub-module instantiations, may not require synthesis.\nIn Figure 4, only two sub-modules, SUB_MOD31 and SUB_MOD32, require re-synthesis in the extensive SOC_TOP design. Their parent module has only experienced connection changes and remains in netlist format, eliminating the need for synthesis. The example below illustrates how to process these files and generate a new SOC_TOP level netlist and SVF file.\n\nFigure 4: Sub-modules to be synthesized\nStep 1: Add missing DFT ports\nThe newly synthesized sub-modules may lack certain ports present in the original netlist. Notably, ports essential for scan in and scan out are typically added by the DFT tool. Since the DFT process is not applied to the new synthesized sub-modules, it's necessary to incorporate these ports as dummy ones within the modules to avoid syntax errors.\nThe procedure for incorporating DFT ports into the newly synthesized modules is as follows:\nuse strict;\nread_library(\"tsmc.lib\");\nread_design(\"-ref\", \"SOC_TOP.pre_layout.gv\");# Read in the original pre_layout netlist\nread_design(\"-imp\", \"SUB_MOD31.new_syn.gv\");# Read in new synthesized netlist\nset_tree(\"ref\");\nset_top(\"SUB_MOD31_1\"); # The old pre-layout netlist may have this module with prefix or suffix added in uniquify\nmy @ref_port_ins = get_ports(\"-input\");\nmy @ref_port_outs = get_ports(\"-output\");\nset_tree(\"imp\");\nset_top(\"SUB_MOD31\");\nmy @imp_port_ins = get_ports(\"-input\");\nmy @imp_port_outs = get_ports(\"-output\");\nmy $cnt = 0;\nforeach my $port (@ref_port_ins){\n  if(!grep($port eq $_, @imp_port_ins)){ # The input port is not in the new synthesized module\n    new_port($port, \"-input\");\n    gprint(\"$cnt: Warning input $port is not in the new synthesized sub-module\\n\"); $cnt++;\n  }\n}\nforeach my $port (@ref_port_outs){\n  if(!grep($port eq $_, @imp_port_outs)){ # The output port is not in the new synthesized module\n    new_port($port, \"-output\");\n    gprint(\"$cnt: Warning output $port is not in the new synthesized sub-module\\n\"); $cnt++;\n  }\n}\nwrite_verilog(\"SUB_MOD31.dft_ports_added.gv\");\nexit;\n\nThe identical process should be executed on SUB_MOD32 to include the necessary DFT-related ports.\nStep 2: Replace sub-modules netlist and SVF\nDuring this step, the DFT ports added netlist and SVF files of the synthesized sub-modules are read to substitute the original pre-layout netlist and SVF files.\nThe procedure for replacing netlist and SVF:\nread_library(\"tsmc.lib\");\nread_svf(\"-imp\", \"SOC_TOP.pre_layout.svf\");\nread_design(\"-imp\", \"SOC_TOP.pre_layout.gv\");\nread_sub_module_svf(\"SUB_MOD31.svf.txt\", \"-module\", \"SUB_MOD31_1\", \"-syn_module\", \"SUB_MOD31\");\nread_sub_module_svf(\"SUB_MOD32.svf.txt\", \"-module\", \"SUB_MOD32_1\", \"-syn_module\", \"SUB_MOD32\");\nread_sub_module_netlist(\"SUB_MOD31.dft_ports_added.gv\", \"-module\", \"SUB_MOD31_1\", \"-syn_module\", \"SUB_MOD31\");\nread_sub_module_netlist(\"SUB_MOD32.dft_ports_added.gv\", \"-module\", \"SUB_MOD32_1\", \"-syn_module\", \"SUB_MOD32\");\nread_sub_module_netlist(\"SUB_MOD3.new.v\", \"-module\", \"SUB_MOD3_1\", \"-syn_module\", \"SUB_MOD3\", \"-sub_only\"); # Need sub_only option\n\nreplace_sub_module_netlist(\"SOC_TOP.new_reference.gv\"); # Replace netlist should be run first\nreplace_sub_module_svf(\"SOC_TOP.new_reference.svf\");    # Then replace SVF\n\n\nAfter the generation of both the top-level netlist and SVF files, they can be incorporated into the complete top-level automatic ECO process.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_tcloutaftergatearray.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_tcloutaftergatearray.txt", "chroma:document": "2.4.6 TCL output file format after Gate Array ECO\n\ncurrent_instance\n\ncurrent_instance up_ma/utx_afe_if\n\ncreate_net eco_ganet_wire270244\n\ncreate_net eco_ganet_gofrev_net_on19915\n\ncreate_net eco_ganet_wire270246\n\ncreate_net eco_ganet_gofrev_net_on19913\n\ndisconnect_net [get_nets n_223] [get_pins slow_cnt_reg_1/D]\n\nconnect_net [get_nets eco_ganet_wire270244] [get_pins slow_cnt_reg_1/D]\n\ncreate_cell eco_gacell_gofrev_inst_19916 GND2D1\n\ncreate_cell eco_gacell_gofrev_inst_19914 GOR2D1\n\ncreate_cell eco_gacell_inst270245 GMX2D1\n\ncreate_cell eco_gacell_gofrev_inst_19912 GAN2D1\n\nconnect_net [get_nets eco_ganet_gofrev_net_on19915] [get_pins eco_gacell_gofrev_inst_19916/A]\n\nconnect_net [get_nets slow_cnt_2] [get_pins eco_gacell_gofrev_inst_19916/B]\n\nconnect_net [get_nets eco_ganet_wire270244] [get_pins eco_gacell_gofrev_inst_19916/Y]\n\nconnect_net [get_nets eco_ganet_gofrev_net_on19913] [get_pins eco_gacell_gofrev_inst_19914/A]\n\nconnect_net [get_nets xg_prbs_0] [get_pins eco_gacell_gofrev_inst_19914/B]\n\nconnect_net [get_nets eco_ganet_gofrev_net_on19915] [get_pins eco_gacell_gofrev_inst_19914/Y]\n\nconnect_net [get_nets n_221] [get_pins eco_gacell_inst270245/A]\n\nconnect_net [get_nets slow_cnt_0] [get_pins eco_gacell_inst270245/B]\n\nconnect_net [get_nets fast_data_9] [get_pins eco_gacell_inst270245/S0]\n\nconnect_net [get_nets eco_ganet_wire270246] [get_pins eco_gacell_inst270245/Y]\n\nconnect_net [get_nets n_223] [get_pins eco_gacell_gofrev_inst_19912/A]\n\nconnect_net [get_nets eco_ganet_wire270246] [get_pins eco_gacell_gofrev_inst_19912/B]\n\nconnect_net [get_nets eco_ganet_gofrev_net_on19913] [get_pins eco_gacell_gofrev_inst_19912/Y]\n\nset_cell_location -ignore_fixed -coordinates \"253.84 413.28\" eco_gacell_inst270245\n\nset_cell_location -ignore_fixed -coordinates \"250.42 390.60\" eco_gacell_gofrev_inst_19912\n\nset_cell_location -ignore_fixed -coordinates \"288.04 497.70\" eco_gacell_gofrev_inst_19914\n\nset_cell_location -ignore_fixed -coordinates \"204.25 267.12\" eco_gacell_gofrev_inst_19916\n\ncurrent_instance\n\nsize_cell FILLER_impl0_7256 GFILL3\n\nsize_cell FILLER_impl1_30700 GFILL2\n\ncurrent_instance\n\nremove_cell FILLER_impl1_20939\n\nremove_cell FILLER_impl1_40219\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_tienetcell.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_tienetcell.txt", "chroma:document": "2.2.13 Tie High Tie Low nets\nBy default, GOF uses 1'b0 for tie low net and 1'b1 for tie high net. Some designs may prefer tie cell over 1'b0/1'b1. API set_tiehi_net and set_tielo_net can be used to control which tie format is used. To overwrite the default 1'b0/1'b1, simply set empty argument to the APIs.\n\n# Set empty argument to set_tiehi_net/set_tielow_net to use Tie Cells\nset_tiehi_net(\"\"); # Tie High cell will be used instead of 1'b1\nset_tielo_net(\"\"); # Tie Low cell will be used instead of 1'b0\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_timingbeforeaftereco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_timingbeforeaftereco.txt", "chroma:document": "2.10.2 Timing before ECO\nIn order to report the timing in paths of interest before a functional ECO, it is necessary to specify the option of 'from,' 'to,' or 'through' in the report_timing function. By comparing the numbers obtained before and after a functional ECO, an appropriate timing ECO method can be selected.\n2.10.3 Timing after ECO\nAfter performing a functional ECO, report_timing can utilize the 'from,' 'to,' or 'through' options. If the function is executed without specifying any of these options, it will report the timing of paths that traverse the ECO instances.\n\nFigure 29: Report timing on paths through ECO instances\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_geco_tstitchscanchain.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.geco_tstitchscanchain.txt", "chroma:document": "2.2.14 Stitch new flops into scan chain\nTo prevent any loss of DFT coverage, it is recommended to integrate new flops added in an ECO into the existing scan chains. Industrial data suggests that in a design with 100K flops, 100 newly added non-scan flops can lead to a DFT coverage loss of over 0.1%. Such loss of DFT coverage is unacceptable for high-reliability chips, such as those used in automobiles. Therefore, if there are any new flops introduced in a functional ECO, it is necessary to redo the scan chain to incorporate the new flops.\n\nFigure 14: Stitch scan chain\nThere are multiple methods available in GOF to insert new flops into scan chains. One option is to utilize the 'stitch_scan_chain' API, which automatically integrates the new flops into the scan chains. Alternatively, there are several netlist processing APIs that can be used to manually insert the new flops into the scan chains.\nAutomatic mode to insert flops into a scan chain in the local modules\nAn automatic method can be used to integrate flops into a scan chain within local modules. In the following example script, suppose the 'fix_design' command adds eight new flops named 'state_new_reg_0' to 'state_new_reg_7'. To integrate these flops into the scan chain within the local module: \n\n# API stitch_scan_chain without any argument to insert new flops in the local modules\nstitch_scan_chain();\n\n\nAutomatic mode to insert flops before one flop\nGOF offers an automatic method to insert new flops before a specified flop instance. Users can identify the instance name of one flop, and GOF will insert all new flops into the scan chain before that instance.For instance, let's say it is required to integrate all the new flops into the scan chain prior to the instance named 'u_pixel_ctrl/pulse_reg':\n\n# API stitch_scan_chain with -to option\nstitch_scan_chain('-to', 'u_pixel_ctrl/pulse_reg');\n\n\nManual mode to connect up all new flops\nThe scan chain can be re-connected up manually by ECO APIs. And new scan in/out ports are created.\n\n\n# GOF ECO script, run_manual_stitch_scan_chain_example.pl\nuse strict;\nundo_eco; # Discard previous ECO operations\nsetup_eco(\"eco_manual_stitch_scan_chain_example\");# Setup ECO name\nread_library(\"art.5nm.lib\");# Read in standard library\nread_svf(\"-ref\", \"reference.svf.txt\");       # Optional, must be loaded before read_design, must be in text format\nread_svf(\"-imp\", \"implementation.svf.txt\");  # Optional, must be loaded before read_design, must be in text format\nread_design(\"-ref\", \"reference.gv\");# Read in Reference Netlist\nread_design(\"-imp\", \"implementation.gv\");# Read in Implementation Netlist Which is under ECO\nset_top(\"topmod\");# Set the top module\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nfix_design;\nsave_session(\"current_eco_name\"); # Save a session for future restoration\nset_error_out(0); # Don't exit if finds error\nmy @flops = get_cells(\"-hier\", \"-nonscan\"); # Find all new flops that are not in scan chain yet\n# @flops can be defined by reading a list file\nif(scalar(@flops)){ # If there are new flops, start the work\n  new_port(\"so1\", \"-output\"); # New a scan out port so1\n  new_port(\"si1\", \"-input\"); # New a scan in port si1\n  my $cnt = 0;\n  my $now_si;\n  foreach my $flop (@flops){\n    $cnt++;\n    if(is_scan_flop($flop)==0){\n      my $flop_name = get_ref($flop);\n      my $scanflop = get_scan_flop($flop_name); # If the flop is not scan type, change to scan type flop\n      change_gate($flop, $scanflop);\n    }\n    if($cnt==1){\n      change_port(\"so1\", \"$flop/Q\"); # The first flop drives the new scan out port\n    }else{\n      change_pin($now_si, \"$flop/Q\");\n    }\n    $now_si = \"$flop/SI\";\n    change_pin(\"$flop/SE\", \"te\"); # All scan enable pin is connected to scan enable signal\n  }\n  change_pin($now_si, \"si1\"); # The last flop has the new scan in port driving SI pin\n}\nwrite_verilog(\"eco_verilog.v\");# Write out ECO result in Verilog\nexit; \n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_coneofinf.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_coneofinf.txt", "chroma:document": "3.1.3 Cone of Influence\nSPFM and LFM metrics can be calculated in two methods, rough mode and detail mode. The rough mode is done by structural analysis of the Cone of Influence. The detail mode is calculated by formal analysis of the Cone of Influence. \nTwo types of strobing points shall be defined for the Cone of Influence extraction.\nObservation PointsDiagnostic Points\nThe observation points are the outputs or registers that are impacted by the injected faults which affect functional safety and violate safety goal. The diagnostic points are the outputs or registers to check if injected faults can be detected at these strobing points or perceived by the up level driver.\nThe logic back traced starting from the observation points and the diagnostic points all the way to the inputs or black boxes. The Cone of Influence (COI) is created for the observation points and the diagnostic points respectively. Each cell and each input port in the cones will be injected faults according to the Fault Model section.\n\nFigure 31: Cone of Influence\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_debugonefault.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_debugonefault.txt", "chroma:document": "3.2.2 FUSA Debug One Fault\nThe API verify_faults can run on an individual fault to check if the fault can propagate to the observation points. If the fault is observable, a VCD file can be dumped to show how to toggle the input ports cycle by cycle to propagate the fault. All internal signals waveforms are captured in the VCD file.\nThe following script is to check if one SEU fault can propagate. If yes, a VCD file is dumped:\n\nset_log_file(\"spfm_lfm.log\");     # Set log file name\nread_library(\"art.5nm.lib\");      # Read in liberty file\nread_design('-imp', 'ecc_process.v'); # Read in the design block\nset_top(\"ecc_top\");               # Set the top module name\nset_pin_constant(\"test_mode\", 0); # Set pin constraint\nset_observe_points(\"data_out*\");  # data_out[31:0] affects functional safety\nset_observe_points(\"synd_out\");   # synd_out affects functional safety\n# To check if the fault can be propagated to the detect points, set_observe_points on the detect points\nverify_faults(\"u_ecc_ops/bit_reg:SEU\", \"-vcd\", \"debug_seu.vcd\");    # Check if the Single Event Upset on the flop can propagate\ngexit;\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_faltsinjectveri.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_faltsinjectveri.txt", "chroma:document": "3.1.6 Faults Injection Formal Verification\nThe formal COI analysis needs to be run to get the final accurate metrics. For each fault injected, GOF Formal either proves that a path exists to propagate the fault to the observation or diagnostic points, or disprove there is such path. A path means by toggling input ports in some limited clock cycles, the fault can propagate to the observation/diagnostic points.\nGOF Formal doesn't require stimulus nor is a testbench required. The tool automatically determines the stimulus. For each fault injected, two designs are compared to see if the specified outputs are equal. One design is the fault injected design, the other is the original design. The specified outputs are the observation points or the diagnostic points set by user. The faults to be injects can be thousands or millions. GOF Formal uses cluster command to fully utilize the cluster computing power. Thousands of jobs can be submitted in parallel to the cluster machines with only one license being used.\nAfter the detail formal COI analysis of the above example, the residual fault number is 178, and the final SPFM is 96%. The latent fault number is 260, so the final LFM is 94%.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_falutmodel.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_falutmodel.txt", "chroma:document": "3.1.2 Fault Model\nGOF Formal injects faults to each input port and each pin of logic gates. Each input port has stuck-at 0 and stuck-at 1 faults injected. Every combinational gate has stuck-at 0 and stuck-at 1 faults injected into each pin. For flip-flop, stuck-at 0 and stuck-at 1 faults are injected into each data and clock pin. And flip-flop has Single Event Upset (SEU) fault injected to the state in random time.\n\nFigure 30: Fault model for logic gates\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_goformaloverview.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_goformaloverview.txt", "chroma:document": "3.1 GOF Formal\nGOF Formal is one of the function components integrated in GOF platform. It provides a formal method to calculate fault coverage in an IC design in functional safety.\nISO26262 defines functional safety as \"the absence of unreasonable risk due to hazards caused by malfunctioning behavior of electrical and electronic systems\". Four ASILs are proposed to represent four degrees of automotive hazards. In IC component, the coverage in the ASIL requirement is the fault coverage in the logic circuit. Specifically, single point fault metric (SPFM) and latent fault metric (LFM) should meet minimum numbers for the corresponding ASIL levels. The following table lists the three ASIL levels with specific coverage numbers defined in the standard. \n\n\nASILSPFMLFM\n\nB&ge;90%&ge;60%\n\nC&ge;97%&ge;80%\n\nD&ge;99%&ge;90%\n\n\nThe traditional method to calculate the fault coverage is pure simulation based. It's inefficient and time consuming. GOF Formal provides a formal and efficient way to calculate the SPFM and LFM numbers of a logic design. It can work in a standalone mode to calculate the coverage metric. And it can also work as a supplemental method to cover the faults left over from simulation based process."}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_metricsimprovement.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_metricsimprovement.txt", "chroma:document": "3.1.7 FUSA Metrics Improvement\nIn order to improve the fault coverage, safety mechanisms should be built in the IC design. There are several approaches for safety mechanism implementation.\n\nRedundancy design, double modular and triple modular redundancy\nParity or error correction implementation\nPeriodically self check\n\nIn Figure 32, a safety mechanism can be a double modular design or ECC design. The diagnostic points would be the alarm bits in the double modular error bit, or ECC error recovering signals. For SPFM metric improvement, those gates in Area A that are not covered by safety mechanism can be modified to support TMR (Triple Module Redundancy), so that &lambda;SPF can be further reduced and SPFM improved accordingly. See this TMR ECO Case\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_roughmethodbycoi.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_roughmethodbycoi.txt", "chroma:document": "3.1.5 Rough Method by COI Analysis\nIn the rough method calculation by analyzing COI structure, the best and worst metrics can be quickly calculated.\nIn the example shown in Figure 32, the faults are distributed as:\nSafe Faults: 550\nResidual Faults in Area A: 122\nMultiple Point Faults in Area B: 1208\nMultiple Point Faults in Area C: 2582\n\nThe best SPFM assumes the faults in Area B are propagatable to the diagnostic points. The single-point/residual faults &Sigma;(&lambda;SPF+&lambda;RF) has number 122 only in Area A. Therefore, the best case SPFM is 97.3%.\nThe worst SPFM assumes the faults in Area B are all residual faults, so &Sigma;(&lambda;SPF+&lambda;RF) has number 1330 which is 1208 plus 122, and get calculated metric to be 70%.\nThe best LFM assumes the faults in Area C are all detectable. &Sigma;(&lambda;MPF_UD) is zero, So LFM is 100% in the rough structural COI analysis.\nThe worst LFM assumes the faults in Area C can not propagate to the diagnostic points, and they are not detectable. Therefore, &Sigma;(&lambda;MPF_UD) has the number of 2582, and the worst LFM is 59.5%.\nFigure 32: Example fault numbers in COI\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_scriptspfmlfmcal.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_scriptspfmlfmcal.txt", "chroma:document": "3.2 FUSA Example Code\n3.2.1 Script for SPFM and LFM Calculation\nOne example script for SPFM and LFM calculation:\n\nset_log_file(\"spfm_lfm.log\");     # Set log file name\nread_library(\"art.5nm.lib\");      # Read in liberty file\nread_design('-imp', 'ecc_process.v'); # Read in the design block\nset_top(\"ecc_top\");               # Set the top module name\ncreate_clock(\"data_clk\", 2);\nset_pin_constant(\"test_mode\", 0); # Set pin constraint\nset_observe_points(\"data_out*\");  # data_out[31:0] affects functional safety\nset_observe_points(\"synd_out\");   # synd_out affects functional safety\nset_detect_points(\"sb_err_o\");    # Safety mechanism detecting output\nset_detect_points(\"db_err_o\");    # Safety mechanism detecting output\nverify_faults(\"-full\");           # Calculate and print SPFM and LFM, Use verify_faults(\"-coi\") for fast SPFM/LFM calculation \ngexit;\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_singlepointfaultandlatentfault.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_singlepointfaultandlatentfault.txt", "chroma:document": "3.1.1 Single Point Fault and Latent Fault\nSingle point fault (SPF) is the fault in the IC design that leads directly to the violation of a safety goal which is defined as observation point in the \"Cone of Influence\" section below and no fault in the IC circuit is covered by any safety mechanism. However, if there is safety mechanism, but the fault can't be covered by the safety mechanism, the fault is called residual fault according to the standard. In calculating SPFM, residual fault is treated as single point fault. Latent faults are multiple-point faults not detected by a safety mechanism or perceived by the driver. The latent fault metric is to determine whether coverage by safety mechanisms is sufficient to protect against risk from latent faults in the IC design.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gformal_spfmlfmcal.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gformal_spfmlfmcal.txt", "chroma:document": "3.1.4 SPFM and LFM Calculation\nIn Figure 31, all faults that are outside of the two COIs are safe faults.\nArea A has faults that are observable but not detectable, so they can be classified as residual faults. And they are called single point faults if safety mechanism is not implemented for the design, in which case the diagnostic points are not present and Area B and Area C are zero size. However, if they don't propagate to the observation points in the detail formal COI analysis, they can be classified as multiple point faults. For example, TMR is implemented on Area A. The majority faults in this area will become multiple point faults.\nArea B has faults that are classified as multiple point faults, since they are observable and detectable. In the rough structural COI analysis, the worst SPFM metric can be calculated by assuming them as all residual faults and the best SPFM metric by assuming them as propagatable to the diagnostic points. So the detail formal COI analysis will determined the fault classification.\nArea C has faults that are classified as detectable multiple point faults, but they are not observable. The detail formal COI analysis will be run on Area C to check if the faults in this area can not propagate to the diagnostic points, then they can be classified officially as latent faults. The best and worst LFM metrics can be gained by the rough structural COI analysis method.\nThe Single Point Fault Metric (SPFM) can be calculated according to the following equation. \nSPFM = 1 - &Sigma;(&lambda;SPF+&lambda;RF)/&Sigma;(&lambda;) \nwhere:\n&lambda;SPF: Single Point Fault when there is no safety mechanism\n&lambda;RF: Residual Fault\n&lambda;: Any Fault\nThe Latent Fault Metric (LFM) can be calculated according to the following equation.\nLFM = 1 - &Sigma;(&lambda;MPF_UD)/&Sigma;(&lambda;MPF - &lambda;SPF - &lambda;RF)\nwhere:\n&lambda;MPF_UD: Multiple Point Fault not detected by the driver\n&lambda;MPF: Any Multiple Point Fault\n&lambda;SPF: Single Point Fault when there is no safety mechanism\n&lambda;RF: Residual Fault\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofdebug_guidetail.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofdebug_guidetail.txt", "chroma:document": "6 GOF Debug: Netlist Debug and Schematic\nFor all GUI mode operations and schematic usage, refer to this chapter."}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecguimode.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecguimode.txt", "chroma:document": "\n  GUI mode ECO\n\nGUI mode ECO has advantage of fast ramping up. It's good for small size ECOs. The incremental schematic feature is very helpful for analyzing the netlist before the next step is decided.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofechiereco.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofechiereco.txt", "chroma:document": "\n  Hierarchical ECO\n\nGOF supports hierarchical ECO by set the ECO scope to the sub-modules. Some Logic Equivalence Check cases can only be resolved in flatten mode. Since GOF only focuses on the modules or spots that user specifies, it can avoid to get false non-equivalence in hierarchical netlist.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecintegratedenv.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecintegratedenv.txt", "chroma:document": "\n  Integrated environment\n\nThe ECO modes listed above are integrated into one work environment seamlessly. The mixing of ECO modes can produce most optimal ECO result. For example, automatic ECO and manual script ECO can be done in one ECO script, so that the minimum size ECO patch can be achieved.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecmetalonly.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecmetalonly.txt", "chroma:document": "\n  Metal Only ECO\n\nWhen ECO is done in either automatic mode or manual mode, 'map_spare_cells' command is run to convert the newly added cells to spare gate types cells. Users can control only spare gate type cells being used in manual mode ECO, so that the converting stage can be bypassed. The flow supports both standard spare cells and gate array spare cells.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecoautomode.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecoautomode.txt", "chroma:document": "\n\nAutomatic mode ECO\n\nThe automatic functional ECO is carried out using a GOF ECO script, which requires an Implementation Netlist that is currently under ECO and a Reference Netlist that is re-synthesized from the modified RTL with the same constraints as the pre-layout netlist. The 'fix_design' API is utilized to execute a top-down global ECO. GOF leverages its built-in Logic Equivalence Check engine to identify and analyze non-equivalent points in both the top-level module and its sub-modules. Logic patches are generated to rectify any non-equivalent modules, and the final patches are optimized circuits that minimize the gate count required to make the Implementation Netlist equivalent to the Reference Netlist. Finally, the 'map_spare_cells' API is used to map these patches to spare-type-gates.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecofeatures.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecofeatures.txt", "chroma:document": "2.1 Netlist ECO Solutions\nGOF ECO incorporates the following features:\n  Automatic functional ECO uses the Reference Netlist to fix the Implementation Netlist\n  RTL-guided automatic functional ECO produces quicker and more targeted ECO results\n  RTL patch ECO can speed up the turnaround time by avoiding full-scale and lengthy synthesis processes\n  Built-in logic equivalence check engine makes the ECO self contained\n  Parallel processing fully utilizes multiple CPU cores to reduce ECO run time\n  Standard spare cells in Metal only ECO remaps only spare gates in post-mask ECO\n  Metal Configurable Gate Array Spare Cells makes larger Metal Only ECO possible\n  Auto mode ECO mixed with GUI and Script mode ECO optimizes ECO patches to the full extent\n  ECO retargeting achieves huge netlist ECO in short period of time\n  DFT friendly maintains test logic untouched to avoid second time ECO in late design stage\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecomanmode.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecomanmode.txt", "chroma:document": "\n  Manual mode ECO\n\nIf the ECO changes are limited in scope and size or involve repetitive operations such as adding inverts on a bus, it is more efficient to use the manual mode ECO. This mode is a better option as it results in fewer final gates being touched compared to automatic mode ECO. Additionally, both automatic and manual modes can be combined and executed within a single GOF ECO script.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gofecovariousmethods.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gofecovariousmethods.txt", "chroma:document": "\nGOF ECO utilizes various advanced ECO methodologies, as netlist ECO can vary significantly in terms of size and complexity across different cases and companies. To provide users with maximum flexibility, GOF offers a range of methodologies to choose from, allowing them to select one or multiple options based on the specific requirements of the changes involved.\n\nFigure 1: Complete Functional ECO Solutions\n\n  Automatic ECO and Manual ECO\n  RTL to Netlist and Netlist to Netlist\n  Script Mode and GUI Mode\n  Metal Only ECO and All Layers ECO\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_goflec_net2netlec.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.goflec_net2netlec.txt", "chroma:document": "5.1 GOF LEC Overview\nThe GOF platform features a logic equivalence checker tool called GOF LEC. While not mandatory, the tool can benefit from SVF files in certain cases. It is strongly advised to utilize SVF files if they are obtainable. The two designs being compared can either be in RTL or Netlist format, with RTL supporting SystemVerilog2017. The read design method differs depending on whether RTL or Netlist is being supported.\n\nFigure 38: GOF LEC Engine\n5.1.1 Netlist to Netlist LEC\nThe following is the example script for Netlist to Netlist LEC:\n# LEC script, run_net2net_lec.pl\nuse strict;\nread_library(\"art.5nm.lib\"); # Read in standard library\nread_svf('-ref', 'AI2023_top_syn.svf.txt'); # Optional, must be loaded before read_design, must be in text format\nread_svf('-imp', 'AI2023_top_pr.svf.txt');  # Optional, must be loaded before read_design, must be in text format\nread_design('-ref', 'AI2023_top_syn.v'); # Read in the Reference Netlist, prelayout netlist\nread_design('-imp', 'AI2023_top_pr.v'); # Read in the Implementation Netlist, postlayout netlist\nset_top(\"AI2021_top\"); # Set the top module\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nmy $non_equal = run_lec; # Run logic equivalence check on the two netlists\nif($non_equal){\n  gprint(\"LEC failed with $non_equal non-equivalent points\");\n}else{\n  gprint(\"LEC passed\");\n}\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_goflec_rtl2netlec.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.goflec_rtl2netlec.txt", "chroma:document": "5.1.2 RTL to Netlist LEC\nThe following is the example script for RTL to Netlist LEC:\n# LEC script, run_rtl2net_lec.pl\nuse strict;\nread_library(\"art.5nm.lib\"); # Read in standard library\nset_inc_dirs(\"-ref\", \"inc_dir_path/include\");\nset_define(\"-ref\", \"NO_SIMULATION\", 1);\nmy @rtl_files = (\"cpu_core.sv\", \"mem_ctrl.sv\", \"display_sys.sv\", \"chip_top.sv\");\nread_rtl(\"-ref\", @rtl_files); # Read in the Reference RTL files\nread_svf('-imp', 'chip_top.svf.txt');  # Optional, must be loaded before read_design, must be in text format\nread_design('-imp', 'chip_top.v'); # Read in the Synthesis Netlist\nset_top(\"CHIP_TOP\"); # Set the top module\nset_ignore_output(\"scan_out*\");\nset_pin_constant(\"scan_enable\", 0);\nset_pin_constant(\"scan_mode\", 0);\nelab_rtl(); # RTL processing\nmy $non_equal = run_lec; # Run logic equivalence checking on RTL vs Netlist\nif($non_equal){\n  gprint(\"LEC failed with $non_equal non-equivalent points\");\n}else{\n  gprint(\"LEC passed\");\n}\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_automaticecoapis.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_automaticecoapis.txt", "chroma:document": "4.1.4.2 Automatic ECO APIs\nThese APIs are for Automatic ECO\n\nfix_design: ECO command to fix the design in automatic ECO (LLM: automatic eco)\nfix_logic: ECO command. Fix listed points\nmap_spare_cells: ECO command. Map all new created cells to spare cells (LLM: metal only)\n\nCombining netlist browsing APIs, users can come up a short script to do complicated changes.\nFor example, to fix all modules named \"tx_machine_*\"\n\nmy @modules = get_modules(\"-hier\", \"tx_machine_*\");\nfix_modules(@modules);\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_bexampletosch.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_bexampletosch.txt", "chroma:document": "4.3.6 Counter-example back-annotated to schematic\nIn GOF shell 'GOF > sch the_non_equivalent_point -both', so that both instances/ports in the Implementation and Reference Netlists are loaded into a schematic. Select both of them, right the mouse and select 'LEC Debug the_non_equivalent_point'. After the run finishes, use mouse middle button to expand the schematic, and the counter-example values are back-annotated on the schematic.\n\nFigure 36: Debug non-equivalence by counter-example back-annotated\nTwo corresponding flops, two corresponding output ports, and any two nets in the Reference Netlist and the Implementation Netlist can be compared in debug mode. In cases where the outcome is non-equivalent, the counterexample will be presented to the gate pins on the schematic.\n\nFigure 37: Counter-example back-annotated on the schematic\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_breakfordebug.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_breakfordebug.txt", "chroma:document": "4.3.5 Break points for debug\n'sch' fast schematic launch command can be used as break points for debug. For example, 'sch' commands are inserted in GOF script, when the tool runs to the point, a schematic is launched.\n\n&hellip;\nsetup_eco(\"eco_3821\");\nset_log_file(\"t_eco_3821.log\");\nread_library(\"art.m.simple.lib\");\nread_design(\"-imp\", \"./cdir/imp_name.v\");\nchange_pin(\"state_reg_0_/D\", \"MX2X4\", \"eco_inst_1\", \".A(-),.B(next_state[7]),.S0(sel_mode)\");\nsch(\"state_reg_0_\");\n&hellip;\n\n\n&nbsp;\nOn the schematic, user can use mouse-middle-button clicking on the pin 'D' to see if the ECO is done as expected.\n&nbsp;\n\n&nbsp;\nFigure 34: Launch schematic at break point\nNote: 'ECO' check-button is enabled automatically, since there is ECO having been done.\nTo compare with the logic before ECO, launch a new schematic by menu Schematic-&gt;'New Schematic'. On the new schematic, press 'ctrl-g' or by menu Schematic-&gt;'Load Gate' to load in the flop under ECO.\n\nFigure 35: Launch schematic before ECO\nNote: 'ECO' check-button is un-checked.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_changefloptoothertype.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_changefloptoothertype.txt", "chroma:document": "4.4.3 Change flops to other type\n4.4.3.1 Change non-reset flop type to resettable flop\n\n# Find all flops matching string \"cnt_reg\" and change each flop to resettable flop\nmy @flops = get_cells(\"*cnt_reg*\");\nforeach my $flop (@flops){\n&nbsp;&nbsp;change_gate($flop, \"DFFRQX2\", \".RD(reset_n)\");\n}\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_fastschematiclaunch.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_fastschematiclaunch.txt", "chroma:document": "4.3.4 Fast schematic launch\nIn GOF shell, GUI windows can be launched by 'start_gui' or 'sch' commands.\n'start_gui' launches netlist view window first and user can bring up schematic window from netlist view window.\n'sch' command only launches schematic window, and it doesn't enable netlist view window. So it has fast turnaround in GUI interactive debug.\nFor example,\nAfter the following command is done,\n\nchange_pin(\"u_top/u_core/u_regmod/state_reg/D\", \"XOR2X2\", \"\", \"-,new_enable\");\n\n\nRun 'sch' in 'GOF >'\n\nGOF > sch(\"u_top/u_core/u_regmod/state_reg\")\n\nThe instance is loaded into a schematic and user can click on the instance's pins to trace fanin/fanout on the schematic to see if the ECO is done as expected.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_fileipapis.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_fileipapis.txt", "chroma:document": "4.1.4.3 File IO APIs\nThese APIs are for reading/writing files.\n\nread_def: Read DEF file\nread_design: Read verilog netlist files (LLM: read verilog)\nread_file: Read timing violation report file\nread_lef: Read LEF file\nread_library: Read standard library or verilog library files (LLM: read library)\nrestore_session: Restore ECO session\nsave_session: Save ECO session\nwrite_dcsh: ECO command. Write ECO result in Design Compiler dcsh script format\nwrite_perl: ECO command to write ECO result in Perl script (LLM: result in perl)\nwrite_soce: ECO command. Write ECO result in  SOC Encounter script format\nwrite_spare_file: ECO command. Write spare cells list to a file\nwrite_tcl: ECO command to write ECO result in Design Compiler tcl script format (LLM: result in tcl)\nwrite_verilog: ECO command to write ECO result in Verilog netlist (LLM: result in verilog)\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_gofscripapilist.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_gofscripapilist.txt", "chroma:document": "4.1.3 Full API list\n\nadd_mapped_instance: Add mapped instance pair between REF and IMP\nbuffer: ECO command. Buffer high fanout ECO nets\nchange_gate: ECO command. Modify an instance in ECO\nchange_net: ECO command. Change a existing net's driver\nchange_pin: ECO command. Modify pin connection of instances by inserting gates, changing connection to other signal (LLM: change pin insert gate)\nchange_port: ECO command. Change an output port's driver, or add gate after input port \ncheck_design: Check if the netlist status, searching for unresolved modules, floating and multi-drivers \ncompare: Logic equivalence check on output port and register input pins\ncompare_nets: Check equivalence of two nets in the reference and implementation netlist\nconvert_gated_clocks: ECO command. Convert gated clocks to MUX logic.\ncreate_clock: Timing command and GOF Formal command. Create clock for fault verification\ncreate_pin_mapping_json_file: Create pin mapping file between original synthesis netlist and pre-ECO netlist\ncreate_reset: Create reset for the design\ncurrent_design: Set the current top level module (LLM: current design module)\ncurrent_instance: Set the current instance, alias of 'set_inst'\ndel_gate: ECO command. Delete gate\ndel_net: ECO command. Delete net\ndel_port: ECO command. Delete port\ndft_drc: DFT DRC checker\nelab_rtl: Elaborate on RTL design\nelaborate: Elaborate and compile RTL files\nexist_inst: Check if an instance exists (LLM: instance existence)\nexist_wire: Check if a wire exists (LLM: wire existence)\nfind_equal_nets: Find equivalent nets in IMP for the listed nets in REF, the results are printed out on the screen\nfix_design: ECO command to fix the design in automatic ECO (LLM: automatic eco)\nfix_logic: ECO command. Fix listed points\nflatten_modules: Flatten hierarchical modules in reference netlist\nget_cell_cofactors: Get combinational cell pin Shannon expansion cofactors\nget_cell_info: Get information of a module or instance (LLM: information)\nget_cells: Get all cells in the current module or sub-modules (LLM: find/get instance)\nget_conns: Get connections of net or pin in the top level module, return the leafs and the hierarchical connections (LLM: conns)\nget_coord: Get an instance's coordination (LLM: coordination)\nget_definition: Get instantiation of instance\nget_driver: Get the driver of a net or pin (LLM: driver)\nget_drivers: Get the drivers of a net or pin (LLM: drivers)\nget_instance: Get instance in the top level module\nget_instances: Get all hierarchical instances in the top level module (LLM: hierarchical instances)\nget_leaf_pin_dir: Get leaf cell pin's direction input/output/inout\nget_leafs_count: Get all leaf cells name and count in the top level module, return an array \nget_lib_cells: Get leaf gates in libraries \nget_loads: Get loads of net in the top level module, return the leafs connections (LLM: loads)\nget_loads_phase: Get loads of net with phase in the top level module, return the non-buffer/inverter leafs connections (LLM: loads with phase)\nget_logic_cone: Get logic cone of nets or pins\nget_modules: Get modules under current module (LLM: submodules)\nget_net_of: Get net name connecting to a pin (LLM: net of pin)\nget_nets: Get nets that matching pattern (LLM: matched nets)\nget_path: Get current hierarchical path (LLM: path)\nget_pins: Get pins of instance or module (LLM: pins)\nget_ports: Get all ports in the current top level module (LLM: ports)\nget_ref: Get the reference of the instance, return leaf cell name or hierarchical module name (LLM: design name)\nget_resolved: Resolve the relative path to module and leaf item\nget_roots: Get root designs name\nget_scan_flop: Get scan flop for the non scan flop (LLM: scan flop)\nget_spare_cells: ECO command. Get spare cells (LLM: metal only)\nget_spare_in_use: Get spare cells used in the ECO \ngexit: Exit the command interactive mode\ngof_version: Print out GOF version\ngprint: Print the message and save to log file (LLM: print)\nis_leaf: Check if a module or instance is leaf cell (LLM: leaf)\nis_pin_masked: Check if an instance pin has been masked in the current constraint (LLM: masked)\nis_scan_flop: Check if an instance is scan flop (LLM: scan flop)\nis_seq: Check if an instance or a leaf cell is a specific sequential cell (LLM: sequential)\nlist_wireload: Timing command. List all wireload defined in the liberty files\nmap_spare_cells: ECO command. Map all new created cells to spare cells (LLM: metal only)\nnew_gate: ECO command. Create new gate\nnew_net: ECO command. Create a new net\nnew_port: ECO command. Create a new port for the current top level module\nplace_gate: ECO command. Place an instance to a specific position\nplace_port: ECO command. Place port position\npop_top: Pop out the saved top level module from the stack and discard the current setting (LLM: pop current top design from stack)\npost_recovery: ECO command. recover deleted gates after ECO\npreserve_modules: Preserve wires in the modules listed or all modules\npush_top: Set the current top level module and push the previous setting to stack, pop_top can retrieve it (LLM: push stack current top design)\nread_def: Read DEF file\nread_design: Read verilog netlist files (LLM: read verilog)\nread_file: Read timing violation report file\nread_lef: Read LEF file\nread_library: Read standard library or verilog library files (LLM: read library)\nread_rtl: Read RTL files\nread_rtlpatch: Read RTL Patch file \nread_sdf: Read SDF Standard Delay Format file (LLM: sdf)\nread_sub_module_netlist: Read in new synthesized netlist file\nread_sub_module_svf: Read in new synthesized design SVF file\nread_svf: Read  SVF text files (LLM: svf)\nread_vcd: Read VCD file\nrename_net: ECO command. Rename a net name\nreplace_sub_module_netlist: Replace sub-module in the design by a new re-synthesized sub-module netlist and write to a new top netlist\nreplace_sub_module_svf: Replace sub-module SVF in the design by a new re-synthesized sub-module SVF file content\nreport_eco: Report ECO\nreport_spares: Report Spare cells\nreport_timing: Timing command. Report timing\nrestore_session: Restore ECO session\nrtl_compare: RTL to RTL compare\nrun: Run Netlist processing script\nrun_lec: Run Logic Equivalence Check of the Implementation Netlist vs the Reference Netlist (LLM: lec)\nsave_session: Save ECO session\nsch: Launch schematic to verify ECO\nset_auto_fix_floating: ECO setting. Enable automatic fixing floating input ports after fix_modules\nset_bfix: Enable or disable BFIX features which is for precise combinational logic fix (LLM: precise combinational) \nset_blackbox: Set Blackbox on Modules\nset_bound_opti: Set boundary optimization checking \nset_buffer: Set buffer type. The tool automatically picks one if the command is not called (LLM: buffer name)\nset_buffer_distance: Set distance limit for inserting buffer\nset_clock_uncertainty: Timing command. Set clock uncertainty\nset_cluster_command: Set cluster command in parallel fault verification\nset_cluster_timeout: Set time out for cluster command\nset_constraints: Set constraints for map_spare_cells command\nset_cutpoint_thresh: Set Cutpoint Threshold\nset_cutpoint_ultra: Set the level in doing CutPoint Ultra (LLM: cutpoint ultra)\nset_define: Set define (LLM: define variable)\nset_detect_points: set detect points\nset_disable_cross_hierarchy_merge: Set this variable to disable cross hierarchy register merging\nset_disable_lib_cache: Disable liberty file cache\nset_dont_fix_modules: Set dont fix property on modules\nset_dont_use: Set dont use property on library cells\nset_eco_effort: ECO setting. Set ECO effort\nset_eco_point_json: Set a JSON file name for saving the ECO point data. \nset_equal: ECO setting. Set two points to be equivalent in the Reference and Implementation Netlists\nset_error_out: Set error out setting\nset_exit_on_error: Whether the tool should exit when the script runs into an error\nset_exit_on_warning: Whether the tool should exit when the script runs into a warning\nset_false_path: Timing command. Set false path\nset_floating_as_zero: Set floating net as constant zero (LLM: floating zero)\nset_flop_default_eco: Set flop default eco by inverting input pin and output pin\nset_flop_merge_enable: Inside module flop merge enable\nset_high_effort: Set high ECO effort on modules (LLM: effort high)\nset_ignore_instance: ECO setting. Set ignored sequential or blackbox instances in ECO\nset_ignore_network: ECO setting. Set ignore network in ECO\nset_ignore_output: ECO setting. Set ignore output ports\nset_ignore_pin: set ignore on the pin of black box like memory in logic equivalence checking (LLM: ignore black box pin)\nset_inc_dirs: Set include directories\nset_initial_trans: Timing command. Set initial transition for clock\nset_input_delay: Timing command. Set input delay\nset_input_transition: Timing command. Set input transition to all input ports\nset_inside_mod: Set fix scope inside the current module\nset_inst: Set the current instance, alias of 'current_instance'\nset_inv: ECO setting. Set two points to be inverted in the Reference and Implementation Netlists\nset_invert: Set invert type. The tool automatically picks one if the command is not called (LLM: invert name)\nset_keep_format: Keep the format of the original verilog when ECO is done (Keep original netlist format)\nset_keep_tree: Set keeping buffer tree, so that buffer tree won't be removed in ECO\nset_keypoints_rep_in_ref: ECO setting. Replace keypoints naming in Reference Netlist.\nset_leaf: Set a hierarchical module to be leaf. Useful to stub hierarchical instances\nset_log_file: Set log file name\nset_low_effort: Set low ECO effort to speed up ECO process (LLM: speed up)\nset_mapped_point: ECO setting. Set two points mapped in Reference and Implementation Netlists\nset_mapping_method: LEC setting. Detecting flop phase inversion.\nset_max_lines: Set max output lines\nset_max_loop: Setup max loop, the tool stops logic optimization when max loop number is reached\nset_mod2mod: Set reference module mapping to implementation module\nset_mu: MU configuration, setup MU value for BDD threshold\nset_multibit_blasting: Set blasting on multibit flops \nset_multibit_output: Set multibit flops output in ECO results \nset_net_constant: Set net to a constant value in DFT constraint (LLM: constant)\nset_no_patch_opt: Disable patch optimization\nset_noexact_pin_match: ECO setting. Don't match some special pins\nset_observe_points: set observe points\nset_one_fault: Set one fault for verify_state command\nset_only_use: In optimize_patch, Only use these cells listed \nset_output_delay: Timing command. Set output delay\nset_output_load: Timing command. Set output load to all output ports\nset_phase_adjust_en: Enable phase adjusting (LLM: phase adjusting)\nset_phase_inv: ECO setting. Set flops invert phase in the Reference and Implementation Netlists\nset_physical_aware: Enable physical aware ECO \nset_pin_constant: Set pin to a constant value in DFT constraint (LLM: constant)\nset_power: Set power pins connections for leaf cell\nset_preserve: Set preserve property on instances. The tool does not remove them in ECO (LLM: preserve)\nset_quiet: Run script in quiet mode\nset_recovery_distance: Set distance limit for gates recovery in ECO\nset_remove_undsc_in_ref: ECO setting. Remove last '_' in flop instance in Reference Netlist\nset_rtl_eco_full_hier_fan: RTL ECO has full hierarchical fanout\nset_save_mapped_instance: Dump key points mapping information for LEC\nset_scan_pairs: Set scan output ports, the command is used with dft_drc\nset_sn_vs_rn: Check set pin and reset pin priority\nset_solver_timeout: Set time out for solver\nset_tiehi_net: Set tiehi net name, it is used if tiehi net is needed in ECO (LLM: tiehi)\nset_tielo_net: Set tielo net name, it is used if tielo net is needed in ECO (LLM: tielo)\nset_time_frame_limit: GOF Formal only. Set limitation for time frame in fault verification, default 35\nset_top: Set the current top level module (LLM: current top design)\nset_top_ref: Set the top level module for the Reference design (LLM: unmatched hierarchy reference)\nset_tree: Set the current tree, if there are more than one sets of databases (LLM: tree)\nset_user_match: Set match between multi-bit flops to multi-bit flops, and between multi-bit flops to single bit flop\nset_verbose: Run script in verbose mode\nset_wireload: Command for Timing Report. Set wireload for one liberty library\nset_write_verilog_remove_backslash: Enable write out verilog with backslash removal\nset_write_verilog_uniquify: Enable write out verilog in uniquified mode\nset_xm_flop_merge_enable: Cross module flop mapping and merging enable. \nsetup_eco: ECO command. Setup ECO\nsource: Run Netlist processing script. \nstart_gui: Start GUI windows\nstitch_scan_chain: ECO command. Stitch scan chain\nsuppress_errors: Suppress error messages\nsuppress_warnings: Suppress warning messages\nswap_inst: ECO command. Swap two instances with same input/output pins.\nundo_eco: ECO command. Undo eco operations, restore the database to the original state.\nverify_faults: GOF Formal only. Verify fault in stuck-0 or stuck-1 mode\nverify_state: GOF Formal only. Verify if a sequence exists to set the signal\nwrite_compare_points: Write all compare points to a report file\nwrite_dcsh: ECO command. Write ECO result in Design Compiler dcsh script format\nwrite_formality_help_files: Write formality help files including mapped instance list and modified netlist files if necessary\nwrite_perl: ECO command to write ECO result in Perl script (LLM: result in perl)\nwrite_soce: ECO command. Write ECO result in  SOC Encounter script format\nwrite_spare_file: ECO command. Write spare cells list to a file\nwrite_tcl: ECO command to write ECO result in Design Compiler tcl script format (LLM: result in tcl)\nwrite_verilog: ECO command to write ECO result in Verilog netlist (LLM: result in verilog)\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_gofscripfeaturelist.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_gofscripfeaturelist.txt", "chroma:document": "4.1.2 GOF Script APIs feature list\n\n\tCompatible with Perl\n\tAutomatic ECO with fix_design/fix_modules APIs\n\tRich ECO APIs to do manual ECO\n\tECO operations are reversible\n\tECO result can be loaded in schematic on the fly\n\tIntegrated commands to browser netlist and check design status\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_gofscripthelp.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_gofscripthelp.txt", "chroma:document": "4 Script Mode Detail Features\n4.1 GOF Script Interface\nGOF Script Interface can access and change internal netlist design database by exported APIs.\n4.1.1 Get Help for APIs\n\n\tType 'help' in interactive shell 'GOF &gt;' to list all APIs\n\tType 'help set_*' to list all APIs matching 'set_', like 'set_top', 'set_invert'\n\tType 'help individual-API' to list detail of the API\n\tVisit https://nandigits.com/gof_manual.php for online manual\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_insertgatetohierpin.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_insertgatetohierpin.txt", "chroma:document": "4.4.4 Insert gate to hierarchical instance pin\n4.4.4.1 Insert inverts to hierarchical instance pins\n\n# Find all instances matching \"tx_mac\" in module \"abc_mod\" and insert invert to 'loop_en' pin\nset_top(\"abc_mod\");\nmy @insts = get_instances(\"*tx_mac*\");\nforeach my $inst (@insts){\n&nbsp; change_pin(\"$inst/loop_en\", \"INVX1\", \"\", \"-\");\n}\n\n\n4.4.4.2 Insert AND to hierarchical instance pins\n\n# Find all instances matching \"tx_mac\" in module \"abc_mod\" and\n# AND all output pins with \"power_on\" signal.\nset_top(\"abc_mod\");\nmy @insts = get_instances(\"*tx_mac*\");\nforeach my $inst (@insts){\n&nbsp; my @pins = get_pins(\"-output\", $inst);\n&nbsp; foreach my $pin (@pins){\n&nbsp; &nbsp; my $net = get_net_of($pin); # Only add AND to those out pins driving nets\n&nbsp; &nbsp; if($net){\n&nbsp; &nbsp; &nbsp; change_pin($pin, \"AND2X2\", \"\", \".A(-),.B(power_on)\");\n&nbsp; &nbsp; }\n&nbsp; }\n}\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_insertgatetoinstpin.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_insertgatetoinstpin.txt", "chroma:document": "4.4.2 Insert gate to register instance pin\n4.4.2.1 Insert invert to flop data pin\n\n# Insert an invert to 'D' pin of flop 'abc_reg'\nchange_pin(\"abc_reg/D\", \"INVX1\", \"\", \"-\");\n\n\n4.4.2.2 Insert invert to flop output pin\n\n# Insert an invert to 'Q' pin of flop 'abc_reg'\nchange_pin(\"abc_reg/Q\", \"INVX1\", \"\", \"-\");\n\n\n4.4.2.3 Insert MUX to data pin of multiple flops\n\n# Find all flops matching string \"cnt_reg\" and insert MUX to 'D' pin of each flop,\n# so that each flop is preset to 'preset_val' when 'preset_enable' is high\nmy @flops = get_cells(\"*cnt_reg*\");\nforeach my $flop (@flops){\n&nbsp;&nbsp;change_pin(\"&#36;flop/D\", \"MUX2X2\", \"\", \".A(-),.B(preset_val),.S(preset_enable)\");\n}\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_insertgatetoport.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_insertgatetoport.txt", "chroma:document": "4.4 Typical Manual ECO operations\n4.4.1 Insert gate to port\nBoth input port and output port have the same operation\n4.4.1.1 Insert an invert to input port\n\n# Insert to input port 'in_enable'\nchange_port(\"in_enable\", \"INVX1\", \"inst_name\", \"-\"); # 'inst_name' can be empty\n\n\n4.4.1.2 Insert to output port\n\n# Insert AND2X1 to output port 'out_enable', one pin connects to the original driver,\n# the other pin is driven by 'scan_mode'\nchange_port(\"out_enable\", \"AND2X1\", \"\", \"scan_mode,-\");\n\n\n4.4.1.3 Insert inverts to multiple ports\n\n# Find all ports matching string \"abcde\" and insert invert to each port\nmy @ports = get_ports(\"*abcde*\");\nforeach my $port (@ports){\n&nbsp;&nbsp;change_port($port, \"INVX1\", \"\", \"-\");\n}\n\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_manualecoapis.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_manualecoapis.txt", "chroma:document": "4.1.4.4 Manual ECO APIs\nThese are APIs for Manual ECO.\n\nbuffer: ECO command. Buffer high fanout ECO nets\nchange_gate: ECO command. Modify an instance in ECO\nchange_net: ECO command. Change a existing net's driver\nchange_pin: ECO command. Modify pin connection of instances by inserting gates, changing connection to other signal (LLM: change pin insert gate)\nchange_port: ECO command. Change an output port's driver, or add gate after input port \ndel_gate: ECO command. Delete gate\ndel_net: ECO command. Delete net\ndel_port: ECO command. Delete port\nnew_gate: ECO command. Create new gate\nnew_net: ECO command. Create a new net\nnew_port: ECO command. Create a new port for the current top level module\n\nCombining netlist browsing APIs, a short GOF script can do very efficient ECOs.\nFor example, to add isolation cells for all output ports of a module.\n\nset_top(\"module_name\");\nmy @out_ports = get_ports(\"-output\");\nforeach my $out (@out_ports){\n&nbsp; change_port($out, \"AND2X2\", \"\", \"-,net_iso_enable\");\n}\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_namewithbackslash.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_namewithbackslash.txt", "chroma:document": "4.2.2 Instance and net with backslash\n&nbsp;\nInstance with backslash should be either put in single quote and with a space in the end.\n\nchange_pin('\\u_abc/u_def/state_reg[0] /RN', \"1'b0\");\n\n\nNet name with backslash should keep the backslash and space. For example\n\nDFFQ_X4M \\u_abc/u_def/state_reg[0] (.D(\\u_abc/u_def/net123 ), .Q(\\u_abc/u_def/state[0] ));\n\nThe net '\\u_abc/u_def/net123 ' should have backslash and space kept in API, for example:\n\nchange_net(\"\\u_abc/u_def/net123 \", \"INVX1\", \"\", \"-\");\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_netlistbrowseapis.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_netlistbrowseapis.txt", "chroma:document": "4.1.4 API grouping\n4.1.4.1 Netlist Browse APIs\nOne key element to do efficient manual ECO is to isolate the ECO spots quickly. The following APIs are for fast Netlist Browsing.\n\nget_cells: Get all cells in the current module or sub-modules (LLM: find/get instance)\nget_conns: Get connections of net or pin in the top level module, return the leafs and the hierarchical connections (LLM: conns)\nget_driver: Get the driver of a net or pin (LLM: driver)\nget_drivers: Get the drivers of a net or pin (LLM: drivers)\nget_instance: Get instance in the top level module\nget_instances: Get all hierarchical instances in the top level module (LLM: hierarchical instances)\nget_lib_cells: Get leaf gates in libraries \nget_loads: Get loads of net in the top level module, return the leafs connections (LLM: loads)\nget_modules: Get modules under current module (LLM: submodules)\nget_net_of: Get net name connecting to a pin (LLM: net of pin)\nget_nets: Get nets that matching pattern (LLM: matched nets)\nget_pins: Get pins of instance or module (LLM: pins)\nget_ports: Get all ports in the current top level module (LLM: ports)\nget_ref: Get the reference of the instance, return leaf cell name or hierarchical module name (LLM: design name)\n\nFor example, to get data pins of flops in one module. The script can use these browse APIs\n\nmy @flop_data_pins;\nset_top(\"module_name\");\nmy @flops = get_cells(\"-type\", \"ff\");\nforeach my $flop (@flops){\n&nbsp;&nbsp;my @dpins = get_pins(\"-data\", $flop);\n&nbsp;&nbsp;push @flop_data_pins, $dpins;\n}\n\n\nAfter run the script, @flop_data_pins have all data pins of all flops in the module.\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_runanddebuggofscript.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_runanddebuggofscript.txt", "chroma:document": "4.3 Run and debug GOF script\n4.3.1 Command line\nIn Linux Shell, the script can be run by &lsquo;-run&rsquo; option.\ngof -run run_example.pl\n4.3.2 GOF Shell\nIf '-run' option is present in the command line, and 'exit' or 'gexit' is not in the script, or GOF meets error when executing the script, GOF goes into interactive mode with GOF shell 'GOF &gt;'.\n\nGOF, Netlist Processing Script APIs, Interactive Mode\nRun 'start_gui' to launch GUI window\nRun 'help' to list API calls\nGOF &gt;\n&nbsp;\n\nIndividual command can be executed in GOF shell. The command can be in nested mode\n\nGOF &gt; set_top(get_ref(\"u_rxbuf\"))\n\n4.3.3 Run in GUI mode\nGOF scripts can be run in GUI window. In GofViewer, click Menu Commands-&gt;&rsquo;Launch GOF Script Interface&rsquo; to launch GOF GUI window.\nType &lsquo;help&rsquo; in the shell entry for help information. Scripts can be run by &lsquo;run&rsquo; command in the shell entry\n\nFigure 33: GofCall window\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_gsc_stringquotes.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.gsc_stringquotes.txt", "chroma:document": "4.2 String Handling In Script Mode\n4.2.1 Single quote and double quote\n&nbsp;\nAny string in GOF script for module/instance/wire/pin/port should be enclosed by single quote or double quote. When a Perl variable is used, double quote should be used\n\nmy $inst = \"state_reg_0\";\nchange_pin(\"inst/D\",\"1'b0\");\n\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_install.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.install.txt", "chroma:document": "1.1 Download and Install GOF\nGOF release package can be found in\nhttps://nandigits.com/download.php\nPlease complete the form to request an evaluation license before downloading the application.The tool supports Linux 64bits OS. Download the release package and unzip to a directory. Set 'the_64bit_install_path/GOF64/bin' in search path.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_intro.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.intro.txt", "chroma:document": "1 Introduction\n\nThe GOF platform is comprised of four powerful functional components: GOF ECO, GOF Formal, GOF LEC, and GOF Debug.\nGOF ECO is the flagship tool within the GOF platform, offering state-of-the-art technology and methodologies for functional netlist ECO. Whether you need to identify non-equivalent modules, fix non-equivalent points, or streamline the Implementation netlist, GOF ECO has you covered.\nGOF Formal is another critical component of the GOF platform, providing a formal method for calculating fault coverage in an IC design in functional safety.\nGOF LEC is the logic equivalence checker tool within the GOF platform, enabling users to easily verify the equivalence of their designs and ensure that they function as intended.\nGOF Debug is the netlist debug tool integrated with incremental schematic, providing a fast and efficient way to identify and resolve errors in your netlist.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: man_license.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\man.license.txt", "chroma:document": "1.2 License and Setup\nVisit https://nandigits.com/supports.php?type=license to request an evaluation license. Or email support@nandigits.com for more information. Without license, the tool can support netlist size less than 500K bytes. There are two license modes, fixed node mode and floating node mode.\n\n\tFixed node license:&nbsp;Copy the license file to &quot;the_install_path/GOF64/bin&quot; and restart GOF.\n\tFloating node license: Please refer to this page to install floating license&nbsp;https://nandigits.com/floating_license_setup_example.htm\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: use_advkeymap.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\use.advkeymap.txt", "chroma:document": "When you see many of those lines in the log, \nDONE FILE in prun1123/done.testequal\nDONE FILE in prun1123/done.testequal..0_1.1_0\n\nand ECO takes long time.\nThe feature is an advanced key point mapping method. It can be disabled by disabling it before running fix_design\nset_key_point_map_adv(0);\n\nfix_design();\n\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: use_panic.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\use.panic.txt", "chroma:document": "When run gof application, an error shows up\nPanic: Can't find bfs section in '/home/tool/gof/bin/gof'\n\nIt is caused by tool download not complete. Please visit nandigits.com/download.php and download the tool again.\n"}


created_at: 2024-03-31 01:12:01
topic: persistent://default/default/5c996fe4-933e-4044-8afb-ae26bdcce65c
id: user_metalonly.0.0
encoding: FLOAT32
metadata:
{"source": "src_en\\user.metalonly.txt", "chroma:document": "What is metal only ECO?\nMetal only ECO only changes metal layers and keeps base layers untouched.\nGOF ECO has two metal only ECO modes, one is using standard library spare cells.\nThe other is using Metal Configurable gate array cells.\n"}


