JohannesGaessler commited on
Commit
df90a14
·
1 Parent(s): ace16dc

CUDA: fix crash on large batch size for quant. MoE (llama/13537)

Browse files
ggml/src/ggml-cuda/mmq.cu CHANGED
@@ -122,6 +122,7 @@ void ggml_cuda_mul_mat_q(
122
  const int64_t s13 = src1->nb[3] / ts_src1;
123
  quantize_mmq_q8_1_cuda(src1_d, nullptr, src1_q8_1.get(), src0->type,
124
  ne10, s11, s12, s13, ne10_padded, ne11, ne12, ne13, stream);
 
125
  }
126
 
127
  const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
@@ -205,6 +206,7 @@ void ggml_cuda_mul_mat_q(
205
  const int64_t s13 = src1->nb[2] / ts_src1;
206
  quantize_mmq_q8_1_cuda(src1_d, ids_src1_dev, src1_q8_1.get(), src0->type,
207
  ne10, s11, s12, s13, ne10_padded, ne11_flat, ne12_flat, ne13_flat, stream);
 
208
  }
209
 
210
  const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
 
122
  const int64_t s13 = src1->nb[3] / ts_src1;
123
  quantize_mmq_q8_1_cuda(src1_d, nullptr, src1_q8_1.get(), src0->type,
124
  ne10, s11, s12, s13, ne10_padded, ne11, ne12, ne13, stream);
125
+ CUDA_CHECK(cudaGetLastError());
126
  }
127
 
128
  const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
 
206
  const int64_t s13 = src1->nb[2] / ts_src1;
207
  quantize_mmq_q8_1_cuda(src1_d, ids_src1_dev, src1_q8_1.get(), src0->type,
208
  ne10, s11, s12, s13, ne10_padded, ne11_flat, ne12_flat, ne13_flat, stream);
209
+ CUDA_CHECK(cudaGetLastError());
210
  }
211
 
212
  const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
ggml/src/ggml-cuda/quantize.cu CHANGED
@@ -56,13 +56,13 @@ static __global__ void quantize_mmq_q8_1(
56
  constexpr int vals_per_scale = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 64 : 32;
57
  constexpr int vals_per_sum = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 16 : 32;
58
 
59
- const int64_t i0 = ((int64_t)blockDim.x*blockIdx.x + threadIdx.x)*4;
60
 
61
  if (i0 >= ne0) {
62
  return;
63
  }
64
 
65
- const int64_t i1 = blockIdx.y;
66
  const int64_t i2 = blockIdx.z % ne2;
67
  const int64_t i3 = blockIdx.z / ne2;
68
 
@@ -75,8 +75,8 @@ static __global__ void quantize_mmq_q8_1(
75
 
76
  block_q8_1_mmq * y = (block_q8_1_mmq *) vy;
77
 
78
- const int64_t ib0 = blockIdx.z*((int64_t)gridDim.y*gridDim.x*blockDim.x/QK8_1); // first block of channel
79
- const int64_t ib = ib0 + (i0 / (4*QK8_1))*ne1 + blockIdx.y; // block index in channel
80
  const int64_t iqs = i0 % (4*QK8_1); // quant index in block
81
 
82
  // Load 4 floats per thread and calculate max. abs. value between them:
@@ -166,8 +166,9 @@ void quantize_mmq_q8_1_cuda(
166
  GGML_ASSERT(ne00 % 4 == 0);
167
  GGML_ASSERT(ne0 % (4*QK8_1) == 0);
168
 
169
- const int64_t block_num_x = (ne0 + 4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ - 1) / (4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ);
170
- const dim3 num_blocks(block_num_x, ne1, ne2*ne3);
 
171
  const dim3 block_size(CUDA_QUANTIZE_BLOCK_SIZE_MMQ, 1, 1);
172
  switch (mmq_get_q8_1_ds_layout(type_src0)) {
173
  case MMQ_Q8_1_DS_LAYOUT_D4:
 
56
  constexpr int vals_per_scale = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 64 : 32;
57
  constexpr int vals_per_sum = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 16 : 32;
58
 
59
+ const int64_t i0 = ((int64_t)blockDim.x*blockIdx.y + threadIdx.x)*4;
60
 
61
  if (i0 >= ne0) {
62
  return;
63
  }
64
 
65
+ const int64_t i1 = blockIdx.x;
66
  const int64_t i2 = blockIdx.z % ne2;
67
  const int64_t i3 = blockIdx.z / ne2;
68
 
 
75
 
76
  block_q8_1_mmq * y = (block_q8_1_mmq *) vy;
77
 
78
+ const int64_t ib0 = blockIdx.z*((int64_t)gridDim.x*gridDim.y*blockDim.x/QK8_1); // first block of channel
79
+ const int64_t ib = ib0 + (i0 / (4*QK8_1))*ne1 + blockIdx.x; // block index in channel
80
  const int64_t iqs = i0 % (4*QK8_1); // quant index in block
81
 
82
  // Load 4 floats per thread and calculate max. abs. value between them:
 
166
  GGML_ASSERT(ne00 % 4 == 0);
167
  GGML_ASSERT(ne0 % (4*QK8_1) == 0);
168
 
169
+ // ne1 tends to assume the highest values, therefore use it as the "x" dimension of the CUDA grid:
170
+ const int64_t block_num_y = (ne0 + 4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ - 1) / (4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ);
171
+ const dim3 num_blocks(ne1, block_num_y, ne2*ne3);
172
  const dim3 block_size(CUDA_QUANTIZE_BLOCK_SIZE_MMQ, 1, 1);
173
  switch (mmq_get_q8_1_ds_layout(type_src0)) {
174
  case MMQ_Q8_1_DS_LAYOUT_D4: