static void s390_init(QEMUMachineInitArgs *args) { ram_addr_t my_ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; const char *initrd_filename = args->initrd_filename; CPUS390XState *env = NULL; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); ram_addr_t kernel_size = 0; ram_addr_t initrd_offset; ram_addr_t initrd_size = 0; int shift = 0; uint8_t *storage_keys; void *virtio_region; hwaddr virtio_region_len; hwaddr virtio_region_start; int i; /* s390x ram size detection needs a 16bit multiplier + an increment. So guests > 64GB can be specified in 2MB steps etc. */ while ((my_ram_size >> (20 + shift)) > 65535) { shift++; } my_ram_size = my_ram_size >> (20 + shift) << (20 + shift); /* lets propagate the changed ram size into the global variable. */ ram_size = my_ram_size; /* get a BUS */ s390_bus = s390_virtio_bus_init(&my_ram_size); s390_sclp_init(); /* allocate RAM */ memory_region_init_ram(ram, "s390.ram", my_ram_size); vmstate_register_ram_global(ram); memory_region_add_subregion(sysmem, 0, ram); /* clear virtio region */ virtio_region_len = my_ram_size - ram_size; virtio_region_start = ram_size; virtio_region = cpu_physical_memory_map(virtio_region_start, &virtio_region_len, true); memset(virtio_region, 0, virtio_region_len); cpu_physical_memory_unmap(virtio_region, virtio_region_len, 1, virtio_region_len); /* allocate storage keys */ storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE); /* init CPUs */ if (cpu_model == NULL) { cpu_model = "host"; } ipi_states = g_malloc(sizeof(S390CPU *) * smp_cpus); for (i = 0; i < smp_cpus; i++) { S390CPU *cpu; CPUS390XState *tmp_env; cpu = cpu_s390x_init(cpu_model); tmp_env = &cpu->env; if (!env) { env = tmp_env; } ipi_states[i] = cpu; tmp_env->halted = 1; tmp_env->exception_index = EXCP_HLT; tmp_env->storage_keys = storage_keys; } /* One CPU has to run */ s390_add_running_cpu(env); if (kernel_filename) { kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); if (kernel_size == -1UL) { kernel_size = load_image_targphys(kernel_filename, 0, ram_size); } if (kernel_size == -1UL) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* * we can not rely on the ELF entry point, since up to 3.2 this * value was 0x800 (the SALIPL loader) and it wont work. For * all (Linux) cases 0x10000 (KERN_IMAGE_START) should be fine. */ env->psw.addr = KERN_IMAGE_START; env->psw.mask = 0x0000000180000000ULL; } else { ram_addr_t bios_size = 0; char *bios_filename; /* Load zipl bootloader */ if (bios_name == NULL) { bios_name = ZIPL_FILENAME; } bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); bios_size = load_image_targphys(bios_filename, ZIPL_LOAD_ADDR, 4096); g_free(bios_filename); if ((long)bios_size < 0) { hw_error("could not load bootloader '%s'\n", bios_name); } if (bios_size > 4096) { hw_error("stage1 bootloader is > 4k\n"); } env->psw.addr = ZIPL_START; env->psw.mask = 0x0000000180000000ULL; } if (initrd_filename) { initrd_offset = INITRD_START; while (kernel_size + 0x100000 > initrd_offset) { initrd_offset += 0x100000; } initrd_size = load_image_targphys(initrd_filename, initrd_offset, ram_size - initrd_offset); if (initrd_size == -1UL) { fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); exit(1); } /* we have to overwrite values in the kernel image, which are "rom" */ stq_p(rom_ptr(INITRD_PARM_START), initrd_offset); stq_p(rom_ptr(INITRD_PARM_SIZE), initrd_size); } if (rom_ptr(KERN_PARM_AREA)) { /* we have to overwrite values in the kernel image, which are "rom" */ memcpy(rom_ptr(KERN_PARM_AREA), kernel_cmdline, strlen(kernel_cmdline) + 1); } /* Create VirtIO network adapters */ for(i = 0; i < nb_nics; i++) { NICInfo *nd = &nd_table[i]; DeviceState *dev; if (!nd->model) { nd->model = g_strdup("virtio"); } if (strcmp(nd->model, "virtio")) { fprintf(stderr, "S390 only supports VirtIO nics\n"); exit(1); } dev = qdev_create((BusState *)s390_bus, "virtio-net-s390"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); } /* Create VirtIO disk drives */ for(i = 0; i < MAX_BLK_DEVS; i++) { DriveInfo *dinfo; DeviceState *dev; dinfo = drive_get(IF_IDE, 0, i); if (!dinfo) { continue; } dev = qdev_create((BusState *)s390_bus, "virtio-blk-s390"); qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); qdev_init_nofail(dev); } }


void sparc64_set_context(CPUSPARCState *env) { abi_ulong ucp_addr; struct target_ucontext *ucp; target_mc_gregset_t *grp; abi_ulong pc, npc, tstate; abi_ulong fp, i7, w_addr; int err; unsigned int i; ucp_addr = env->regwptr[UREG_I0]; if (!lock_user_struct(VERIFY_READ, ucp, ucp_addr, 1)) goto do_sigsegv; grp = &ucp->tuc_mcontext.mc_gregs; err = __get_user(pc, &((*grp)[MC_PC])); err |= __get_user(npc, &((*grp)[MC_NPC])); if (err || ((pc | npc) & 3)) goto do_sigsegv; if (env->regwptr[UREG_I1]) { target_sigset_t target_set; sigset_t set; if (TARGET_NSIG_WORDS == 1) { if (__get_user(target_set.sig[0], &ucp->tuc_sigmask.sig[0])) goto do_sigsegv; } else { abi_ulong *src, *dst; src = ucp->tuc_sigmask.sig; dst = target_set.sig; for (i = 0; i < TARGET_NSIG_WORDS; i++, dst++, src++) { err |= __get_user(*dst, src); } if (err) goto do_sigsegv; } target_to_host_sigset_internal(&set, &target_set); sigprocmask(SIG_SETMASK, &set, NULL); } env->pc = pc; env->npc = npc; err |= __get_user(env->y, &((*grp)[MC_Y])); err |= __get_user(tstate, &((*grp)[MC_TSTATE])); env->asi = (tstate >> 24) & 0xff; cpu_put_ccr(env, tstate >> 32); cpu_put_cwp64(env, tstate & 0x1f); err |= __get_user(env->gregs[1], (&(*grp)[MC_G1])); err |= __get_user(env->gregs[2], (&(*grp)[MC_G2])); err |= __get_user(env->gregs[3], (&(*grp)[MC_G3])); err |= __get_user(env->gregs[4], (&(*grp)[MC_G4])); err |= __get_user(env->gregs[5], (&(*grp)[MC_G5])); err |= __get_user(env->gregs[6], (&(*grp)[MC_G6])); err |= __get_user(env->gregs[7], (&(*grp)[MC_G7])); err |= __get_user(env->regwptr[UREG_I0], (&(*grp)[MC_O0])); err |= __get_user(env->regwptr[UREG_I1], (&(*grp)[MC_O1])); err |= __get_user(env->regwptr[UREG_I2], (&(*grp)[MC_O2])); err |= __get_user(env->regwptr[UREG_I3], (&(*grp)[MC_O3])); err |= __get_user(env->regwptr[UREG_I4], (&(*grp)[MC_O4])); err |= __get_user(env->regwptr[UREG_I5], (&(*grp)[MC_O5])); err |= __get_user(env->regwptr[UREG_I6], (&(*grp)[MC_O6])); err |= __get_user(env->regwptr[UREG_I7], (&(*grp)[MC_O7])); err |= __get_user(fp, &(ucp->tuc_mcontext.mc_fp)); err |= __get_user(i7, &(ucp->tuc_mcontext.mc_i7)); w_addr = TARGET_STACK_BIAS+env->regwptr[UREG_I6]; if (put_user(fp, w_addr + offsetof(struct target_reg_window, ins[6]), abi_ulong) != 0) goto do_sigsegv; if (put_user(i7, w_addr + offsetof(struct target_reg_window, ins[7]), abi_ulong) != 0) goto do_sigsegv; /* FIXME this does not match how the kernel handles the FPU in * its sparc64_set_context implementation. In particular the FPU * is only restored if fenab is non-zero in: * __get_user(fenab, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_enab)); */ err |= __get_user(env->fprs, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fprs)); { uint32_t *src = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs; for (i = 0; i < 64; i++, src++) { if (i & 1) { err |= __get_user(env->fpr[i/2].l.lower, src); } else { err |= __get_user(env->fpr[i/2].l.upper, src); } } } err |= __get_user(env->fsr, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fsr)); err |= __get_user(env->gsr, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_gsr)); if (err) goto do_sigsegv; unlock_user_struct(ucp, ucp_addr, 0); return; do_sigsegv: unlock_user_struct(ucp, ucp_addr, 0); force_sig(TARGET_SIGSEGV); }


uint32_t cpu_mips_get_count (CPUState *env) { if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; } else { return env->CP0_Count + (uint32_t)muldiv64(qemu_get_clock(vm_clock), TIMER_FREQ, get_ticks_per_sec()); } }


static int cpu_has_work(CPUState *env) { if (env->stop) return 1; if (env->stopped) return 0; if (!env->halted) return 1; if (qemu_cpu_has_work(env)) return 1; return 0; }


static void outport_write(KBDState *s, uint32_t val) { DPRINTF("kbd: write outport=0x%02x\n", val); s->outport = val; if (s->a20_out) { qemu_set_irq(*s->a20_out, (val >> 1) & 1); } if (!(val & 1)) { qemu_system_reset_request(); } }


static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in, hwaddr dsm_mem_addr) { NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm); NvdimmFuncGetLabelDataIn *get_label_data; NvdimmFuncGetLabelDataOut *get_label_data_out; uint32_t status; int size; get_label_data = (NvdimmFuncGetLabelDataIn *)in->arg3; le32_to_cpus(&get_label_data->offset); le32_to_cpus(&get_label_data->length); nvdimm_debug("Read Label Data: offset %#x length %#x.\n", get_label_data->offset, get_label_data->length); status = nvdimm_rw_label_data_check(nvdimm, get_label_data->offset, get_label_data->length); if (status != 0 /* Success */) { nvdimm_dsm_no_payload(status, dsm_mem_addr); return; } size = sizeof(*get_label_data_out) + get_label_data->length; assert(size <= 4096); get_label_data_out = g_malloc(size); get_label_data_out->len = cpu_to_le32(size); get_label_data_out->func_ret_status = cpu_to_le32(0 /* Success */); nvc->read_label_data(nvdimm, get_label_data_out->out_buf, get_label_data->length, get_label_data->offset); cpu_physical_memory_write(dsm_mem_addr, get_label_data_out, size); g_free(get_label_data_out); }


static QObject *visitor_get(TestOutputVisitorData *data) { visit_complete(data->ov, &data->obj); g_assert(data->obj); return data->obj; }


static void fill_elf_header(struct elfhdr *elf, int segs, uint16_t machine, uint32_t flags) { (void) memset(elf, 0, sizeof(*elf)); (void) memcpy(elf->e_ident, ELFMAG, SELFMAG); elf->e_ident[EI_CLASS] = ELF_CLASS; elf->e_ident[EI_DATA] = ELF_DATA; elf->e_ident[EI_VERSION] = EV_CURRENT; elf->e_ident[EI_OSABI] = ELF_OSABI; elf->e_type = ET_CORE; elf->e_machine = machine; elf->e_version = EV_CURRENT; elf->e_phoff = sizeof(struct elfhdr); elf->e_flags = flags; elf->e_ehsize = sizeof(struct elfhdr); elf->e_phentsize = sizeof(struct elf_phdr); elf->e_phnum = segs; #ifdef BSWAP_NEEDED bswap_ehdr(elf); #endif }


static int vm_can_run(void) { if (powerdown_requested) return 0; if (reset_requested) return 0; if (shutdown_requested) return 0; if (debug_requested) return 0; return 1; }


void vga_common_init(VGACommonState *s, int vga_ram_size) { int i, j, v, b; for(i = 0;i < 256; i++) { v = 0; for(j = 0; j < 8; j++) { v |= ((i >> j) & 1) << (j * 4); } expand4[i] = v; v = 0; for(j = 0; j < 4; j++) { v |= ((i >> (2 * j)) & 3) << (j * 4); } expand2[i] = v; } for(i = 0; i < 16; i++) { v = 0; for(j = 0; j < 4; j++) { b = ((i >> j) & 1); v |= b << (2 * j); v |= b << (2 * j + 1); } expand4to8[i] = v; } #ifdef CONFIG_BOCHS_VBE s->is_vbe_vmstate = 1; #else s->is_vbe_vmstate = 0; #endif s->vram_offset = qemu_ram_alloc(vga_ram_size); s->vram_ptr = qemu_get_ram_ptr(s->vram_offset); s->vram_size = vga_ram_size; s->get_bpp = vga_get_bpp; s->get_offsets = vga_get_offsets; s->get_resolution = vga_get_resolution; s->update = vga_update_display; s->invalidate = vga_invalidate_display; s->screen_dump = vga_screen_dump; s->text_update = vga_update_text; switch (vga_retrace_method) { case VGA_RETRACE_DUMB: s->retrace = vga_dumb_retrace; s->update_retrace_info = vga_dumb_update_retrace_info; break; case VGA_RETRACE_PRECISE: s->retrace = vga_precise_retrace; s->update_retrace_info = vga_precise_update_retrace_info; break; } vga_reset(s); }


InputEvent *qemu_input_event_new_btn(InputButton btn, bool down) { InputEvent *evt = g_new0(InputEvent, 1); evt->btn = g_new0(InputBtnEvent, 1); evt->kind = INPUT_EVENT_KIND_BTN; evt->btn->button = btn; evt->btn->down = down; return evt; }


static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { ECCState *s = opaque; trace_ecc_diag_mem_writeb(addr, val); s->diag[addr & ECC_DIAG_MASK] = val; }


static void imx_fec_do_tx(IMXFECState *s) { int frame_size = 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr = frame; uint32_t addr = s->tx_descriptor; while (1) { IMXFECBufDesc bd; int len; imx_fec_read_bd(&bd, addr); FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n", addr, bd.flags, bd.length, bd.data); if ((bd.flags & ENET_BD_R) == 0) { /* Run out of descriptors to transmit. */ FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); break; } len = bd.length; if (frame_size + len > ENET_MAX_FRAME_SIZE) { len = ENET_MAX_FRAME_SIZE - frame_size; s->regs[ENET_EIR] |= ENET_INT_BABT; } dma_memory_read(&address_space_memory, bd.data, ptr, len); ptr += len; frame_size += len; if (bd.flags & ENET_BD_L) { /* Last buffer in frame. */ qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size); ptr = frame; frame_size = 0; s->regs[ENET_EIR] |= ENET_INT_TXF; } s->regs[ENET_EIR] |= ENET_INT_TXB; bd.flags &= ~ENET_BD_R; /* Write back the modified descriptor. */ imx_fec_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { addr = s->regs[ENET_TDSR]; } else { addr += sizeof(bd); } } s->tx_descriptor = addr; imx_eth_update(s); }


static void omap_eac_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { struct omap_eac_s *s = (struct omap_eac_s *) opaque; if (size != 2) { return omap_badwidth_write16(opaque, addr, value); } switch (addr) { case 0x098: /* APD1LCR */ case 0x09c: /* APD1RCR */ case 0x0a0: /* APD2LCR */ case 0x0a4: /* APD2RCR */ case 0x0a8: /* APD3LCR */ case 0x0ac: /* APD3RCR */ case 0x0b0: /* APD4R */ case 0x0b8: /* ADRDR */ case 0x0d0: /* MPDDMARR */ case 0x0d8: /* MPUDMARR */ case 0x0e4: /* BPDDMARR */ case 0x0ec: /* BPUDMARR */ case 0x100: /* VERSION_NUMBER */ case 0x108: /* SYSSTATUS */ OMAP_RO_REG(addr); return; case 0x000: /* CPCFR1 */ s->config[0] = value & 0xff; omap_eac_format_update(s); break; case 0x004: /* CPCFR2 */ s->config[1] = value & 0xff; omap_eac_format_update(s); break; case 0x008: /* CPCFR3 */ s->config[2] = value & 0xff; omap_eac_format_update(s); break; case 0x00c: /* CPCFR4 */ s->config[3] = value & 0xff; omap_eac_format_update(s); break; case 0x010: /* CPTCTL */ /* Assuming TXF and TXE bits are read-only... */ s->control = value & 0x5f; omap_eac_interrupt_update(s); break; case 0x014: /* CPTTADR */ s->address = value & 0xff; break; case 0x018: /* CPTDATL */ s->data &= 0xff00; s->data |= value & 0xff; break; case 0x01c: /* CPTDATH */ s->data &= 0x00ff; s->data |= value << 8; break; case 0x020: /* CPTVSLL */ s->vtol = value & 0xf8; break; case 0x024: /* CPTVSLH */ s->vtsl = value & 0x9f; break; case 0x040: /* MPCTR */ s->modem.control = value & 0x8f; break; case 0x044: /* MPMCCFR */ s->modem.config = value & 0x7fff; break; case 0x060: /* BPCTR */ s->bt.control = value & 0x8f; break; case 0x064: /* BPMCCFR */ s->bt.config = value & 0x7fff; break; case 0x080: /* AMSCFR */ s->mixer = value & 0x0fff; break; case 0x084: /* AMVCTR */ s->gain[0] = value & 0xffff; break; case 0x088: /* AM1VCTR */ s->gain[1] = value & 0xff7f; break; case 0x08c: /* AM2VCTR */ s->gain[2] = value & 0xff7f; break; case 0x090: /* AM3VCTR */ s->gain[3] = value & 0xff7f; break; case 0x094: /* ASTCTR */ s->att = value & 0xff; break; case 0x0b4: /* ADWR */ s->codec.txbuf[s->codec.txlen ++] = value; if (unlikely(s->codec.txlen == EAC_BUF_LEN || s->codec.txlen == s->codec.txavail)) { if (s->codec.txavail) omap_eac_out_empty(s); /* Discard what couldn't be written */ s->codec.txlen = 0; } break; case 0x0bc: /* AGCFR */ s->codec.config[0] = value & 0x07ff; omap_eac_format_update(s); break; case 0x0c0: /* AGCTR */ s->codec.config[1] = value & 0x780f; omap_eac_format_update(s); break; case 0x0c4: /* AGCFR2 */ s->codec.config[2] = value & 0x003f; omap_eac_format_update(s); break; case 0x0c8: /* AGCFR3 */ s->codec.config[3] = value & 0xffff; omap_eac_format_update(s); break; case 0x0cc: /* MBPDMACTR */ case 0x0d4: /* MPDDMAWR */ case 0x0e0: /* MPUDMAWR */ case 0x0e8: /* BPDDMAWR */ case 0x0f0: /* BPUDMAWR */ break; case 0x104: /* SYSCONFIG */ if (value & (1 << 1)) /* SOFTRESET */ omap_eac_reset(s); s->sysconfig = value & 0x31d; break; default: OMAP_BAD_REG(addr); return; } }


static void do_hybrid_window(int order, int n, int non_rec, const float *in, float *out, float *hist, float *out2, const float *window) { int i; float buffer1[order + 1]; float buffer2[order + 1]; float work[order + n + non_rec]; /* update history */ memmove(hist, hist + n, (order + non_rec)*sizeof(*hist)); for (i=0; i < n; i++) hist[order + non_rec + i] = in[n-i-1]; colmult(work, window, hist, order + n + non_rec); convolve(buffer1, work + order , n , order); convolve(buffer2, work + order + n, non_rec, order); for (i=0; i <= order; i++) { out2[i] = out2[i] * 0.5625 + buffer1[i]; out [i] = out2[i] + buffer2[i]; } /* Multiply by the white noise correcting factor (WNCF) */ *out *= 257./256.; }


static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) { int64_t rt = qemu_get_clock(rt_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_rdcr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_hz = rt; }


void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr) { address_space_stl(env->address_space_er, addr, data, (MemTxAttrs){0}, NULL); }


static void qemu_input_event_trace(QemuConsole *src, InputEvent *evt) { const char *name; int qcode, idx = -1; if (src) { idx = qemu_console_get_index(src); } switch (evt->kind) { case INPUT_EVENT_KIND_KEY: switch (evt->key->key->kind) { case KEY_VALUE_KIND_NUMBER: qcode = qemu_input_key_number_to_qcode(evt->key->key->number); name = QKeyCode_lookup[qcode]; trace_input_event_key_number(idx, evt->key->key->number, name, evt->key->down); break; case KEY_VALUE_KIND_QCODE: name = QKeyCode_lookup[evt->key->key->qcode]; trace_input_event_key_qcode(idx, name, evt->key->down); break; case KEY_VALUE_KIND_MAX: /* keep gcc happy */ break; } break; case INPUT_EVENT_KIND_BTN: name = InputButton_lookup[evt->btn->button]; trace_input_event_btn(idx, name, evt->btn->down); break; case INPUT_EVENT_KIND_REL: name = InputAxis_lookup[evt->rel->axis]; trace_input_event_rel(idx, name, evt->rel->value); break; case INPUT_EVENT_KIND_ABS: name = InputAxis_lookup[evt->abs->axis]; trace_input_event_abs(idx, name, evt->abs->value); break; case INPUT_EVENT_KIND_MAX: /* keep gcc happy */ break; } }


void ff_aac_encode_tns_info(AACEncContext *s, SingleChannelElement *sce) { int i, w, filt, coef_len, coef_compress; const int coef_res = MAX_LPC_PRECISION == 4 ? 1 : 0; const int is8 = sce->ics.window_sequence[0] == EIGHT_SHORT_SEQUENCE; put_bits(&s->pb, 1, !!sce->tns.present); if (!sce->tns.present) return; for (i = 0; i < sce->ics.num_windows; i++) { put_bits(&s->pb, 2 - is8, sce->tns.n_filt[i]); if (sce->tns.n_filt[i]) { put_bits(&s->pb, 1, !!coef_res); for (filt = 0; filt < sce->tns.n_filt[i]; filt++) { put_bits(&s->pb, 6 - 2 * is8, sce->tns.length[i][filt]); put_bits(&s->pb, 5 - 2 * is8, sce->tns.order[i][filt]); if (sce->tns.order[i][filt]) { coef_compress = compress_coef(sce->tns.coef_idx[i][filt], sce->tns.order[i][filt]); put_bits(&s->pb, 1, !!sce->tns.direction[i][filt]); put_bits(&s->pb, 1, !!coef_compress); coef_len = coef_res + 3 - coef_compress; for (w = 0; w < sce->tns.order[i][filt]; w++) put_bits(&s->pb, coef_len, sce->tns.coef_idx[i][filt][w]); } } } } }


AVFilterBufferRef *avfilter_null_get_audio_buffer(AVFilterLink *link, int perms, enum AVSampleFormat sample_fmt, int size, int64_t channel_layout, int packed) { return avfilter_get_audio_buffer(link->dst->outputs[0], perms, sample_fmt, size, channel_layout, packed); }


static void tcp_chr_read(void *opaque) { CharDriverState *chr = opaque; TCPCharDriver *s = chr->opaque; uint8_t buf[1024]; int len, size; if (!s->connected || s->max_size <= 0) return; len = sizeof(buf); if (len > s->max_size) len = s->max_size; size = tcp_chr_recv(chr, (void *)buf, len); if (size == 0) { /* connection closed */ s->connected = 0; if (s->listen_fd >= 0) { qemu_set_fd_handler(s->listen_fd, tcp_chr_accept, NULL, chr); } qemu_set_fd_handler(s->fd, NULL, NULL, NULL); closesocket(s->fd); s->fd = -1; qemu_chr_event(chr, CHR_EVENT_CLOSED); } else if (size > 0) { if (s->do_telnetopt) tcp_chr_process_IAC_bytes(chr, s, buf, &size); if (size > 0) qemu_chr_read(chr, buf, size); if (s->msgfd != -1) { close(s->msgfd); s->msgfd = -1; } } }


uint64_t helper_fctid(CPUPPCState *env, uint64_t arg) { CPU_DoubleU farg; farg.ll = arg; if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN conversion */ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); } else if (unlikely(float64_is_quiet_nan(farg.d) || float64_is_infinity(farg.d))) { /* qNan / infinity conversion */ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI); } else { farg.ll = float64_to_int64(farg.d, &env->fp_status); } return farg.ll; }


static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size) { CPUAlphaState *env = cpu_single_env; TyphoonState *s = opaque; uint64_t ret = 0; if (addr & 4) { return s->latch_tmp; } switch (addr) { case 0x0000: /* CSC: Cchip System Configuration Register. */ /* All sorts of data here; probably the only thing relevant is PIP<14> Pchip 1 Present = 0. */ break; case 0x0040: /* MTR: Memory Timing Register. */ /* All sorts of stuff related to real DRAM. */ break; case 0x0080: /* MISC: Miscellaneous Register. */ ret = s->cchip.misc | (env->cpu_index & 3); break; case 0x00c0: /* MPD: Memory Presence Detect Register. */ break; case 0x0100: /* AAR0 */ case 0x0140: /* AAR1 */ case 0x0180: /* AAR2 */ case 0x01c0: /* AAR3 */ /* AAR: Array Address Register. */ /* All sorts of information about DRAM. */ break; case 0x0200: /* DIM0: Device Interrupt Mask Register, CPU0. */ ret = s->cchip.dim[0]; break; case 0x0240: /* DIM1: Device Interrupt Mask Register, CPU1. */ ret = s->cchip.dim[1]; break; case 0x0280: /* DIR0: Device Interrupt Request Register, CPU0. */ ret = s->cchip.dim[0] & s->cchip.drir; break; case 0x02c0: /* DIR1: Device Interrupt Request Register, CPU1. */ ret = s->cchip.dim[1] & s->cchip.drir; break; case 0x0300: /* DRIR: Device Raw Interrupt Request Register. */ ret = s->cchip.drir; break; case 0x0340: /* PRBEN: Probe Enable Register. */ break; case 0x0380: /* IIC0: Interval Ignore Count Register, CPU0. */ ret = s->cchip.iic[0]; break; case 0x03c0: /* IIC1: Interval Ignore Count Register, CPU1. */ ret = s->cchip.iic[1]; break; case 0x0400: /* MPR0 */ case 0x0440: /* MPR1 */ case 0x0480: /* MPR2 */ case 0x04c0: /* MPR3 */ /* MPR: Memory Programming Register. */ break; case 0x0580: /* TTR: TIGbus Timing Register. */ /* All sorts of stuff related to interrupt delivery timings. */ break; case 0x05c0: /* TDR: TIGbug Device Timing Register. */ break; case 0x0600: /* DIM2: Device Interrupt Mask Register, CPU2. */ ret = s->cchip.dim[2]; break; case 0x0640: /* DIM3: Device Interrupt Mask Register, CPU3. */ ret = s->cchip.dim[3]; break; case 0x0680: /* DIR2: Device Interrupt Request Register, CPU2. */ ret = s->cchip.dim[2] & s->cchip.drir; break; case 0x06c0: /* DIR3: Device Interrupt Request Register, CPU3. */ ret = s->cchip.dim[3] & s->cchip.drir; break; case 0x0700: /* IIC2: Interval Ignore Count Register, CPU2. */ ret = s->cchip.iic[2]; break; case 0x0740: /* IIC3: Interval Ignore Count Register, CPU3. */ ret = s->cchip.iic[3]; break; case 0x0780: /* PWR: Power Management Control. */ break; case 0x0c00: /* CMONCTLA */ case 0x0c40: /* CMONCTLB */ case 0x0c80: /* CMONCNT01 */ case 0x0cc0: /* CMONCNT23 */ break; default: cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); return -1; } s->latch_tmp = ret >> 32; return ret; }


void qemu_system_reset(ShutdownCause reason) { MachineClass *mc; mc = current_machine ? MACHINE_GET_CLASS(current_machine) : NULL; cpu_synchronize_all_states(); if (mc && mc->reset) { mc->reset(); } else { qemu_devices_reset(); } if (reason) { /* TODO update event based on reason */ qapi_event_send_reset(&error_abort); } cpu_synchronize_all_post_reset(); }


static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf) { const char *p; int ch, reg_size, type; char buf[MAX_PACKET_LENGTH]; uint8_t mem_buf[MAX_PACKET_LENGTH]; uint8_t *registers; target_ulong addr, len; #ifdef DEBUG_GDB printf("command='%s'\n", line_buf); #endif p = line_buf; ch = *p++; switch(ch) { case '?': /* TODO: Make this return the correct value for user-mode. */ snprintf(buf, sizeof(buf), "S%02x", SIGTRAP); put_packet(s, buf); /* Remove all the breakpoints when this query is issued, * because gdb is doing and initial connect and the state * should be cleaned up. */ cpu_breakpoint_remove_all(env); cpu_watchpoint_remove_all(env); break; case 'c': if (*p != '\0') { addr = strtoull(p, (char **)&p, 16); #if defined(TARGET_I386) env->eip = addr; #elif defined (TARGET_PPC) env->nip = addr; #elif defined (TARGET_SPARC) env->pc = addr; env->npc = addr + 4; #elif defined (TARGET_ARM) env->regs[15] = addr; #elif defined (TARGET_SH4) env->pc = addr; #elif defined (TARGET_MIPS) env->active_tc.PC = addr; #elif defined (TARGET_CRIS) env->pc = addr; #endif } gdb_continue(s); return RS_IDLE; case 'C': s->signal = strtoul(p, (char **)&p, 16); gdb_continue(s); return RS_IDLE; case 'k': /* Kill the target */ fprintf(stderr, "\nQEMU: Terminated via GDBstub\n"); exit(0); case 'D': /* Detach packet */ cpu_breakpoint_remove_all(env); cpu_watchpoint_remove_all(env); gdb_continue(s); put_packet(s, "OK"); break; case 's': if (*p != '\0') { addr = strtoull(p, (char **)&p, 16); #if defined(TARGET_I386) env->eip = addr; #elif defined (TARGET_PPC) env->nip = addr; #elif defined (TARGET_SPARC) env->pc = addr; env->npc = addr + 4; #elif defined (TARGET_ARM) env->regs[15] = addr; #elif defined (TARGET_SH4) env->pc = addr; #elif defined (TARGET_MIPS) env->active_tc.PC = addr; #elif defined (TARGET_CRIS) env->pc = addr; #endif } cpu_single_step(env, sstep_flags); gdb_continue(s); return RS_IDLE; case 'F': { target_ulong ret; target_ulong err; ret = strtoull(p, (char **)&p, 16); if (*p == ',') { p++; err = strtoull(p, (char **)&p, 16); } else { err = 0; } if (*p == ',') p++; type = *p; if (gdb_current_syscall_cb) gdb_current_syscall_cb(s->env, ret, err); if (type == 'C') { put_packet(s, "T02"); } else { gdb_continue(s); } } break; case 'g': len = 0; for (addr = 0; addr < num_g_regs; addr++) { reg_size = gdb_read_register(env, mem_buf + len, addr); len += reg_size; } memtohex(buf, mem_buf, len); put_packet(s, buf); break; case 'G': registers = mem_buf; len = strlen(p) / 2; hextomem((uint8_t *)registers, p, len); for (addr = 0; addr < num_g_regs && len > 0; addr++) { reg_size = gdb_write_register(env, registers, addr); len -= reg_size; registers += reg_size; } put_packet(s, "OK"); break; case 'm': addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, NULL, 16); if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) { put_packet (s, "E14"); } else { memtohex(buf, mem_buf, len); put_packet(s, buf); } break; case 'M': addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, (char **)&p, 16); if (*p == ':') p++; hextomem(mem_buf, p, len); if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0) put_packet(s, "E14"); else put_packet(s, "OK"); break; case 'p': /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable. This works, but can be very slow. Anything new enough to understand XML also knows how to use this properly. */ if (!gdb_has_xml) goto unknown_command; addr = strtoull(p, (char **)&p, 16); reg_size = gdb_read_register(env, mem_buf, addr); if (reg_size) { memtohex(buf, mem_buf, reg_size); put_packet(s, buf); } else { put_packet(s, "E14"); } break; case 'P': if (!gdb_has_xml) goto unknown_command; addr = strtoull(p, (char **)&p, 16); if (*p == '=') p++; reg_size = strlen(p) / 2; hextomem(mem_buf, p, reg_size); gdb_write_register(env, mem_buf, addr); put_packet(s, "OK"); break; case 'Z': type = strtoul(p, (char **)&p, 16); if (*p == ',') p++; addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, (char **)&p, 16); switch (type) { case 0: case 1: if (cpu_breakpoint_insert(env, addr) < 0) goto breakpoint_error; put_packet(s, "OK"); break; #ifndef CONFIG_USER_ONLY case 2: type = PAGE_WRITE; goto insert_watchpoint; case 3: type = PAGE_READ; goto insert_watchpoint; case 4: type = PAGE_READ | PAGE_WRITE; insert_watchpoint: if (cpu_watchpoint_insert(env, addr, type) < 0) goto breakpoint_error; put_packet(s, "OK"); break; #endif default: put_packet(s, ""); break; } break; breakpoint_error: put_packet(s, "E22"); break; case 'z': type = strtoul(p, (char **)&p, 16); if (*p == ',') p++; addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, (char **)&p, 16); if (type == 0 || type == 1) { cpu_breakpoint_remove(env, addr); put_packet(s, "OK"); #ifndef CONFIG_USER_ONLY } else if (type >= 2 || type <= 4) { cpu_watchpoint_remove(env, addr); put_packet(s, "OK"); #endif } else { put_packet(s, ""); } break; case 'q': case 'Q': /* parse any 'q' packets here */ if (!strcmp(p,"qemu.sstepbits")) { /* Query Breakpoint bit definitions */ snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", SSTEP_ENABLE, SSTEP_NOIRQ, SSTEP_NOTIMER); put_packet(s, buf); break; } else if (strncmp(p,"qemu.sstep",10) == 0) { /* Display or change the sstep_flags */ p += 10; if (*p != '=') { /* Display current setting */ snprintf(buf, sizeof(buf), "0x%x", sstep_flags); put_packet(s, buf); break; } p++; type = strtoul(p, (char **)&p, 16); sstep_flags = type; put_packet(s, "OK"); break; } #ifdef CONFIG_LINUX_USER else if (strncmp(p, "Offsets", 7) == 0) { TaskState *ts = env->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx ";Bss=" TARGET_ABI_FMT_lx, ts->info->code_offset, ts->info->data_offset, ts->info->data_offset); put_packet(s, buf); break; } #endif if (strncmp(p, "Supported", 9) == 0) { sprintf(buf, "PacketSize=%x", MAX_PACKET_LENGTH); #ifdef GDB_CORE_XML strcat(buf, ";qXfer:features:read+"); #endif put_packet(s, buf); break; } #ifdef GDB_CORE_XML if (strncmp(p, "Xfer:features:read:", 19) == 0) { const char *xml; target_ulong total_len; gdb_has_xml = 1; p += 19; xml = get_feature_xml(env, p, &p); if (!xml) { sprintf(buf, "E00"); put_packet(s, buf); break; } if (*p == ':') p++; addr = strtoul(p, (char **)&p, 16); if (*p == ',') p++; len = strtoul(p, (char **)&p, 16); total_len = strlen(xml); if (addr > total_len) { sprintf(buf, "E00"); put_packet(s, buf); break; } if (len > (MAX_PACKET_LENGTH - 5) / 2) len = (MAX_PACKET_LENGTH - 5) / 2; if (len < total_len - addr) { buf[0] = 'm'; len = memtox(buf + 1, xml + addr, len); } else { buf[0] = 'l'; len = memtox(buf + 1, xml + addr, total_len - addr); } put_packet_binary(s, buf, len + 1); break; } #endif /* Unrecognised 'q' command. */ goto unknown_command; default: unknown_command: /* put empty packet */ buf[0] = '\0'; put_packet(s, buf); break; } return RS_IDLE; }


av_cold void ff_volume_init_x86(VolumeContext *vol) { int cpu_flags = av_get_cpu_flags(); enum AVSampleFormat sample_fmt = av_get_packed_sample_fmt(vol->sample_fmt); if (sample_fmt == AV_SAMPLE_FMT_S16) { if (EXTERNAL_SSE2(cpu_flags) && vol->volume_i < 32768) { vol->scale_samples = ff_scale_samples_s16_sse2; vol->samples_align = 8; } } else if (sample_fmt == AV_SAMPLE_FMT_S32) { if (EXTERNAL_SSE2(cpu_flags)) { vol->scale_samples = ff_scale_samples_s32_sse2; vol->samples_align = 4; } if (EXTERNAL_SSSE3(cpu_flags) && cpu_flags & AV_CPU_FLAG_ATOM) { vol->scale_samples = ff_scale_samples_s32_ssse3_atom; vol->samples_align = 4; } if (EXTERNAL_AVX(cpu_flags)) { vol->scale_samples = ff_scale_samples_s32_avx; vol->samples_align = 8; } } }


static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp) { PCIBus *bus = dev->bus; int pxb_bus_num = pci_bus_num(pxb_bus); if (bus->parent_dev) { error_setg(errp, "PXB devices can be attached only to root bus"); return; } QLIST_FOREACH(bus, &bus->child, sibling) { if (pci_bus_num(bus) == pxb_bus_num) { error_setg(errp, "Bus %d is already in use", pxb_bus_num); return; } } QLIST_INSERT_HEAD(&dev->bus->child, pxb_bus, sibling); }


static void v9fs_flush(void *opaque) { int16_t tag; size_t offset = 7; V9fsPDU *cancel_pdu; V9fsPDU *pdu = opaque; V9fsState *s = pdu->s; pdu_unmarshal(pdu, offset, "w", &tag); trace_v9fs_flush(pdu->tag, pdu->id, tag); QLIST_FOREACH(cancel_pdu, &s->active_list, next) { if (cancel_pdu->tag == tag) { break; } } if (cancel_pdu) { cancel_pdu->cancelled = 1; /* * Wait for pdu to complete. */ qemu_co_queue_wait(&cancel_pdu->complete); cancel_pdu->cancelled = 0; free_pdu(pdu->s, cancel_pdu); } complete_pdu(s, pdu, 7); return; }


static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); assert(in_range_b(disp)); return disp & 0x3fffffc; }


static void enable_interrupt(EEPRO100State * s) { if (!s->int_stat) { logout("interrupt enabled\n"); qemu_irq_raise(s->pci_dev->irq[0]); s->int_stat = 1; } }


static abi_ulong load_elf_interp(struct elfhdr * interp_elf_ex, int interpreter_fd, abi_ulong *interp_load_addr, char bprm_buf[BPRM_BUF_SIZE]) { struct elf_phdr *elf_phdata = NULL; abi_ulong load_addr, load_bias, loaddr, hiaddr; int retval; abi_ulong error; int i; bswap_ehdr(interp_elf_ex); /* First of all, some simple consistency checks */ if ((interp_elf_ex->e_type != ET_EXEC && interp_elf_ex->e_type != ET_DYN) || !elf_check_arch(interp_elf_ex->e_machine)) { return ~((abi_ulong)0UL); } /* Now read in all of the header information */ if (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum > TARGET_PAGE_SIZE) return ~(abi_ulong)0UL; elf_phdata = (struct elf_phdr *) malloc(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); if (!elf_phdata) return ~((abi_ulong)0UL); /* * If the size of this structure has changed, then punt, since * we will be doing the wrong thing. */ if (interp_elf_ex->e_phentsize != sizeof(struct elf_phdr)) { free(elf_phdata); return ~((abi_ulong)0UL); } i = interp_elf_ex->e_phnum * sizeof(struct elf_phdr); if (interp_elf_ex->e_phoff + i <= BPRM_BUF_SIZE) { memcpy(elf_phdata, bprm_buf + interp_elf_ex->e_phoff, i); } else { retval = pread(interpreter_fd, elf_phdata, i, interp_elf_ex->e_phoff); if (retval != i) { perror("load_elf_interp"); exit(-1); } } bswap_phdr(elf_phdata, interp_elf_ex->e_phnum); /* Find the maximum size of the image and allocate an appropriate amount of memory to handle that. */ loaddr = -1, hiaddr = 0; for (i = 0; i < interp_elf_ex->e_phnum; ++i) { if (elf_phdata[i].p_type == PT_LOAD) { abi_ulong a = elf_phdata[i].p_vaddr; if (a < loaddr) { loaddr = a; } a += elf_phdata[i].p_memsz; if (a > hiaddr) { hiaddr = a; } } } load_addr = loaddr; if (interp_elf_ex->e_type == ET_DYN) { /* The image indicates that it can be loaded anywhere. Find a location that can hold the memory space required. If the image is pre-linked, LOADDR will be non-zero. Since we do not supply MAP_FIXED here we'll use that address if and only if it remains available. */ load_addr = target_mmap(loaddr, hiaddr - loaddr, PROT_NONE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); if (load_addr == -1) { perror("mmap"); exit(-1); } } load_bias = load_addr - loaddr; for (i = 0; i < interp_elf_ex->e_phnum; i++) { struct elf_phdr *eppnt = elf_phdata + i; if (eppnt->p_type == PT_LOAD) { abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em; int elf_prot = 0; if (eppnt->p_flags & PF_R) elf_prot = PROT_READ; if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE; if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC; vaddr = load_bias + eppnt->p_vaddr; vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr); vaddr_ps = TARGET_ELF_PAGESTART(vaddr); error = target_mmap(vaddr_ps, eppnt->p_filesz + vaddr_po, elf_prot, MAP_PRIVATE | MAP_FIXED, interpreter_fd, eppnt->p_offset - vaddr_po); if (error == -1) { /* Real error */ close(interpreter_fd); free(elf_phdata); return ~((abi_ulong)0UL); } vaddr_ef = vaddr + eppnt->p_filesz; vaddr_em = vaddr + eppnt->p_memsz; /* If the load segment requests extra zeros (e.g. bss), map it. */ if (vaddr_ef < vaddr_em) { zero_bss(vaddr_ef, vaddr_em, elf_prot); } } } if (qemu_log_enabled()) { load_symbols(interp_elf_ex, interpreter_fd, load_bias); } close(interpreter_fd); free(elf_phdata); *interp_load_addr = load_addr; return ((abi_ulong) interp_elf_ex->e_entry) + load_bias; }


static int execute_command(BlockDriverState *bdrv, SCSIGenericReq *r, int direction, BlockCompletionFunc *complete) { r->io_header.interface_id = 'S'; r->io_header.dxfer_direction = direction; r->io_header.dxferp = r->buf; r->io_header.dxfer_len = r->buflen; r->io_header.cmdp = r->req.cmd.buf; r->io_header.cmd_len = r->req.cmd.len; r->io_header.mx_sb_len = sizeof(r->req.sense); r->io_header.sbp = r->req.sense; r->io_header.timeout = MAX_UINT; r->io_header.usr_ptr = r; r->io_header.flags |= SG_FLAG_DIRECT_IO; r->req.aiocb = bdrv_aio_ioctl(bdrv, SG_IO, &r->io_header, complete, r); if (r->req.aiocb == NULL) { return -EIO; } return 0; }


void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) { uint8_t *ptr; MemoryRegionSection *section; section = phys_page_find(addr >> TARGET_PAGE_BITS); if (!memory_region_is_ram(section->mr) || section->readonly) { addr = memory_region_section_addr(section, addr); if (memory_region_is_ram(section->mr)) { section = &phys_sections[phys_section_rom]; } #ifdef TARGET_WORDS_BIGENDIAN io_mem_write(section->mr, addr, val >> 32, 4); io_mem_write(section->mr, addr + 4, (uint32_t)val, 4); #else io_mem_write(section->mr, addr, (uint32_t)val, 4); io_mem_write(section->mr, addr + 4, val >> 32, 4); #endif } else { ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) + memory_region_section_addr(section, addr)); stq_p(ptr, val); } }


static void clear_program(MpegTSContext *ts, unsigned int programid) { int i; clear_avprogram(ts, programid); for(i=0; i<ts->nb_prg; i++) if(ts->prg[i].id == programid) ts->prg[i].nb_pids = 0; }


static void jpeg2000_flush(Jpeg2000DecoderContext *s) { if (*s->buf == 0xff) s->buf++; s->bit_index = 8; s->buf++; }


static void kvm_apic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t data, unsigned size) { MSIMessage msg = { .address = addr, .data = data }; int ret; ret = kvm_irqchip_send_msi(kvm_state, msg); if (ret < 0) { fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", strerror(-ret)); } }


void os_daemonize(void) { if (daemonize) { pid_t pid; int fds[2]; if (pipe(fds) == -1) { exit(1); } pid = fork(); if (pid > 0) { uint8_t status; ssize_t len; close(fds[1]); again: len = read(fds[0], &status, 1); if (len == -1 && (errno == EINTR)) { goto again; } if (len != 1) { exit(1); } else if (status == 1) { fprintf(stderr, "Could not acquire pidfile\n"); exit(1); } else { exit(0); } } else if (pid < 0) { exit(1); } close(fds[0]); daemon_pipe = fds[1]; qemu_set_cloexec(daemon_pipe); setsid(); pid = fork(); if (pid > 0) { exit(0); } else if (pid < 0) { exit(1); } umask(027); signal(SIGTSTP, SIG_IGN); signal(SIGTTOU, SIG_IGN); signal(SIGTTIN, SIG_IGN); } }


int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info = pinfo; ucontext_t *uc = puc; uint32_t *pc = uc->uc_mcontext.sc_pc; uint32_t insn = *pc; int is_write = 0; /* XXX: need kernel patch to get write flag faster */ switch (insn >> 26) { case 0x0d: /* stw */ case 0x0e: /* stb */ case 0x0f: /* stq_u */ case 0x24: /* stf */ case 0x25: /* stg */ case 0x26: /* sts */ case 0x27: /* stt */ case 0x2c: /* stl */ case 0x2d: /* stq */ case 0x2e: /* stl_c */ case 0x2f: /* stq_c */ is_write = 1; } return handle_cpu_signal(pc, (unsigned long)info->si_addr, is_write, &uc->uc_sigmask); }


static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset) { uint32_t addr; uint16_t mask; uint16_t v; addr = bitband_addr(opaque, offset) & ~1; mask = (1 << ((offset >> 2) & 15)); mask = tswap16(mask); cpu_physical_memory_read(addr, (uint8_t *)&v, 2); return (v & mask) != 0; }


static void sd_set_ocr(SDState *sd) { /* All voltages OK, card power-up OK, Standard Capacity SD Memory Card */ sd->ocr = 0x80ffff00; }


static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) { PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; switch (addr) { case RTTR: return s->rttr; case RTSR: return s->rtsr; case RTAR: return s->rtar; case RDAR1: return s->rdar1; case RDAR2: return s->rdar2; case RYAR1: return s->ryar1; case RYAR2: return s->ryar2; case SWAR1: return s->swar1; case SWAR2: return s->swar2; case PIAR: return s->piar; case RCNR: return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); case RDCR: return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); case RYCR: return s->last_rycr; case SWCR: if (s->rtsr & (1 << 12)) return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; else return s->last_swcr; default: printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); break; } return 0; }


static int check_protocol_support(bool *has_ipv4, bool *has_ipv6) { #ifdef HAVE_IFADDRS_H struct ifaddrs *ifaddr = NULL, *ifa; struct addrinfo hints = { 0 }; struct addrinfo *ai = NULL; int gaierr; *has_ipv4 = *has_ipv6 = false; if (getifaddrs(&ifaddr) < 0) { g_printerr("Failed to lookup interface addresses: %s\n", strerror(errno)); return -1; } for (ifa = ifaddr; ifa != NULL; ifa = ifa->ifa_next) { if (!ifa->ifa_addr) { continue; } if (ifa->ifa_addr->sa_family == AF_INET) { *has_ipv4 = true; } if (ifa->ifa_addr->sa_family == AF_INET6) { *has_ipv6 = true; } } freeifaddrs(ifaddr); hints.ai_flags = AI_PASSIVE | AI_ADDRCONFIG; hints.ai_family = AF_INET6; hints.ai_socktype = SOCK_STREAM; gaierr = getaddrinfo("::1", NULL, &hints, &ai); if (gaierr != 0) { if (gaierr == EAI_ADDRFAMILY || gaierr == EAI_FAMILY || gaierr == EAI_NONAME) { *has_ipv6 = false; } else { g_printerr("Failed to resolve ::1 address: %s\n", gai_strerror(gaierr)); return -1; } } freeaddrinfo(ai); return 0; #else *has_ipv4 = *has_ipv6 = false; return -1; #endif }


static int init(AVFilterContext *ctx) { EvalContext *eval = ctx->priv; char *args1 = av_strdup(eval->exprs); char *expr, *buf; int ret, i; if (!args1) { av_log(ctx, AV_LOG_ERROR, "Channels expressions list is empty\n"); ret = eval->exprs ? AVERROR(ENOMEM) : AVERROR(EINVAL); goto end; } /* parse expressions */ buf = args1; i = 0; while (i < FF_ARRAY_ELEMS(eval->expr) && (expr = av_strtok(buf, "|", &buf))) { ret = av_expr_parse(&eval->expr[i], expr, var_names, NULL, NULL, NULL, NULL, 0, ctx); if (ret < 0) goto end; i++; } eval->nb_channels = i; if (eval->chlayout_str) { int n; ret = ff_parse_channel_layout(&eval->chlayout, eval->chlayout_str, ctx); if (ret < 0) goto end; n = av_get_channel_layout_nb_channels(eval->chlayout); if (n != eval->nb_channels) { av_log(ctx, AV_LOG_ERROR, "Mismatch between the specified number of channels '%d' " "and the number of channels '%d' in the specified channel layout '%s'\n", eval->nb_channels, n, eval->chlayout_str); ret = AVERROR(EINVAL); goto end; } } else { /* guess channel layout from nb expressions/channels */ eval->chlayout = av_get_default_channel_layout(eval->nb_channels); if (!eval->chlayout) { av_log(ctx, AV_LOG_ERROR, "Invalid number of channels '%d' provided\n", eval->nb_channels); ret = AVERROR(EINVAL); goto end; } } if ((ret = ff_parse_sample_rate(&eval->sample_rate, eval->sample_rate_str, ctx))) goto end; eval->n = 0; end: av_free(args1); return ret; }


void OPPROTO op_addl_EDI_T0(void) { EDI = (uint32_t)(EDI + T0); }


START_TEST(qdict_haskey_not_test) { fail_unless(qdict_haskey(tests_dict, "test") == 0); }


static void test_acpi_piix4_tcg_memhp(void) { test_data data; memset(&data, 0, sizeof(data)); data.machine = MACHINE_PC; data.variant = ".memhp"; test_acpi_one(" -m 128,slots=3,maxmem=1G -numa node", &data); free_test_data(&data); }


static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) { int b1, op1_offset, op2_offset, is_xmm, val, ot; int modrm, mod, rm, reg, reg_addr, offset_addr; GenOpFunc2 *sse_op2; GenOpFunc3 *sse_op3; b &= 0xff; if (s->prefix & PREFIX_DATA) b1 = 1; else if (s->prefix & PREFIX_REPZ) b1 = 2; else if (s->prefix & PREFIX_REPNZ) b1 = 3; else b1 = 0; sse_op2 = sse_op_table1[b][b1]; if (!sse_op2) goto illegal_op; if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { is_xmm = 1; } else { if (b1 == 0) { /* MMX case */ is_xmm = 0; } else { is_xmm = 1; } } /* simple MMX/SSE operation */ if (s->flags & HF_TS_MASK) { gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); return; } if (s->flags & HF_EM_MASK) { illegal_op: gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); return; } if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) goto illegal_op; if (b == 0x77 || b == 0x0e) { /* emms or femms */ gen_op_emms(); return; } /* prepare MMX state (XXX: optimize by storing fptt and fptags in the static cpu state) */ if (!is_xmm) { gen_op_enter_mmx(); } modrm = ldub_code(s->pc++); reg = ((modrm >> 3) & 7); if (is_xmm) reg |= rex_r; mod = (modrm >> 6) & 3; if (sse_op2 == SSE_SPECIAL) { b |= (b1 << 8); switch(b) { case 0x0e7: /* movntq */ if (mod == 3) goto illegal_op; gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx)); break; case 0x1e7: /* movntdq */ case 0x02b: /* movntps */ case 0x12b: /* movntps */ case 0x3f0: /* lddqu */ if (mod == 3) goto illegal_op; gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg])); break; case 0x6e: /* movd mm, ea */ #ifdef TARGET_X86_64 if (s->dflag == 2) { gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); gen_op_movq_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx)); } else #endif { gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx)); } break; case 0x16e: /* movd xmm, ea */ #ifdef TARGET_X86_64 if (s->dflag == 2) { gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); gen_op_movq_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg])); } else #endif { gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg])); } break; case 0x6f: /* movq mm, ea */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx)); } else { rm = (modrm & 7); gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx), offsetof(CPUX86State,fpregs[rm].mmx)); } break; case 0x010: /* movups */ case 0x110: /* movupd */ case 0x028: /* movaps */ case 0x128: /* movapd */ case 0x16f: /* movdqa xmm, ea */ case 0x26f: /* movdqu xmm, ea */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), offsetof(CPUX86State,xmm_regs[rm])); } break; case 0x210: /* movss xmm, ea */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_op_ld_T0_A0(OT_LONG + s->mem_index); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_movl_T0_0(); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); } break; case 0x310: /* movsd xmm, ea */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); gen_op_movl_T0_0(); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); } break; case 0x012: /* movlps */ case 0x112: /* movlpd */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { /* movhlps */ rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); } break; case 0x212: /* movsldup */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); } gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); break; case 0x312: /* movddup */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); } gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); break; case 0x016: /* movhps */ case 0x116: /* movhpd */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); } else { /* movlhps */ rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); } break; case 0x216: /* movshdup */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); } gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); break; case 0x7e: /* movd ea, mm */ #ifdef TARGET_X86_64 if (s->dflag == 2) { gen_op_movq_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx)); gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); } else #endif { gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx)); gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); } break; case 0x17e: /* movd ea, xmm */ #ifdef TARGET_X86_64 if (s->dflag == 2) { gen_op_movq_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg])); gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); } else #endif { gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg])); gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); } break; case 0x27e: /* movq xmm, ea */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); } gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); break; case 0x7f: /* movq ea, mm */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx)); } else { rm = (modrm & 7); gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), offsetof(CPUX86State,fpregs[reg].mmx)); } break; case 0x011: /* movups */ case 0x111: /* movupd */ case 0x029: /* movaps */ case 0x129: /* movapd */ case 0x17f: /* movdqa ea, xmm */ case 0x27f: /* movdqu ea, xmm */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), offsetof(CPUX86State,xmm_regs[reg])); } break; case 0x211: /* movss ea, xmm */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_st_T0_A0(OT_LONG + s->mem_index); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); } break; case 0x311: /* movsd ea, xmm */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } break; case 0x013: /* movlps */ case 0x113: /* movlpd */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { goto illegal_op; } break; case 0x017: /* movhps */ case 0x117: /* movhpd */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); } else { goto illegal_op; } break; case 0x71: /* shift mm, im */ case 0x72: case 0x73: case 0x171: /* shift xmm, im */ case 0x172: case 0x173: val = ldub_code(s->pc++); if (is_xmm) { gen_op_movl_T0_im(val); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); gen_op_movl_T0_0(); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { gen_op_movl_T0_im(val); gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0))); gen_op_movl_T0_0(); gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; if (!sse_op2) goto illegal_op; if (is_xmm) { rm = (modrm & 7) | REX_B(s); op2_offset = offsetof(CPUX86State,xmm_regs[rm]); } else { rm = (modrm & 7); op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); } sse_op2(op2_offset, op1_offset); break; case 0x050: /* movmskps */ rm = (modrm & 7) | REX_B(s); gen_op_movmskps(offsetof(CPUX86State,xmm_regs[rm])); gen_op_mov_reg_T0(OT_LONG, reg); break; case 0x150: /* movmskpd */ rm = (modrm & 7) | REX_B(s); gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[rm])); gen_op_mov_reg_T0(OT_LONG, reg); break; case 0x02a: /* cvtpi2ps */ case 0x12a: /* cvtpi2pd */ gen_op_enter_mmx(); if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); gen_ldq_env_A0[s->mem_index >> 2](op2_offset); } else { rm = (modrm & 7); op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); } op1_offset = offsetof(CPUX86State,xmm_regs[reg]); switch(b >> 8) { case 0x0: gen_op_cvtpi2ps(op1_offset, op2_offset); break; default: case 0x1: gen_op_cvtpi2pd(op1_offset, op2_offset); break; } break; case 0x22a: /* cvtsi2ss */ case 0x32a: /* cvtsi2sd */ ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); op1_offset = offsetof(CPUX86State,xmm_regs[reg]); sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset); break; case 0x02c: /* cvttps2pi */ case 0x12c: /* cvttpd2pi */ case 0x02d: /* cvtps2pi */ case 0x12d: /* cvtpd2pi */ gen_op_enter_mmx(); if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); gen_ldo_env_A0[s->mem_index >> 2](op2_offset); } else { rm = (modrm & 7) | REX_B(s); op2_offset = offsetof(CPUX86State,xmm_regs[rm]); } op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); switch(b) { case 0x02c: gen_op_cvttps2pi(op1_offset, op2_offset); break; case 0x12c: gen_op_cvttpd2pi(op1_offset, op2_offset); break; case 0x02d: gen_op_cvtps2pi(op1_offset, op2_offset); break; case 0x12d: gen_op_cvtpd2pi(op1_offset, op2_offset); break; } break; case 0x22c: /* cvttss2si */ case 0x32c: /* cvttsd2si */ case 0x22d: /* cvtss2si */ case 0x32d: /* cvtsd2si */ ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); if ((b >> 8) & 1) { gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_Q(0))); } else { gen_op_ld_T0_A0(OT_LONG + s->mem_index); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); } op2_offset = offsetof(CPUX86State,xmm_t0); } else { rm = (modrm & 7) | REX_B(s); op2_offset = offsetof(CPUX86State,xmm_regs[rm]); } sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + (b & 1) * 4](op2_offset); gen_op_mov_reg_T0(ot, reg); break; case 0xc4: /* pinsrw */ case 0x1c4: s->rip_offset = 1; gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); val = ldub_code(s->pc++); if (b1) { val &= 7; gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val); } else { val &= 3; gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val); } break; case 0xc5: /* pextrw */ case 0x1c5: if (mod != 3) goto illegal_op; val = ldub_code(s->pc++); if (b1) { val &= 7; rm = (modrm & 7) | REX_B(s); gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val); } else { val &= 3; rm = (modrm & 7); gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val); } reg = ((modrm >> 3) & 7) | rex_r; gen_op_mov_reg_T0(OT_LONG, reg); break; case 0x1d6: /* movq ea, xmm */ if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); } break; case 0x2d6: /* movq2dq */ gen_op_enter_mmx(); rm = (modrm & 7); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,fpregs[rm].mmx)); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); break; case 0x3d6: /* movdq2q */ gen_op_enter_mmx(); rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); break; case 0xd7: /* pmovmskb */ case 0x1d7: if (mod != 3) goto illegal_op; if (b1) { rm = (modrm & 7) | REX_B(s); gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm])); } else { rm = (modrm & 7); gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx)); } reg = ((modrm >> 3) & 7) | rex_r; gen_op_mov_reg_T0(OT_LONG, reg); break; default: goto illegal_op; } } else { /* generic MMX or SSE operation */ switch(b) { case 0xf7: /* maskmov : we must prepare A0 */ if (mod != 3) goto illegal_op; #ifdef TARGET_X86_64 if (s->aflag == 2) { gen_op_movq_A0_reg(R_EDI); } else #endif { gen_op_movl_A0_reg(R_EDI); if (s->aflag == 0) gen_op_andl_A0_ffff(); } gen_add_A0_ds_seg(s); break; case 0x70: /* pshufx insn */ case 0xc6: /* pshufx insn */ case 0xc2: /* compare insns */ s->rip_offset = 1; break; default: break; } if (is_xmm) { op1_offset = offsetof(CPUX86State,xmm_regs[reg]); if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || b == 0xc2)) { /* specific case for SSE single instructions */ if (b1 == 2) { /* 32 bit access */ gen_op_ld_T0_A0(OT_LONG + s->mem_index); gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); } else { /* 64 bit access */ gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0))); } } else { gen_ldo_env_A0[s->mem_index >> 2](op2_offset); } } else { rm = (modrm & 7) | REX_B(s); op2_offset = offsetof(CPUX86State,xmm_regs[rm]); } } else { op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); if (mod != 3) { gen_lea_modrm(s, modrm, &reg_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); gen_ldq_env_A0[s->mem_index >> 2](op2_offset); } else { rm = (modrm & 7); op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); } } switch(b) { case 0x0f: /* 3DNow! data insns */ val = ldub_code(s->pc++); sse_op2 = sse_op_table5[val]; if (!sse_op2) goto illegal_op; sse_op2(op1_offset, op2_offset); break; case 0x70: /* pshufx insn */ case 0xc6: /* pshufx insn */ val = ldub_code(s->pc++); sse_op3 = (GenOpFunc3 *)sse_op2; sse_op3(op1_offset, op2_offset, val); break; case 0xc2: /* compare insns */ val = ldub_code(s->pc++); if (val >= 8) goto illegal_op; sse_op2 = sse_op_table4[val][b1]; sse_op2(op1_offset, op2_offset); break; default: sse_op2(op1_offset, op2_offset); break; } if (b == 0x2e || b == 0x2f) { s->cc_op = CC_OP_EFLAGS; } } }


int ff_h264_pred_weight_table(GetBitContext *gb, const SPS *sps, const int *ref_count, int slice_type_nos, H264PredWeightTable *pwt, void *logctx) { int list, i, j; int luma_def, chroma_def; pwt->use_weight = 0; pwt->use_weight_chroma = 0; pwt->luma_log2_weight_denom = get_ue_golomb(gb); if (sps->chroma_format_idc) pwt->chroma_log2_weight_denom = get_ue_golomb(gb); if (pwt->luma_log2_weight_denom > 7U) { av_log(logctx, AV_LOG_ERROR, "luma_log2_weight_denom %d is out of range\n", pwt->luma_log2_weight_denom); pwt->luma_log2_weight_denom = 0; } if (pwt->chroma_log2_weight_denom > 7U) { av_log(logctx, AV_LOG_ERROR, "chroma_log2_weight_denom %d is out of range\n", pwt->chroma_log2_weight_denom); pwt->chroma_log2_weight_denom = 0; } luma_def = 1 << pwt->luma_log2_weight_denom; chroma_def = 1 << pwt->chroma_log2_weight_denom; for (list = 0; list < 2; list++) { pwt->luma_weight_flag[list] = 0; pwt->chroma_weight_flag[list] = 0; for (i = 0; i < ref_count[list]; i++) { int luma_weight_flag, chroma_weight_flag; luma_weight_flag = get_bits1(gb); if (luma_weight_flag) { pwt->luma_weight[i][list][0] = get_se_golomb(gb); pwt->luma_weight[i][list][1] = get_se_golomb(gb); if (pwt->luma_weight[i][list][0] != luma_def || pwt->luma_weight[i][list][1] != 0) { pwt->use_weight = 1; pwt->luma_weight_flag[list] = 1; } } else { pwt->luma_weight[i][list][0] = luma_def; pwt->luma_weight[i][list][1] = 0; } if (sps->chroma_format_idc) { chroma_weight_flag = get_bits1(gb); if (chroma_weight_flag) { int j; for (j = 0; j < 2; j++) { pwt->chroma_weight[i][list][j][0] = get_se_golomb(gb); pwt->chroma_weight[i][list][j][1] = get_se_golomb(gb); if ((int8_t)pwt->chroma_weight[i][list][j][0] != pwt->chroma_weight[i][list][j][0] || (int8_t)pwt->chroma_weight[i][list][j][1] != pwt->chroma_weight[i][list][j][1]) if (pwt->chroma_weight[i][list][j][0] != chroma_def || pwt->chroma_weight[i][list][j][1] != 0) { pwt->use_weight_chroma = 1; pwt->chroma_weight_flag[list] = 1; } } } else { int j; for (j = 0; j < 2; j++) { pwt->chroma_weight[i][list][j][0] = chroma_def; pwt->chroma_weight[i][list][j][1] = 0; } } } // for MBAFF pwt->luma_weight[16 + 2 * i][list][0] = pwt->luma_weight[16 + 2 * i + 1][list][0] = pwt->luma_weight[i][list][0]; pwt->luma_weight[16 + 2 * i][list][1] = pwt->luma_weight[16 + 2 * i + 1][list][1] = pwt->luma_weight[i][list][1]; for (j = 0; j < 2; j++) { pwt->chroma_weight[16 + 2 * i][list][j][0] = pwt->chroma_weight[16 + 2 * i + 1][list][j][0] = pwt->chroma_weight[i][list][j][0]; pwt->chroma_weight[16 + 2 * i][list][j][1] = pwt->chroma_weight[16 + 2 * i + 1][list][j][1] = pwt->chroma_weight[i][list][j][1]; } } if (slice_type_nos != AV_PICTURE_TYPE_B) break; } pwt->use_weight = pwt->use_weight || pwt->use_weight_chroma; return 0; out_range_weight: avpriv_request_sample(logctx, "Out of range weight\n"); return AVERROR_INVALIDDATA; }


static int do_vm_stop(RunState state) { int ret = 0; if (runstate_is_running()) { cpu_disable_ticks(); pause_all_vcpus(); runstate_set(state); vm_state_notify(0, state); qapi_event_send_stop(&error_abort); } bdrv_drain_all(); ret = blk_flush_all(); return ret; }


static int cin_read_packet(AVFormatContext *s, AVPacket *pkt) { CinDemuxContext *cin = s->priv_data; ByteIOContext *pb = s->pb; CinFrameHeader *hdr = &cin->frame_header; int rc, palette_type, pkt_size; if (cin->audio_buffer_size == 0) { rc = cin_read_frame_header(cin, pb); if (rc) return rc; if ((int16_t)hdr->pal_colors_count < 0) { hdr->pal_colors_count = -(int16_t)hdr->pal_colors_count; palette_type = 1; } else { palette_type = 0; } /* palette and video packet */ pkt_size = (palette_type + 3) * hdr->pal_colors_count + hdr->video_frame_size; if (av_new_packet(pkt, 4 + pkt_size)) return AVERROR(ENOMEM); pkt->stream_index = cin->video_stream_index; pkt->pts = cin->video_stream_pts++; pkt->data[0] = palette_type; pkt->data[1] = hdr->pal_colors_count & 0xFF; pkt->data[2] = hdr->pal_colors_count >> 8; pkt->data[3] = hdr->video_frame_type; if (get_buffer(pb, &pkt->data[4], pkt_size) != pkt_size) return AVERROR(EIO); /* sound buffer will be processed on next read_packet() call */ cin->audio_buffer_size = hdr->audio_frame_size; return 0; } /* audio packet */ if (av_new_packet(pkt, cin->audio_buffer_size)) return AVERROR(ENOMEM); pkt->stream_index = cin->audio_stream_index; pkt->pts = cin->audio_stream_pts; cin->audio_stream_pts += cin->audio_buffer_size * 2 / cin->file_header.audio_frame_size; if (get_buffer(pb, pkt->data, cin->audio_buffer_size) != cin->audio_buffer_size) return AVERROR(EIO); cin->audio_buffer_size = 0; return 0; }


static void kvm_do_inject_x86_mce(void *_data) { struct kvm_x86_mce_data *data = _data; int r; r = kvm_set_mce(data->env, data->mce); if (r < 0) perror("kvm_set_mce FAILED"); }


static int v4l2_receive_packet(AVCodecContext *avctx, AVPacket *avpkt) { V4L2m2mContext *s = avctx->priv_data; V4L2Context *const capture = &s->capture; V4L2Context *const output = &s->output; int ret; if (s->draining) goto dequeue; if (!output->streamon) { ret = ff_v4l2_context_set_status(output, VIDIOC_STREAMON); if (ret) { av_log(avctx, AV_LOG_ERROR, "VIDIOC_STREAMOFF failed on output context\n"); return ret; } } if (!capture->streamon) { ret = ff_v4l2_context_set_status(capture, VIDIOC_STREAMON); if (ret) { av_log(avctx, AV_LOG_ERROR, "VIDIOC_STREAMON failed on capture context\n"); return ret; } } dequeue: return ff_v4l2_context_dequeue_packet(capture, avpkt); }


static int mov_rewrite_dvd_sub_extradata(AVStream *st) { char pal_s[256]; char buf[256]; int pal_s_pos = 0; uint8_t *src = st->codec->extradata; int i; if (st->codec->extradata_size != 64) return 0; for (i = 0; i < 16; i++) { uint32_t yuv = AV_RB32(src + i * 4); uint32_t rgba = yuv_to_rgba(yuv); snprintf(pal_s + pal_s_pos, sizeof(pal_s) - pal_s_pos, "%06x%s", rgba, i != 15 ? ", " : ""); pal_s_pos = strlen(pal_s); if (pal_s_pos >= sizeof(pal_s)) return 0; } snprintf(buf, sizeof(buf), "size: %dx%d\npalette: %s\n", st->codec->width, st->codec->height, pal_s); av_freep(&st->codec->extradata); st->codec->extradata_size = 0; st->codec->extradata = av_mallocz(strlen(buf) + FF_INPUT_BUFFER_PADDING_SIZE); if (!st->codec->extradata) return AVERROR(ENOMEM); st->codec->extradata_size = strlen(buf); memcpy(st->codec->extradata, buf, st->codec->extradata_size); return 0; }


static void do_streamcopy(InputStream *ist, OutputStream *ost, const AVPacket *pkt) { OutputFile *of = output_files[ost->file_index]; int64_t ost_tb_start_time = av_rescale_q(of->start_time, AV_TIME_BASE_Q, ost->st->time_base); AVPacket opkt; av_init_packet(&opkt); if ((!ost->frame_number && !(pkt->flags & AV_PKT_FLAG_KEY)) && !ost->copy_initial_nonkeyframes) return; if (of->recording_time != INT64_MAX && ist->last_dts >= of->recording_time + of->start_time) { ost->is_past_recording_time = 1; return; } /* force the input stream PTS */ if (ost->st->codec->codec_type == AVMEDIA_TYPE_AUDIO) audio_size += pkt->size; else if (ost->st->codec->codec_type == AVMEDIA_TYPE_VIDEO) { video_size += pkt->size; ost->sync_opts++; } if (pkt->pts != AV_NOPTS_VALUE) opkt.pts = av_rescale_q(pkt->pts, ist->st->time_base, ost->st->time_base) - ost_tb_start_time; else opkt.pts = AV_NOPTS_VALUE; if (pkt->dts == AV_NOPTS_VALUE) opkt.dts = av_rescale_q(ist->last_dts, AV_TIME_BASE_Q, ost->st->time_base); else opkt.dts = av_rescale_q(pkt->dts, ist->st->time_base, ost->st->time_base); opkt.dts -= ost_tb_start_time; opkt.duration = av_rescale_q(pkt->duration, ist->st->time_base, ost->st->time_base); opkt.flags = pkt->flags; // FIXME remove the following 2 lines they shall be replaced by the bitstream filters if ( ost->st->codec->codec_id != AV_CODEC_ID_H264 && ost->st->codec->codec_id != AV_CODEC_ID_MPEG1VIDEO && ost->st->codec->codec_id != AV_CODEC_ID_MPEG2VIDEO && ost->st->codec->codec_id != AV_CODEC_ID_VC1 ) { if (av_parser_change(ist->st->parser, ost->st->codec, &opkt.data, &opkt.size, pkt->data, pkt->size, pkt->flags & AV_PKT_FLAG_KEY)) opkt.destruct = av_destruct_packet; } else { opkt.data = pkt->data; opkt.size = pkt->size; } write_frame(of->ctx, &opkt, ost); ost->st->codec->frame_number++; av_free_packet(&opkt); }


static int au_read_packet(AVFormatContext *s, AVPacket *pkt) { int ret; ret= av_get_packet(s->pb, pkt, BLOCK_SIZE * s->streams[0]->codec->channels * av_get_bits_per_sample(s->streams[0]->codec->codec_id) >> 3); if (ret < 0) return ret; pkt->flags &= ~AV_PKT_FLAG_CORRUPT; pkt->stream_index = 0; return 0; }


int av_find_stream_info(AVFormatContext *ic) { int i, count, ret, read_size, j; AVStream *st; AVPacket pkt1, *pkt; int64_t old_offset = url_ftell(ic->pb); struct { int64_t last_dts; int64_t duration_gcd; int duration_count; double duration_error[MAX_STD_TIMEBASES]; int64_t codec_info_duration; } info[MAX_STREAMS] = {{0}}; for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if (st->codec->codec_id == CODEC_ID_AAC) { st->codec->sample_rate = 0; st->codec->frame_size = 0; st->codec->channels = 0; } if(st->codec->codec_type == AVMEDIA_TYPE_VIDEO){ /* if(!st->time_base.num) st->time_base= */ if(!st->codec->time_base.num) st->codec->time_base= st->time_base; } //only for the split stuff if (!st->parser && !(ic->flags & AVFMT_FLAG_NOPARSE)) { st->parser = av_parser_init(st->codec->codec_id); if(st->need_parsing == AVSTREAM_PARSE_HEADERS && st->parser){ st->parser->flags |= PARSER_FLAG_COMPLETE_FRAMES; } } assert(!st->codec->codec); //try to just open decoders, in case this is enough to get parameters if(!has_codec_parameters(st->codec)){ AVCodec *codec = avcodec_find_decoder(st->codec->codec_id); if (codec) avcodec_open(st->codec, codec); } } for(i=0;i<MAX_STREAMS;i++){ info[i].last_dts= AV_NOPTS_VALUE; } count = 0; read_size = 0; for(;;) { if(url_interrupt_cb()){ ret= AVERROR(EINTR); av_log(ic, AV_LOG_DEBUG, "interrupted\n"); break; } /* check if one codec still needs to be handled */ for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if (!has_codec_parameters(st->codec)) break; /* variable fps and no guess at the real fps */ if( tb_unreliable(st->codec) && !(st->r_frame_rate.num && st->avg_frame_rate.num) && info[i].duration_count<20 && st->codec->codec_type == AVMEDIA_TYPE_VIDEO) break; if(st->parser && st->parser->parser->split && !st->codec->extradata) break; if(st->first_dts == AV_NOPTS_VALUE) break; } if (i == ic->nb_streams) { /* NOTE: if the format has no header, then we need to read some packets to get most of the streams, so we cannot stop here */ if (!(ic->ctx_flags & AVFMTCTX_NOHEADER)) { /* if we found the info for all the codecs, we can stop */ ret = count; av_log(ic, AV_LOG_DEBUG, "All info found\n"); break; } } /* we did not get all the codec info, but we read too much data */ if (read_size >= ic->probesize) { ret = count; av_log(ic, AV_LOG_DEBUG, "Probe buffer size limit %d reached\n", ic->probesize); break; } /* NOTE: a new stream can be added there if no header in file (AVFMTCTX_NOHEADER) */ ret = av_read_frame_internal(ic, &pkt1); if(ret == AVERROR(EAGAIN)) continue; if (ret < 0) { /* EOF or error */ ret = -1; /* we could not have all the codec parameters before EOF */ for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if (!has_codec_parameters(st->codec)){ char buf[256]; avcodec_string(buf, sizeof(buf), st->codec, 0); av_log(ic, AV_LOG_WARNING, "Could not find codec parameters (%s)\n", buf); } else { ret = 0; } } break; } pkt= add_to_pktbuf(&ic->packet_buffer, &pkt1, &ic->packet_buffer_end); if(av_dup_packet(pkt) < 0) { return AVERROR(ENOMEM); } read_size += pkt->size; st = ic->streams[pkt->stream_index]; if(st->codec_info_nb_frames>1) { if (st->time_base.den > 0 && av_rescale_q(info[st->index].codec_info_duration, st->time_base, AV_TIME_BASE_Q) >= ic->max_analyze_duration){ av_log(ic, AV_LOG_WARNING, "max_analyze_duration reached\n"); break; } info[st->index].codec_info_duration += pkt->duration; } { int index= pkt->stream_index; int64_t last= info[index].last_dts; int64_t duration= pkt->dts - last; if(pkt->dts != AV_NOPTS_VALUE && last != AV_NOPTS_VALUE && duration>0){ double dur= duration * av_q2d(st->time_base); // if(st->codec->codec_type == AVMEDIA_TYPE_VIDEO) // av_log(NULL, AV_LOG_ERROR, "%f\n", dur); if(info[index].duration_count < 2) memset(info[index].duration_error, 0, sizeof(info[index].duration_error)); for(i=1; i<MAX_STD_TIMEBASES; i++){ int framerate= get_std_framerate(i); int ticks= lrintf(dur*framerate/(1001*12)); double error= dur - ticks*1001*12/(double)framerate; info[index].duration_error[i] += error*error; } info[index].duration_count++; // ignore the first 4 values, they might have some random jitter if (info[index].duration_count > 3) info[index].duration_gcd = av_gcd(info[index].duration_gcd, duration); } if(last == AV_NOPTS_VALUE || info[index].duration_count <= 1) info[pkt->stream_index].last_dts = pkt->dts; } if(st->parser && st->parser->parser->split && !st->codec->extradata){ int i= st->parser->parser->split(st->codec, pkt->data, pkt->size); if(i){ st->codec->extradata_size= i; st->codec->extradata= av_malloc(st->codec->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE); memcpy(st->codec->extradata, pkt->data, st->codec->extradata_size); memset(st->codec->extradata + i, 0, FF_INPUT_BUFFER_PADDING_SIZE); } } /* if still no information, we try to open the codec and to decompress the frame. We try to avoid that in most cases as it takes longer and uses more memory. For MPEG-4, we need to decompress for QuickTime. */ if (!has_codec_parameters(st->codec) || !has_decode_delay_been_guessed(st)) try_decode_frame(st, pkt); st->codec_info_nb_frames++; count++; } // close codecs which were opened in try_decode_frame() for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if(st->codec->codec) avcodec_close(st->codec); } for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if(st->codec_info_nb_frames>2 && !st->avg_frame_rate.num && info[i].codec_info_duration) av_reduce(&st->avg_frame_rate.num, &st->avg_frame_rate.den, (st->codec_info_nb_frames-2)*(int64_t)st->time_base.den, info[i].codec_info_duration*(int64_t)st->time_base.num, 60000); if (st->codec->codec_type == AVMEDIA_TYPE_VIDEO) { if(st->codec->codec_id == CODEC_ID_RAWVIDEO && !st->codec->codec_tag && !st->codec->bits_per_coded_sample) st->codec->codec_tag= avcodec_pix_fmt_to_codec_tag(st->codec->pix_fmt); // the check for tb_unreliable() is not completely correct, since this is not about handling // a unreliable/inexact time base, but a time base that is finer than necessary, as e.g. // ipmovie.c produces. if (tb_unreliable(st->codec) && info[i].duration_count > 15 && info[i].duration_gcd > 1 && !st->r_frame_rate.num) av_reduce(&st->r_frame_rate.num, &st->r_frame_rate.den, st->time_base.den, st->time_base.num * info[i].duration_gcd, INT_MAX); if(info[i].duration_count && !st->r_frame_rate.num && tb_unreliable(st->codec) /*&& //FIXME we should not special-case MPEG-2, but this needs testing with non-MPEG-2 ... st->time_base.num*duration_sum[i]/info[i].duration_count*101LL > st->time_base.den*/){ int num = 0; double best_error= 2*av_q2d(st->time_base); best_error= best_error*best_error*info[i].duration_count*1000*12*30; for(j=1; j<MAX_STD_TIMEBASES; j++){ double error= info[i].duration_error[j] * get_std_framerate(j); // if(st->codec->codec_type == AVMEDIA_TYPE_VIDEO) // av_log(NULL, AV_LOG_ERROR, "%f %f\n", get_std_framerate(j) / 12.0/1001, error); if(error < best_error){ best_error= error; num = get_std_framerate(j); } } // do not increase frame rate by more than 1 % in order to match a standard rate. if (num && (!st->r_frame_rate.num || (double)num/(12*1001) < 1.01 * av_q2d(st->r_frame_rate))) av_reduce(&st->r_frame_rate.num, &st->r_frame_rate.den, num, 12*1001, INT_MAX); } if (!st->r_frame_rate.num){ if( st->codec->time_base.den * (int64_t)st->time_base.num <= st->codec->time_base.num * st->codec->ticks_per_frame * (int64_t)st->time_base.den){ st->r_frame_rate.num = st->codec->time_base.den; st->r_frame_rate.den = st->codec->time_base.num * st->codec->ticks_per_frame; }else{ st->r_frame_rate.num = st->time_base.den; st->r_frame_rate.den = st->time_base.num; } } }else if(st->codec->codec_type == AVMEDIA_TYPE_AUDIO) { if(!st->codec->bits_per_coded_sample) st->codec->bits_per_coded_sample= av_get_bits_per_sample(st->codec->codec_id); } } av_estimate_timings(ic, old_offset); compute_chapters_end(ic); #if 0 /* correct DTS for B-frame streams with no timestamps */ for(i=0;i<ic->nb_streams;i++) { st = ic->streams[i]; if (st->codec->codec_type == AVMEDIA_TYPE_VIDEO) { if(b-frames){ ppktl = &ic->packet_buffer; while(ppkt1){ if(ppkt1->stream_index != i) continue; if(ppkt1->pkt->dts < 0) break; if(ppkt1->pkt->pts != AV_NOPTS_VALUE) break; ppkt1->pkt->dts -= delta; ppkt1= ppkt1->next; } if(ppkt1) continue; st->cur_dts -= delta; } } } #endif return ret; }


static int r3d_read_reda(AVFormatContext *s, AVPacket *pkt, Atom *atom) { AVStream *st = s->streams[1]; int av_unused tmp, tmp2; int samples, size; uint64_t pos = avio_tell(s->pb); unsigned dts; int ret; dts = avio_rb32(s->pb); st->codec->sample_rate = avio_rb32(s->pb); if (st->codec->sample_rate <= 0) { av_log(s, AV_LOG_ERROR, "Bad sample rate\n"); return AVERROR_INVALIDDATA; } samples = avio_rb32(s->pb); tmp = avio_rb32(s->pb); av_dlog(s, "packet num %d\n", tmp); tmp = avio_rb16(s->pb); // unknown av_dlog(s, "unknown %d\n", tmp); tmp = avio_r8(s->pb); // major version tmp2 = avio_r8(s->pb); // minor version av_dlog(s, "version %d.%d\n", tmp, tmp2); tmp = avio_rb32(s->pb); // unknown av_dlog(s, "unknown %d\n", tmp); size = atom->size - 8 - (avio_tell(s->pb) - pos); if (size < 0) return -1; ret = av_get_packet(s->pb, pkt, size); if (ret < 0) { av_log(s, AV_LOG_ERROR, "error reading audio packet\n"); return ret; } pkt->stream_index = 1; pkt->dts = dts; pkt->duration = av_rescale(samples, st->time_base.den, st->codec->sample_rate); av_dlog(s, "pkt dts %"PRId64" duration %d samples %d sample rate %d\n", pkt->dts, pkt->duration, samples, st->codec->sample_rate); return 0; }


void hmp_hostfwd_add(Monitor *mon, const QDict *qdict) { const char *redir_str; SlirpState *s; const char *arg1 = qdict_get_str(qdict, "arg1"); const char *arg2 = qdict_get_try_str(qdict, "arg2"); const char *arg3 = qdict_get_try_str(qdict, "arg3"); if (arg2) { s = slirp_lookup(mon, arg1, arg2); redir_str = arg3; } else { s = slirp_lookup(mon, NULL, NULL); redir_str = arg1; } if (s) { slirp_hostfwd(s, redir_str, 0); } }


void rgb16tobgr32(const uint8_t *src, uint8_t *dst, long src_size) { const uint16_t *end; uint8_t *d = (uint8_t *)dst; const uint16_t *s = (uint16_t *)src; end = s + src_size/2; while(s < end) { register uint16_t bgr; bgr = *s++; #ifdef WORDS_BIGENDIAN *d++ = 0; *d++ = (bgr&0x1F)<<3; *d++ = (bgr&0x7E0)>>3; *d++ = (bgr&0xF800)>>8; #else *d++ = (bgr&0xF800)>>8; *d++ = (bgr&0x7E0)>>3; *d++ = (bgr&0x1F)<<3; *d++ = 0; #endif } }


static void ir2_decode_plane_inter(Ir2Context *ctx, int width, int height, uint8_t *dst, int stride, const uint8_t *table) { int j; int out = 0; int c; int t; for (j = 0; j < height; j++){ out = 0; while (out < width){ c = ir2_get_code(&ctx->gb); if(c > 0x80) { /* we have a skip */ c -= 0x80; out += c * 2; } else { /* add two deltas from table */ t = dst[out] + (table[c * 2] - 128); CLAMP_TO_BYTE(t); dst[out] = t; out++; t = dst[out] + (table[(c * 2) + 1] - 128); CLAMP_TO_BYTE(t); dst[out] = t; out++; } } dst += stride; } }


static int get_video_frame(VideoState *is, AVFrame *frame, int64_t *pts, AVPacket *pkt, int *serial) { int got_picture; if (packet_queue_get(&is->videoq, pkt, 1, serial) < 0) return -1; if (pkt->data == flush_pkt.data) { avcodec_flush_buffers(is->video_st->codec); SDL_LockMutex(is->pictq_mutex); // Make sure there are no long delay timers (ideally we should just flush the queue but that's harder) while (is->pictq_size && !is->videoq.abort_request) { SDL_CondWait(is->pictq_cond, is->pictq_mutex); } is->video_current_pos = -1; is->frame_last_pts = AV_NOPTS_VALUE; is->frame_last_duration = 0; is->frame_timer = (double)av_gettime() / 1000000.0; is->frame_last_dropped_pts = AV_NOPTS_VALUE; SDL_UnlockMutex(is->pictq_mutex); return 0; } if(avcodec_decode_video2(is->video_st->codec, frame, &got_picture, pkt) < 0) return 0; if (got_picture) { int ret = 1; if (decoder_reorder_pts == -1) { *pts = av_frame_get_best_effort_timestamp(frame); } else if (decoder_reorder_pts) { *pts = frame->pkt_pts; } else { *pts = frame->pkt_dts; } if (*pts == AV_NOPTS_VALUE) { *pts = 0; } if (framedrop>0 || (framedrop && get_master_sync_type(is) != AV_SYNC_VIDEO_MASTER)) { SDL_LockMutex(is->pictq_mutex); if (is->frame_last_pts != AV_NOPTS_VALUE && *pts) { double clockdiff = get_video_clock(is) - get_master_clock(is); double dpts = av_q2d(is->video_st->time_base) * *pts; double ptsdiff = dpts - is->frame_last_pts; if (!isnan(clockdiff) && fabs(clockdiff) < AV_NOSYNC_THRESHOLD && ptsdiff > 0 && ptsdiff < AV_NOSYNC_THRESHOLD && clockdiff + ptsdiff - is->frame_last_filter_delay < 0) { is->frame_last_dropped_pos = pkt->pos; is->frame_last_dropped_pts = dpts; is->frame_drops_early++; ret = 0; } } SDL_UnlockMutex(is->pictq_mutex); } return ret; } return 0; }


int ff_audio_rechunk_interleave(AVFormatContext *s, AVPacket *out, AVPacket *pkt, int flush, int (*get_packet)(AVFormatContext *, AVPacket *, AVPacket *, int), int (*compare_ts)(AVFormatContext *, AVPacket *, AVPacket *)) { int i; if (pkt) { AVStream *st = s->streams[pkt->stream_index]; AudioInterleaveContext *aic = st->priv_data; if (st->codec->codec_type == AVMEDIA_TYPE_AUDIO) { unsigned new_size = av_fifo_size(aic->fifo) + pkt->size; if (new_size > aic->fifo_size) { if (av_fifo_realloc2(aic->fifo, new_size) < 0) return -1; aic->fifo_size = new_size; } av_fifo_generic_write(aic->fifo, pkt->data, pkt->size, NULL); } else { // rewrite pts and dts to be decoded time line position pkt->pts = pkt->dts = aic->dts; aic->dts += pkt->duration; ff_interleave_add_packet(s, pkt, compare_ts); } pkt = NULL; } for (i = 0; i < s->nb_streams; i++) { AVStream *st = s->streams[i]; if (st->codec->codec_type == AVMEDIA_TYPE_AUDIO) { AVPacket new_pkt; while (ff_interleave_new_audio_packet(s, &new_pkt, i, flush)) ff_interleave_add_packet(s, &new_pkt, compare_ts); } } return get_packet(s, out, pkt, flush); }


static int aac_decode_frame_int(AVCodecContext *avctx, void *data, int *got_frame_ptr, GetBitContext *gb) { AACContext *ac = avctx->priv_data; ChannelElement *che = NULL, *che_prev = NULL; enum RawDataBlockType elem_type, elem_type_prev = TYPE_END; int err, elem_id; int samples = 0, multiplier, audio_found = 0, pce_found = 0; if (show_bits(gb, 12) == 0xfff) { if (parse_adts_frame_header(ac, gb) < 0) { av_log(avctx, AV_LOG_ERROR, "Error decoding AAC frame header.\n"); err = -1; goto fail; } if (ac->oc[1].m4ac.sampling_index > 12) { av_log(ac->avctx, AV_LOG_ERROR, "invalid sampling rate index %d\n", ac->oc[1].m4ac.sampling_index); err = -1; goto fail; } } ac->tags_mapped = 0; // parse while ((elem_type = get_bits(gb, 3)) != TYPE_END) { elem_id = get_bits(gb, 4); if (elem_type < TYPE_DSE) { if (!(che=get_che(ac, elem_type, elem_id))) { av_log(ac->avctx, AV_LOG_ERROR, "channel element %d.%d is not allocated\n", elem_type, elem_id); err = -1; goto fail; } samples = 1024; } switch (elem_type) { case TYPE_SCE: err = decode_ics(ac, &che->ch[0], gb, 0, 0); audio_found = 1; break; case TYPE_CPE: err = decode_cpe(ac, gb, che); audio_found = 1; break; case TYPE_CCE: err = decode_cce(ac, gb, che); break; case TYPE_LFE: err = decode_ics(ac, &che->ch[0], gb, 0, 0); audio_found = 1; break; case TYPE_DSE: err = skip_data_stream_element(ac, gb); break; case TYPE_PCE: { uint8_t layout_map[MAX_ELEM_ID*4][3]; int tags; push_output_configuration(ac); tags = decode_pce(avctx, &ac->oc[1].m4ac, layout_map, gb); if (tags < 0) { err = tags; break; } if (pce_found) { av_log(avctx, AV_LOG_ERROR, "Not evaluating a further program_config_element as this construct is dubious at best.\n"); pop_output_configuration(ac); } else { err = output_configure(ac, layout_map, tags, 0, OC_TRIAL_PCE); if (!err) ac->oc[1].m4ac.chan_config = 0; pce_found = 1; } break; } case TYPE_FIL: if (elem_id == 15) elem_id += get_bits(gb, 8) - 1; if (get_bits_left(gb) < 8 * elem_id) { av_log(avctx, AV_LOG_ERROR, overread_err); err = -1; goto fail; } while (elem_id > 0) elem_id -= decode_extension_payload(ac, gb, elem_id, che_prev, elem_type_prev); err = 0; /* FIXME */ break; default: err = -1; /* should not happen, but keeps compiler happy */ break; } che_prev = che; elem_type_prev = elem_type; if (err) goto fail; if (get_bits_left(gb) < 3) { av_log(avctx, AV_LOG_ERROR, overread_err); err = -1; goto fail; } } spectral_to_sample(ac); multiplier = (ac->oc[1].m4ac.sbr == 1) ? ac->oc[1].m4ac.ext_sample_rate > ac->oc[1].m4ac.sample_rate : 0; samples <<= multiplier; if (samples) { /* get output buffer */ ac->frame.nb_samples = samples; if ((err = avctx->get_buffer(avctx, &ac->frame)) < 0) { av_log(avctx, AV_LOG_ERROR, "get_buffer() failed\n"); err = -1; goto fail; } if (avctx->sample_fmt == AV_SAMPLE_FMT_FLT) ac->fmt_conv.float_interleave((float *)ac->frame.data[0], (const float **)ac->output_data, samples, avctx->channels); else ac->fmt_conv.float_to_int16_interleave((int16_t *)ac->frame.data[0], (const float **)ac->output_data, samples, avctx->channels); *(AVFrame *)data = ac->frame; } *got_frame_ptr = !!samples; if (ac->oc[1].status && audio_found) { avctx->sample_rate = ac->oc[1].m4ac.sample_rate << multiplier; avctx->frame_size = samples; ac->oc[1].status = OC_LOCKED; } return 0; fail: pop_output_configuration(ac); return err; }


static void musicpal_init(MachineState *machine) { const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; ARMCPU *cpu; qemu_irq pic[32]; DeviceState *dev; DeviceState *i2c_dev; DeviceState *lcd_dev; DeviceState *key_dev; DeviceState *wm8750_dev; SysBusDevice *s; I2CBus *i2c; int i; unsigned long flash_size; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); if (!cpu_model) { cpu_model = "arm926"; } cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); if (!cpu) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } /* For now we use a fixed - the original - RAM size */ memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE); memory_region_add_subregion(address_space_mem, 0, ram); memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, &error_fatal); memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); for (i = 0; i < 32; i++) { pic[i] = qdev_get_gpio_in(dev, i); } sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], pic[MP_TIMER4_IRQ], NULL); if (serial_hds[0]) { serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN); } if (serial_hds[1]) { serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN); } /* Register flash */ dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { BlockBackend *blk = blk_by_legacy_dinfo(dinfo); flash_size = blk_getlength(blk); if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && flash_size != 32*1024*1024) { fprintf(stderr, "Invalid flash image size\n"); exit(1); } /* * The original U-Boot accesses the flash at 0xFE000000 instead of * 0xFF800000 (if there is 8 MB flash). So remap flash access if the * image is smaller than 32 MB. */ #ifdef TARGET_WORDS_BIGENDIAN pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, "musicpal.flash", flash_size, blk, 0x10000, (flash_size + 0xffff) >> 16, MP_FLASH_SIZE_MAX / flash_size, 2, 0x00BF, 0x236D, 0x0000, 0x0000, 0x5555, 0x2AAA, 1); #else pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, "musicpal.flash", flash_size, blk, 0x10000, (flash_size + 0xffff) >> 16, MP_FLASH_SIZE_MAX / flash_size, 2, 0x00BF, 0x236D, 0x0000, 0x0000, 0x5555, 0x2AAA, 0); #endif } sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); qemu_check_nic_model(&nd_table[0], "mv88w8618"); dev = qdev_create(NULL, TYPE_MV88W8618_ETH); qdev_set_nic_properties(dev, &nd_table[0]); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, pic[MP_GPIO_IRQ]); i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); /* I2C read data */ qdev_connect_gpio_out(i2c_dev, 0, qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); /* I2C data */ qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); /* I2C clock */ qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); for (i = 0; i < 3; i++) { qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); } for (i = 0; i < 4; i++) { qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); } for (i = 4; i < 8; i++) { qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); } wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR); dev = qdev_create(NULL, "mv88w8618_audio"); s = SYS_BUS_DEVICE(dev); qdev_prop_set_ptr(dev, "wm8750", wm8750_dev); qdev_init_nofail(dev); sysbus_mmio_map(s, 0, MP_AUDIO_BASE); sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; musicpal_binfo.kernel_filename = kernel_filename; musicpal_binfo.kernel_cmdline = kernel_cmdline; musicpal_binfo.initrd_filename = initrd_filename; arm_load_kernel(cpu, &musicpal_binfo); }


void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) { int i, fpus, fptag, nb_xmm_regs; floatx80 tmp; target_ulong addr; /* The operand must be 16 byte aligned */ if (ptr & 0xf) { raise_exception(env, EXCP0D_GPF); } env->fpuc = cpu_lduw_data(env, ptr); fpus = cpu_lduw_data(env, ptr + 2); fptag = cpu_lduw_data(env, ptr + 4); env->fpstt = (fpus >> 11) & 7; env->fpus = fpus & ~0x3800; fptag ^= 0xff; for (i = 0; i < 8; i++) { env->fptags[i] = ((fptag >> i) & 1); } addr = ptr + 0x20; for (i = 0; i < 8; i++) { tmp = helper_fldt(env, addr); ST(i) = tmp; addr += 16; } if (env->cr[4] & CR4_OSFXSR_MASK) { /* XXX: finish it */ env->mxcsr = cpu_ldl_data(env, ptr + 0x18); /* cpu_ldl_data(env, ptr + 0x1c); */ if (env->hflags & HF_CS64_MASK) { nb_xmm_regs = 16; } else { nb_xmm_regs = 8; } addr = ptr + 0xa0; /* Fast FXRESTORE leaves out the XMM registers */ if (!(env->efer & MSR_EFER_FFXSR) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) { for (i = 0; i < nb_xmm_regs; i++) { env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr); env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8); addr += 16; } } } }


static int fill_default_ref_list(H264Context *h){ MpegEncContext * const s = &h->s; int i; int smallest_poc_greater_than_current = -1; Picture sorted_short_ref[32]; if(h->slice_type==B_TYPE){ int out_i; int limit= -1; /* sort frame according to poc in B slice */ for(out_i=0; out_i<h->short_ref_count; out_i++){ int best_i=-1; int best_poc=INT_MAX; for(i=0; i<h->short_ref_count; i++){ const int poc= h->short_ref[i]->poc; if(poc > limit && poc < best_poc){ best_poc= poc; best_i= i; } } assert(best_i != -1); limit= best_poc; sorted_short_ref[out_i]= *h->short_ref[best_i]; tprintf("sorted poc: %d->%d poc:%d fn:%d\n", best_i, out_i, sorted_short_ref[out_i].poc, sorted_short_ref[out_i].frame_num); if (-1 == smallest_poc_greater_than_current) { if (h->short_ref[best_i]->poc >= s->current_picture_ptr->poc) { smallest_poc_greater_than_current = out_i; } } } } if(s->picture_structure == PICT_FRAME){ if(h->slice_type==B_TYPE){ int list; tprintf("current poc: %d, smallest_poc_greater_than_current: %d\n", s->current_picture_ptr->poc, smallest_poc_greater_than_current); // find the largest poc for(list=0; list<2; list++){ int index = 0; int j= -99; int step= list ? -1 : 1; for(i=0; i<h->short_ref_count && index < h->ref_count[list]; i++, j+=step) { while(j<0 || j>= h->short_ref_count){ if(j != -99 && step == (list ? -1 : 1)) return -1; step = -step; j= smallest_poc_greater_than_current + (step>>1); } if(sorted_short_ref[j].reference != 3) continue; h->default_ref_list[list][index ]= sorted_short_ref[j]; h->default_ref_list[list][index++].pic_id= sorted_short_ref[j].frame_num; } for(i = 0; i < 16 && index < h->ref_count[ list ]; i++){ if(h->long_ref[i] == NULL) continue; if(h->long_ref[i]->reference != 3) continue; h->default_ref_list[ list ][index ]= *h->long_ref[i]; h->default_ref_list[ list ][index++].pic_id= i;; } if(list && (smallest_poc_greater_than_current<=0 || smallest_poc_greater_than_current>=h->short_ref_count) && (1 < index)){ // swap the two first elements of L1 when // L0 and L1 are identical Picture temp= h->default_ref_list[1][0]; h->default_ref_list[1][0] = h->default_ref_list[1][1]; h->default_ref_list[1][1] = temp; } if(index < h->ref_count[ list ]) memset(&h->default_ref_list[list][index], 0, sizeof(Picture)*(h->ref_count[ list ] - index)); } }else{ int index=0; for(i=0; i<h->short_ref_count; i++){ if(h->short_ref[i]->reference != 3) continue; //FIXME refernce field shit h->default_ref_list[0][index ]= *h->short_ref[i]; h->default_ref_list[0][index++].pic_id= h->short_ref[i]->frame_num; } for(i = 0; i < 16; i++){ if(h->long_ref[i] == NULL) continue; if(h->long_ref[i]->reference != 3) continue; h->default_ref_list[0][index ]= *h->long_ref[i]; h->default_ref_list[0][index++].pic_id= i;; } if(index < h->ref_count[0]) memset(&h->default_ref_list[0][index], 0, sizeof(Picture)*(h->ref_count[0] - index)); } }else{ //FIELD if(h->slice_type==B_TYPE){ }else{ //FIXME second field balh } } #ifdef TRACE for (i=0; i<h->ref_count[0]; i++) { tprintf("List0: %s fn:%d 0x%p\n", (h->default_ref_list[0][i].long_ref ? "LT" : "ST"), h->default_ref_list[0][i].pic_id, h->default_ref_list[0][i].data[0]); } if(h->slice_type==B_TYPE){ for (i=0; i<h->ref_count[1]; i++) { tprintf("List1: %s fn:%d 0x%p\n", (h->default_ref_list[1][i].long_ref ? "LT" : "ST"), h->default_ref_list[1][i].pic_id, h->default_ref_list[0][i].data[0]); } } #endif return 0; }


target_ulong helper_rdhwr_cc(CPUMIPSState *env) { check_hwrena(env, 2); #ifdef CONFIG_USER_ONLY return env->CP0_Count; #else return (int32_t)cpu_mips_get_count(env); #endif }


void helper_rfci(CPUPPCState *env) { do_rfi(env, env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1, ~((target_ulong)0x3FFF0000), 0); }


static void gen_nabso(DisasContext *ctx) { int l1 = gen_new_label(); int l2 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); gen_set_label(l2); /* nabs never overflows */ tcg_gen_movi_tl(cpu_ov, 0); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); }


static coroutine_fn int cow_co_read(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, int nb_sectors) { int ret; BDRVCowState *s = bs->opaque; qemu_co_mutex_lock(&s->lock); ret = cow_read(bs, sector_num, buf, nb_sectors); qemu_co_mutex_unlock(&s->lock); return ret; }


static inline uint32_t ucf64_stoi(float32 s) { union { uint32_t i; float32 s; } v; v.s = s; return v.i; }


static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) { AHCIPortRegs *pr = &s->dev[port].port_regs; DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); switch (offset) { case PORT_LST_ADDR: pr->lst_addr = val; break; case PORT_LST_ADDR_HI: pr->lst_addr_hi = val; break; case PORT_FIS_ADDR: pr->fis_addr = val; break; case PORT_FIS_ADDR_HI: pr->fis_addr_hi = val; break; case PORT_IRQ_STAT: pr->irq_stat &= ~val; ahci_check_irq(s); break; case PORT_IRQ_MASK: pr->irq_mask = val & 0xfdc000ff; ahci_check_irq(s); break; case PORT_CMD: pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); if (pr->cmd & PORT_CMD_START) { if (ahci_map_clb_address(&s->dev[port])) { pr->cmd |= PORT_CMD_LIST_ON; } else { error_report("AHCI: Failed to start DMA engine: " "bad command list buffer address"); } } if (pr->cmd & PORT_CMD_FIS_RX) { if (ahci_map_fis_address(&s->dev[port])) { pr->cmd |= PORT_CMD_FIS_ON; } else { error_report("AHCI: Failed to start FIS receive engine: " "bad FIS receive buffer address"); } } /* XXX usually the FIS would be pending on the bus here and issuing deferred until the OS enables FIS receival. Instead, we only submit it once - which works in most cases, but is a hack. */ if ((pr->cmd & PORT_CMD_FIS_ON) && !s->dev[port].init_d2h_sent) { ahci_init_d2h(&s->dev[port]); s->dev[port].init_d2h_sent = true; } check_cmd(s, port); break; case PORT_TFDATA: /* Read Only. */ break; case PORT_SIG: /* Read Only */ break; case PORT_SCR_STAT: /* Read Only */ break; case PORT_SCR_CTL: if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && ((val & AHCI_SCR_SCTL_DET) == 0)) { ahci_reset_port(s, port); } pr->scr_ctl = val; break; case PORT_SCR_ERR: pr->scr_err &= ~val; break; case PORT_SCR_ACT: /* RW1 */ pr->scr_act |= val; break; case PORT_CMD_ISSUE: pr->cmd_issue |= val; check_cmd(s, port); break; default: break; } }


static int do_write_compressed(BlockBackend *blk, char *buf, int64_t offset, int64_t count, int64_t *total) { int ret; if (count >> 9 > INT_MAX) { return -ERANGE; } ret = blk_write_compressed(blk, offset >> 9, (uint8_t *)buf, count >> 9); if (ret < 0) { return ret; } *total = count; return 1; }


void qdict_put_obj(QDict *qdict, const char *key, QObject *value) { unsigned int hash; QDictEntry *entry; hash = tdb_hash(key) % QDICT_HASH_SIZE; entry = qdict_find(qdict, key, hash); if (entry) { /* replace key's value */ qobject_decref(entry->value); entry->value = value; } else { /* allocate a new entry */ entry = alloc_entry(key, value); LIST_INSERT_HEAD(&qdict->table[hash], entry, next); } qdict->size++; }


static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type, uint64_t asc, int rw, bool exc) { int ilen = ILEN_LATER; uint64_t tec; tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46; DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec); if (!exc) { return; } /* Code accesses have an undefined ilc. */ if (rw == MMU_INST_FETCH) { ilen = 2; } trigger_access_exception(env, type, ilen, tec); }