int64_t qmp_query_migrate_cache_size(Error **errp) { return migrate_xbzrle_cache_size(); }


av_cold int MPV_common_init(MpegEncContext *s) { int y_size, c_size, yc_size, i, mb_array_size, mv_table_size, x, y, threads; if(s->codec_id == CODEC_ID_MPEG2VIDEO && !s->progressive_sequence) s->mb_height = (s->height + 31) / 32 * 2; else s->mb_height = (s->height + 15) / 16; if(s->avctx->pix_fmt == PIX_FMT_NONE){ av_log(s->avctx, AV_LOG_ERROR, "decoding to PIX_FMT_NONE is not supported.\n"); return -1; } if(s->avctx->thread_count > MAX_THREADS || (s->avctx->thread_count > s->mb_height && s->mb_height)){ av_log(s->avctx, AV_LOG_ERROR, "too many threads\n"); return -1; } if((s->width || s->height) && avcodec_check_dimensions(s->avctx, s->width, s->height)) return -1; dsputil_init(&s->dsp, s->avctx); ff_dct_common_init(s); s->flags= s->avctx->flags; s->flags2= s->avctx->flags2; s->mb_width = (s->width + 15) / 16; s->mb_stride = s->mb_width + 1; s->b8_stride = s->mb_width*2 + 1; s->b4_stride = s->mb_width*4 + 1; mb_array_size= s->mb_height * s->mb_stride; mv_table_size= (s->mb_height+2) * s->mb_stride + 1; /* set chroma shifts */ avcodec_get_chroma_sub_sample(s->avctx->pix_fmt,&(s->chroma_x_shift), &(s->chroma_y_shift) ); /* set default edge pos, will be overriden in decode_header if needed */ s->h_edge_pos= s->mb_width*16; s->v_edge_pos= s->mb_height*16; s->mb_num = s->mb_width * s->mb_height; s->block_wrap[0]= s->block_wrap[1]= s->block_wrap[2]= s->block_wrap[3]= s->b8_stride; s->block_wrap[4]= s->block_wrap[5]= s->mb_stride; y_size = s->b8_stride * (2 * s->mb_height + 1); c_size = s->mb_stride * (s->mb_height + 1); yc_size = y_size + 2 * c_size; /* convert fourcc to upper case */ s->codec_tag = ff_toupper4(s->avctx->codec_tag); s->stream_codec_tag = ff_toupper4(s->avctx->stream_codec_tag); s->avctx->coded_frame= (AVFrame*)&s->current_picture; FF_ALLOCZ_OR_GOTO(s->avctx, s->mb_index2xy, (s->mb_num+1)*sizeof(int), fail) //error ressilience code looks cleaner with this for(y=0; y<s->mb_height; y++){ for(x=0; x<s->mb_width; x++){ s->mb_index2xy[ x + y*s->mb_width ] = x + y*s->mb_stride; } } s->mb_index2xy[ s->mb_height*s->mb_width ] = (s->mb_height-1)*s->mb_stride + s->mb_width; //FIXME really needed? if (s->encoding) { /* Allocate MV tables */ FF_ALLOCZ_OR_GOTO(s->avctx, s->p_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->b_forw_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->b_back_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->b_bidir_forw_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->b_bidir_back_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->b_direct_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail) s->p_mv_table = s->p_mv_table_base + s->mb_stride + 1; s->b_forw_mv_table = s->b_forw_mv_table_base + s->mb_stride + 1; s->b_back_mv_table = s->b_back_mv_table_base + s->mb_stride + 1; s->b_bidir_forw_mv_table= s->b_bidir_forw_mv_table_base + s->mb_stride + 1; s->b_bidir_back_mv_table= s->b_bidir_back_mv_table_base + s->mb_stride + 1; s->b_direct_mv_table = s->b_direct_mv_table_base + s->mb_stride + 1; if(s->msmpeg4_version){ FF_ALLOCZ_OR_GOTO(s->avctx, s->ac_stats, 2*2*(MAX_LEVEL+1)*(MAX_RUN+1)*2*sizeof(int), fail); } FF_ALLOCZ_OR_GOTO(s->avctx, s->avctx->stats_out, 256, fail); /* Allocate MB type table */ FF_ALLOCZ_OR_GOTO(s->avctx, s->mb_type , mb_array_size * sizeof(uint16_t), fail) //needed for encoding FF_ALLOCZ_OR_GOTO(s->avctx, s->lambda_table, mb_array_size * sizeof(int), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->q_intra_matrix , 64*32 * sizeof(int), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->q_inter_matrix , 64*32 * sizeof(int), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->q_intra_matrix16, 64*32*2 * sizeof(uint16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->q_inter_matrix16, 64*32*2 * sizeof(uint16_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->input_picture, MAX_PICTURE_COUNT * sizeof(Picture*), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->reordered_input_picture, MAX_PICTURE_COUNT * sizeof(Picture*), fail) if(s->avctx->noise_reduction){ FF_ALLOCZ_OR_GOTO(s->avctx, s->dct_offset, 2 * 64 * sizeof(uint16_t), fail) } } FF_ALLOCZ_OR_GOTO(s->avctx, s->picture, MAX_PICTURE_COUNT * sizeof(Picture), fail) for(i = 0; i < MAX_PICTURE_COUNT; i++) { avcodec_get_frame_defaults((AVFrame *)&s->picture[i]); } FF_ALLOCZ_OR_GOTO(s->avctx, s->error_status_table, mb_array_size*sizeof(uint8_t), fail) if(s->codec_id==CODEC_ID_MPEG4 || (s->flags & CODEC_FLAG_INTERLACED_ME)){ /* interlaced direct mode decoding tables */ for(i=0; i<2; i++){ int j, k; for(j=0; j<2; j++){ for(k=0; k<2; k++){ FF_ALLOCZ_OR_GOTO(s->avctx, s->b_field_mv_table_base[i][j][k], mv_table_size * 2 * sizeof(int16_t), fail) s->b_field_mv_table[i][j][k] = s->b_field_mv_table_base[i][j][k] + s->mb_stride + 1; } FF_ALLOCZ_OR_GOTO(s->avctx, s->b_field_select_table [i][j], mb_array_size * 2 * sizeof(uint8_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->p_field_mv_table_base[i][j], mv_table_size * 2 * sizeof(int16_t), fail) s->p_field_mv_table[i][j] = s->p_field_mv_table_base[i][j]+ s->mb_stride + 1; } FF_ALLOCZ_OR_GOTO(s->avctx, s->p_field_select_table[i], mb_array_size * 2 * sizeof(uint8_t), fail) } } if (s->out_format == FMT_H263) { /* ac values */ FF_ALLOCZ_OR_GOTO(s->avctx, s->ac_val_base, yc_size * sizeof(int16_t) * 16, fail); s->ac_val[0] = s->ac_val_base + s->b8_stride + 1; s->ac_val[1] = s->ac_val_base + y_size + s->mb_stride + 1; s->ac_val[2] = s->ac_val[1] + c_size; /* cbp values */ FF_ALLOCZ_OR_GOTO(s->avctx, s->coded_block_base, y_size, fail); s->coded_block= s->coded_block_base + s->b8_stride + 1; /* cbp, ac_pred, pred_dir */ FF_ALLOCZ_OR_GOTO(s->avctx, s->cbp_table , mb_array_size * sizeof(uint8_t), fail) FF_ALLOCZ_OR_GOTO(s->avctx, s->pred_dir_table, mb_array_size * sizeof(uint8_t), fail) } if (s->h263_pred || s->h263_plus || !s->encoding) { /* dc values */ //MN: we need these for error resilience of intra-frames FF_ALLOCZ_OR_GOTO(s->avctx, s->dc_val_base, yc_size * sizeof(int16_t), fail); s->dc_val[0] = s->dc_val_base + s->b8_stride + 1; s->dc_val[1] = s->dc_val_base + y_size + s->mb_stride + 1; s->dc_val[2] = s->dc_val[1] + c_size; for(i=0;i<yc_size;i++) s->dc_val_base[i] = 1024; } /* which mb is a intra block */ FF_ALLOCZ_OR_GOTO(s->avctx, s->mbintra_table, mb_array_size, fail); memset(s->mbintra_table, 1, mb_array_size); /* init macroblock skip table */ FF_ALLOCZ_OR_GOTO(s->avctx, s->mbskip_table, mb_array_size+2, fail); //Note the +1 is for a quicker mpeg4 slice_end detection FF_ALLOCZ_OR_GOTO(s->avctx, s->prev_pict_types, PREV_PICT_TYPES_BUFFER_SIZE, fail); s->parse_context.state= -1; if((s->avctx->debug&(FF_DEBUG_VIS_QP|FF_DEBUG_VIS_MB_TYPE)) || (s->avctx->debug_mv)){ s->visualization_buffer[0] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH); s->visualization_buffer[1] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH); s->visualization_buffer[2] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH); } s->context_initialized = 1; s->thread_context[0]= s; threads = s->avctx->thread_count; for(i=1; i<threads; i++){ s->thread_context[i]= av_malloc(sizeof(MpegEncContext)); memcpy(s->thread_context[i], s, sizeof(MpegEncContext)); } for(i=0; i<threads; i++){ if(init_duplicate_context(s->thread_context[i], s) < 0) goto fail; s->thread_context[i]->start_mb_y= (s->mb_height*(i ) + s->avctx->thread_count/2) / s->avctx->thread_count; s->thread_context[i]->end_mb_y = (s->mb_height*(i+1) + s->avctx->thread_count/2) / s->avctx->thread_count; } return 0; fail: MPV_common_end(s); return -1; }


static av_cold int aac_decode_init(AVCodecContext *avctx) { AACContext *ac = avctx->priv_data; int ret; ac->avctx = avctx; ac->oc[1].m4ac.sample_rate = avctx->sample_rate; aacdec_init(ac); #if USE_FIXED avctx->sample_fmt = AV_SAMPLE_FMT_S32P; #else avctx->sample_fmt = AV_SAMPLE_FMT_FLTP; #endif /* USE_FIXED */ if (avctx->extradata_size > 0) { if ((ret = decode_audio_specific_config(ac, ac->avctx, &ac->oc[1].m4ac, avctx->extradata, avctx->extradata_size * 8, 1)) < 0) return ret; } else { int sr, i; uint8_t layout_map[MAX_ELEM_ID*4][3]; int layout_map_tags; sr = sample_rate_idx(avctx->sample_rate); ac->oc[1].m4ac.sampling_index = sr; ac->oc[1].m4ac.channels = avctx->channels; ac->oc[1].m4ac.sbr = -1; ac->oc[1].m4ac.ps = -1; for (i = 0; i < FF_ARRAY_ELEMS(ff_mpeg4audio_channels); i++) if (ff_mpeg4audio_channels[i] == avctx->channels) break; if (i == FF_ARRAY_ELEMS(ff_mpeg4audio_channels)) { i = 0; } ac->oc[1].m4ac.chan_config = i; if (ac->oc[1].m4ac.chan_config) { int ret = set_default_channel_config(avctx, layout_map, &layout_map_tags, ac->oc[1].m4ac.chan_config); if (!ret) output_configure(ac, layout_map, layout_map_tags, OC_GLOBAL_HDR, 0); else if (avctx->err_recognition & AV_EF_EXPLODE) return AVERROR_INVALIDDATA; } } if (avctx->channels > MAX_CHANNELS) { av_log(avctx, AV_LOG_ERROR, "Too many channels\n"); return AVERROR_INVALIDDATA; } AAC_INIT_VLC_STATIC( 0, 304); AAC_INIT_VLC_STATIC( 1, 270); AAC_INIT_VLC_STATIC( 2, 550); AAC_INIT_VLC_STATIC( 3, 300); AAC_INIT_VLC_STATIC( 4, 328); AAC_INIT_VLC_STATIC( 5, 294); AAC_INIT_VLC_STATIC( 6, 306); AAC_INIT_VLC_STATIC( 7, 268); AAC_INIT_VLC_STATIC( 8, 510); AAC_INIT_VLC_STATIC( 9, 366); AAC_INIT_VLC_STATIC(10, 462); AAC_RENAME(ff_aac_sbr_init)(); #if USE_FIXED ac->fdsp = avpriv_alloc_fixed_dsp(avctx->flags & AV_CODEC_FLAG_BITEXACT); #else ac->fdsp = avpriv_float_dsp_alloc(avctx->flags & AV_CODEC_FLAG_BITEXACT); #endif /* USE_FIXED */ if (!ac->fdsp) { return AVERROR(ENOMEM); } ac->random_state = 0x1f2e3d4c; ff_aac_tableinit(); INIT_VLC_STATIC(&vlc_scalefactors, 7, FF_ARRAY_ELEMS(ff_aac_scalefactor_code), ff_aac_scalefactor_bits, sizeof(ff_aac_scalefactor_bits[0]), sizeof(ff_aac_scalefactor_bits[0]), ff_aac_scalefactor_code, sizeof(ff_aac_scalefactor_code[0]), sizeof(ff_aac_scalefactor_code[0]), 352); AAC_RENAME_32(ff_mdct_init)(&ac->mdct, 11, 1, 1.0 / RANGE15(1024.0)); AAC_RENAME_32(ff_mdct_init)(&ac->mdct_ld, 10, 1, 1.0 / RANGE15(512.0)); AAC_RENAME_32(ff_mdct_init)(&ac->mdct_small, 8, 1, 1.0 / RANGE15(128.0)); AAC_RENAME_32(ff_mdct_init)(&ac->mdct_ltp, 11, 0, RANGE15(-2.0)); #if !USE_FIXED ret = ff_imdct15_init(&ac->mdct480, 5); if (ret < 0) return ret; #endif // window initialization AAC_RENAME(ff_kbd_window_init)(AAC_RENAME(ff_aac_kbd_long_1024), 4.0, 1024); AAC_RENAME(ff_kbd_window_init)(AAC_RENAME(ff_aac_kbd_short_128), 6.0, 128); AAC_RENAME(ff_init_ff_sine_windows)(10); AAC_RENAME(ff_init_ff_sine_windows)( 9); AAC_RENAME(ff_init_ff_sine_windows)( 7); AAC_RENAME(cbrt_tableinit)(); return 0; }


PPC_OP(addic) { T1 = T0; T0 += PARAM(1); if (T0 < T1) { xer_ca = 1; } else { xer_ca = 0; } RETURN(); }


void qemu_update_position(QEMUFile *f, size_t size) { f->pos += size; }


static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) { int32_t disp21, disp16, disp12 __attribute__((unused)); uint16_t fn11; uint8_t opc, ra, rb, rc, fpfn, fn7, lit; bool islit; TCGv va, vb, vc, tmp; TCGv_i32 t32; ExitStatus ret; /* Decode all instruction fields */ opc = extract32(insn, 26, 6); ra = extract32(insn, 21, 5); rb = extract32(insn, 16, 5); rc = extract32(insn, 0, 5); islit = extract32(insn, 12, 1); lit = extract32(insn, 13, 8); disp21 = sextract32(insn, 0, 21); disp16 = sextract32(insn, 0, 16); disp12 = sextract32(insn, 0, 12); fn11 = extract32(insn, 5, 11); fpfn = extract32(insn, 5, 6); fn7 = extract32(insn, 5, 7); if (rb == 31 && !islit) { islit = true; lit = 0; } ret = NO_EXIT; switch (opc) { case 0x00: /* CALL_PAL */ ret = gen_call_pal(ctx, insn & 0x03ffffff); break; case 0x01: /* OPC01 */ goto invalid_opc; case 0x02: /* OPC02 */ goto invalid_opc; case 0x03: /* OPC03 */ goto invalid_opc; case 0x04: /* OPC04 */ goto invalid_opc; case 0x05: /* OPC05 */ goto invalid_opc; case 0x06: /* OPC06 */ goto invalid_opc; case 0x07: /* OPC07 */ goto invalid_opc; case 0x09: /* LDAH */ disp16 = (uint32_t)disp16 << 16; /* fall through */ case 0x08: /* LDA */ va = dest_gpr(ctx, ra); /* It's worth special-casing immediate loads. */ if (rb == 31) { tcg_gen_movi_i64(va, disp16); } else { tcg_gen_addi_i64(va, load_gpr(ctx, rb), disp16); } break; case 0x0A: /* LDBU */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: /* LDQ_U */ gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); break; case 0x0C: /* LDWU */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); break; case 0x0D: /* STW */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: /* STQ_U */ gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); break; case 0x10: vc = dest_gpr(ctx, rc); vb = load_gpr_lit(ctx, rb, lit, islit); if (ra == 31) { if (fn7 == 0x00) { /* Special case ADDL as SEXTL. */ tcg_gen_ext32s_i64(vc, vb); break; } if (fn7 == 0x29) { /* Special case SUBQ as NEGQ. */ tcg_gen_neg_i64(vc, vb); break; } } va = load_gpr(ctx, ra); switch (fn7) { case 0x00: /* ADDL */ tcg_gen_add_i64(vc, va, vb); tcg_gen_ext32s_i64(vc, vc); break; case 0x02: /* S4ADDL */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_add_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); tcg_temp_free(tmp); break; case 0x09: /* SUBL */ tcg_gen_sub_i64(vc, va, vb); tcg_gen_ext32s_i64(vc, vc); break; case 0x0B: /* S4SUBL */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_sub_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); tcg_temp_free(tmp); break; case 0x0F: /* CMPBGE */ gen_helper_cmpbge(vc, va, vb); break; case 0x12: /* S8ADDL */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_add_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); tcg_temp_free(tmp); break; case 0x1B: /* S8SUBL */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_sub_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); tcg_temp_free(tmp); break; case 0x1D: /* CMPULT */ tcg_gen_setcond_i64(TCG_COND_LTU, vc, va, vb); break; case 0x20: /* ADDQ */ tcg_gen_add_i64(vc, va, vb); break; case 0x22: /* S4ADDQ */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_add_i64(vc, tmp, vb); tcg_temp_free(tmp); break; case 0x29: /* SUBQ */ tcg_gen_sub_i64(vc, va, vb); break; case 0x2B: /* S4SUBQ */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_sub_i64(vc, tmp, vb); tcg_temp_free(tmp); break; case 0x2D: /* CMPEQ */ tcg_gen_setcond_i64(TCG_COND_EQ, vc, va, vb); break; case 0x32: /* S8ADDQ */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_add_i64(vc, tmp, vb); tcg_temp_free(tmp); break; case 0x3B: /* S8SUBQ */ tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_sub_i64(vc, tmp, vb); tcg_temp_free(tmp); break; case 0x3D: /* CMPULE */ tcg_gen_setcond_i64(TCG_COND_LEU, vc, va, vb); break; case 0x40: /* ADDL/V */ gen_helper_addlv(vc, cpu_env, va, vb); break; case 0x49: /* SUBL/V */ gen_helper_sublv(vc, cpu_env, va, vb); break; case 0x4D: /* CMPLT */ tcg_gen_setcond_i64(TCG_COND_LT, vc, va, vb); break; case 0x60: /* ADDQ/V */ gen_helper_addqv(vc, cpu_env, va, vb); break; case 0x69: /* SUBQ/V */ gen_helper_subqv(vc, cpu_env, va, vb); break; case 0x6D: /* CMPLE */ tcg_gen_setcond_i64(TCG_COND_LE, vc, va, vb); break; default: goto invalid_opc; } break; case 0x11: if (fn7 == 0x20) { if (rc == 31) { /* Special case BIS as NOP. */ break; } if (ra == 31) { /* Special case BIS as MOV. */ vc = dest_gpr(ctx, rc); if (islit) { tcg_gen_movi_i64(vc, lit); } else { tcg_gen_mov_i64(vc, load_gpr(ctx, rb)); } break; } } vc = dest_gpr(ctx, rc); vb = load_gpr_lit(ctx, rb, lit, islit); if (fn7 == 0x28 && ra == 31) { /* Special case ORNOT as NOT. */ tcg_gen_not_i64(vc, vb); break; } va = load_gpr(ctx, ra); switch (fn7) { case 0x00: /* AND */ tcg_gen_and_i64(vc, va, vb); break; case 0x08: /* BIC */ tcg_gen_andc_i64(vc, va, vb); break; case 0x14: /* CMOVLBS */ tmp = tcg_temp_new(); tcg_gen_andi_i64(tmp, va, 1); tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx), vb, load_gpr(ctx, rc)); tcg_temp_free(tmp); break; case 0x16: /* CMOVLBC */ tmp = tcg_temp_new(); tcg_gen_andi_i64(tmp, va, 1); tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx), vb, load_gpr(ctx, rc)); tcg_temp_free(tmp); break; case 0x20: /* BIS */ tcg_gen_or_i64(vc, va, vb); break; case 0x24: /* CMOVEQ */ tcg_gen_movcond_i64(TCG_COND_EQ, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x26: /* CMOVNE */ tcg_gen_movcond_i64(TCG_COND_NE, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x28: /* ORNOT */ tcg_gen_orc_i64(vc, va, vb); break; case 0x40: /* XOR */ tcg_gen_xor_i64(vc, va, vb); break; case 0x44: /* CMOVLT */ tcg_gen_movcond_i64(TCG_COND_LT, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x46: /* CMOVGE */ tcg_gen_movcond_i64(TCG_COND_GE, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x48: /* EQV */ tcg_gen_eqv_i64(vc, va, vb); break; case 0x61: /* AMASK */ REQUIRE_REG_31(ra); { uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; tcg_gen_andi_i64(vc, vb, ~amask); } break; case 0x64: /* CMOVLE */ tcg_gen_movcond_i64(TCG_COND_LE, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x66: /* CMOVGT */ tcg_gen_movcond_i64(TCG_COND_GT, vc, va, load_zero(ctx), vb, load_gpr(ctx, rc)); break; case 0x6C: /* IMPLVER */ REQUIRE_REG_31(ra); tcg_gen_movi_i64(vc, ctx->implver); break; default: goto invalid_opc; } break; case 0x12: vc = dest_gpr(ctx, rc); va = load_gpr(ctx, ra); switch (fn7) { case 0x02: /* MSKBL */ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x01); break; case 0x06: /* EXTBL */ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x01); break; case 0x0B: /* INSBL */ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x01); break; case 0x12: /* MSKWL */ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x16: /* EXTWL */ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x1B: /* INSWL */ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x22: /* MSKLL */ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x26: /* EXTLL */ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x2B: /* INSLL */ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x30: /* ZAP */ if (islit) { gen_zapnoti(vc, va, ~lit); } else { gen_helper_zap(vc, va, load_gpr(ctx, rb)); } break; case 0x31: /* ZAPNOT */ if (islit) { gen_zapnoti(vc, va, lit); } else { gen_helper_zapnot(vc, va, load_gpr(ctx, rb)); } break; case 0x32: /* MSKQL */ gen_msk_l(ctx, vc, va, rb, islit, lit, 0xff); break; case 0x34: /* SRL */ if (islit) { tcg_gen_shri_i64(vc, va, lit & 0x3f); } else { tmp = tcg_temp_new(); vb = load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_shr_i64(vc, va, tmp); tcg_temp_free(tmp); } break; case 0x36: /* EXTQL */ gen_ext_l(ctx, vc, va, rb, islit, lit, 0xff); break; case 0x39: /* SLL */ if (islit) { tcg_gen_shli_i64(vc, va, lit & 0x3f); } else { tmp = tcg_temp_new(); vb = load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_shl_i64(vc, va, tmp); tcg_temp_free(tmp); } break; case 0x3B: /* INSQL */ gen_ins_l(ctx, vc, va, rb, islit, lit, 0xff); break; case 0x3C: /* SRA */ if (islit) { tcg_gen_sari_i64(vc, va, lit & 0x3f); } else { tmp = tcg_temp_new(); vb = load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_sar_i64(vc, va, tmp); tcg_temp_free(tmp); } break; case 0x52: /* MSKWH */ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x57: /* INSWH */ gen_ins_h(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x5A: /* EXTWH */ gen_ext_h(ctx, vc, va, rb, islit, lit, 0x03); break; case 0x62: /* MSKLH */ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x67: /* INSLH */ gen_ins_h(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x6A: /* EXTLH */ gen_ext_h(ctx, vc, va, rb, islit, lit, 0x0f); break; case 0x72: /* MSKQH */ gen_msk_h(ctx, vc, va, rb, islit, lit, 0xff); break; case 0x77: /* INSQH */ gen_ins_h(ctx, vc, va, rb, islit, lit, 0xff); break; case 0x7A: /* EXTQH */ gen_ext_h(ctx, vc, va, rb, islit, lit, 0xff); break; default: goto invalid_opc; } break; case 0x13: vc = dest_gpr(ctx, rc); vb = load_gpr_lit(ctx, rb, lit, islit); va = load_gpr(ctx, ra); switch (fn7) { case 0x00: /* MULL */ tcg_gen_mul_i64(vc, va, vb); tcg_gen_ext32s_i64(vc, vc); break; case 0x20: /* MULQ */ tcg_gen_mul_i64(vc, va, vb); break; case 0x30: /* UMULH */ tmp = tcg_temp_new(); tcg_gen_mulu2_i64(tmp, vc, va, vb); tcg_temp_free(tmp); break; case 0x40: /* MULL/V */ gen_helper_mullv(vc, cpu_env, va, vb); break; case 0x60: /* MULQ/V */ gen_helper_mulqv(vc, cpu_env, va, vb); break; default: goto invalid_opc; } break; case 0x14: REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); vc = dest_fpr(ctx, rc); switch (fpfn) { /* fn11 & 0x3F */ case 0x04: /* ITOFS */ REQUIRE_REG_31(rb); t32 = tcg_temp_new_i32(); va = load_gpr(ctx, ra); tcg_gen_trunc_i64_i32(t32, va); gen_helper_memory_to_s(vc, t32); tcg_temp_free_i32(t32); break; case 0x0A: /* SQRTF */ REQUIRE_REG_31(ra); vb = load_fpr(ctx, rb); gen_helper_sqrtf(vc, cpu_env, vb); break; case 0x0B: /* SQRTS */ REQUIRE_REG_31(ra); gen_sqrts(ctx, rb, rc, fn11); break; case 0x14: /* ITOFF */ REQUIRE_REG_31(rb); t32 = tcg_temp_new_i32(); va = load_gpr(ctx, ra); tcg_gen_trunc_i64_i32(t32, va); gen_helper_memory_to_f(vc, t32); tcg_temp_free_i32(t32); break; case 0x24: /* ITOFT */ REQUIRE_REG_31(rb); va = load_gpr(ctx, ra); tcg_gen_mov_i64(vc, va); break; case 0x2A: /* SQRTG */ REQUIRE_REG_31(ra); vb = load_fpr(ctx, rb); gen_helper_sqrtg(vc, cpu_env, vb); break; case 0x02B: /* SQRTT */ REQUIRE_REG_31(ra); gen_sqrtt(ctx, rb, rc, fn11); break; default: goto invalid_opc; } break; case 0x15: /* VAX floating point */ /* XXX: rounding mode and trap are ignored (!) */ vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); va = load_fpr(ctx, ra); switch (fpfn) { /* fn11 & 0x3F */ case 0x00: /* ADDF */ gen_helper_addf(vc, cpu_env, va, vb); break; case 0x01: /* SUBF */ gen_helper_subf(vc, cpu_env, va, vb); break; case 0x02: /* MULF */ gen_helper_mulf(vc, cpu_env, va, vb); break; case 0x03: /* DIVF */ gen_helper_divf(vc, cpu_env, va, vb); break; case 0x1E: /* CVTDG -- TODO */ REQUIRE_REG_31(ra); goto invalid_opc; case 0x20: /* ADDG */ gen_helper_addg(vc, cpu_env, va, vb); break; case 0x21: /* SUBG */ gen_helper_subg(vc, cpu_env, va, vb); break; case 0x22: /* MULG */ gen_helper_mulg(vc, cpu_env, va, vb); break; case 0x23: /* DIVG */ gen_helper_divg(vc, cpu_env, va, vb); break; case 0x25: /* CMPGEQ */ gen_helper_cmpgeq(vc, cpu_env, va, vb); break; case 0x26: /* CMPGLT */ gen_helper_cmpglt(vc, cpu_env, va, vb); break; case 0x27: /* CMPGLE */ gen_helper_cmpgle(vc, cpu_env, va, vb); break; case 0x2C: /* CVTGF */ REQUIRE_REG_31(ra); gen_helper_cvtgf(vc, cpu_env, vb); break; case 0x2D: /* CVTGD -- TODO */ REQUIRE_REG_31(ra); goto invalid_opc; case 0x2F: /* CVTGQ */ REQUIRE_REG_31(ra); gen_helper_cvtgq(vc, cpu_env, vb); break; case 0x3C: /* CVTQF */ REQUIRE_REG_31(ra); gen_helper_cvtqf(vc, cpu_env, vb); break; case 0x3E: /* CVTQG */ REQUIRE_REG_31(ra); gen_helper_cvtqg(vc, cpu_env, vb); break; default: goto invalid_opc; } break; case 0x16: /* IEEE floating-point */ switch (fpfn) { /* fn11 & 0x3F */ case 0x00: /* ADDS */ gen_adds(ctx, ra, rb, rc, fn11); break; case 0x01: /* SUBS */ gen_subs(ctx, ra, rb, rc, fn11); break; case 0x02: /* MULS */ gen_muls(ctx, ra, rb, rc, fn11); break; case 0x03: /* DIVS */ gen_divs(ctx, ra, rb, rc, fn11); break; case 0x20: /* ADDT */ gen_addt(ctx, ra, rb, rc, fn11); break; case 0x21: /* SUBT */ gen_subt(ctx, ra, rb, rc, fn11); break; case 0x22: /* MULT */ gen_mult(ctx, ra, rb, rc, fn11); break; case 0x23: /* DIVT */ gen_divt(ctx, ra, rb, rc, fn11); break; case 0x24: /* CMPTUN */ gen_cmptun(ctx, ra, rb, rc, fn11); break; case 0x25: /* CMPTEQ */ gen_cmpteq(ctx, ra, rb, rc, fn11); break; case 0x26: /* CMPTLT */ gen_cmptlt(ctx, ra, rb, rc, fn11); break; case 0x27: /* CMPTLE */ gen_cmptle(ctx, ra, rb, rc, fn11); break; case 0x2C: REQUIRE_REG_31(ra); if (fn11 == 0x2AC || fn11 == 0x6AC) { /* CVTST */ gen_cvtst(ctx, rb, rc, fn11); } else { /* CVTTS */ gen_cvtts(ctx, rb, rc, fn11); } break; case 0x2F: /* CVTTQ */ REQUIRE_REG_31(ra); gen_cvttq(ctx, rb, rc, fn11); break; case 0x3C: /* CVTQS */ REQUIRE_REG_31(ra); gen_cvtqs(ctx, rb, rc, fn11); break; case 0x3E: /* CVTQT */ REQUIRE_REG_31(ra); gen_cvtqt(ctx, rb, rc, fn11); break; default: goto invalid_opc; } break; case 0x17: switch (fn11) { case 0x010: /* CVTLQ */ REQUIRE_REG_31(ra); vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); gen_cvtlq(vc, vb); break; case 0x020: /* CPYS */ if (rc == 31) { /* Special case CPYS as FNOP. */ } else { vc = dest_fpr(ctx, rc); va = load_fpr(ctx, ra); if (ra == rb) { /* Special case CPYS as FMOV. */ tcg_gen_mov_i64(vc, va); } else { vb = load_fpr(ctx, rb); gen_cpy_mask(vc, va, vb, 0, 0x8000000000000000ULL); } } break; case 0x021: /* CPYSN */ vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); va = load_fpr(ctx, ra); gen_cpy_mask(vc, va, vb, 1, 0x8000000000000000ULL); break; case 0x022: /* CPYSE */ vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); va = load_fpr(ctx, ra); gen_cpy_mask(vc, va, vb, 0, 0xFFF0000000000000ULL); break; case 0x024: /* MT_FPCR */ va = load_fpr(ctx, ra); gen_helper_store_fpcr(cpu_env, va); if (ctx->tb_rm == QUAL_RM_D) { /* Re-do the copy of the rounding mode to fp_status the next time we use dynamic rounding. */ ctx->tb_rm = -1; } break; case 0x025: /* MF_FPCR */ va = dest_fpr(ctx, ra); gen_helper_load_fpcr(va, cpu_env); break; case 0x02A: /* FCMOVEQ */ gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc); break; case 0x02B: /* FCMOVNE */ gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc); break; case 0x02C: /* FCMOVLT */ gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc); break; case 0x02D: /* FCMOVGE */ gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc); break; case 0x02E: /* FCMOVLE */ gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc); break; case 0x02F: /* FCMOVGT */ gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc); break; case 0x030: /* CVTQL */ REQUIRE_REG_31(ra); vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); gen_cvtql(vc, vb); break; case 0x130: /* CVTQL/V */ case 0x530: /* CVTQL/SV */ REQUIRE_REG_31(ra); /* ??? I'm pretty sure there's nothing that /sv needs to do that /v doesn't do. The only thing I can think is that /sv is a valid instruction merely for completeness in the ISA. */ vc = dest_fpr(ctx, rc); vb = load_fpr(ctx, rb); gen_helper_cvtql_v_input(cpu_env, vb); gen_cvtql(vc, vb); break; default: goto invalid_opc; } break; case 0x18: switch ((uint16_t)disp16) { case 0x0000: /* TRAPB */ /* No-op. */ break; case 0x0400: /* EXCB */ /* No-op. */ break; case 0x4000: /* MB */ /* No-op */ break; case 0x4400: /* WMB */ /* No-op */ break; case 0x8000: /* FETCH */ /* No-op */ break; case 0xA000: /* FETCH_M */ /* No-op */ break; case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); ret = EXIT_PC_STALE; } else { gen_helper_load_pcc(va, cpu_env); } break; case 0xE000: /* RC */ gen_rx(ra, 0); break; case 0xE800: /* ECB */ break; case 0xF000: /* RS */ gen_rx(ra, 1); break; case 0xF800: /* WH64 */ /* No-op */ break; default: goto invalid_opc; } break; case 0x19: /* HW_MFPR (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); va = dest_gpr(ctx, ra); ret = gen_mfpr(ctx, va, insn & 0xffff); break; #else goto invalid_opc; #endif case 0x1A: /* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch prediction stack action, which of course we don't implement. */ vb = load_gpr(ctx, rb); tcg_gen_andi_i64(cpu_pc, vb, ~3); if (ra != 31) { tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); } ret = EXIT_PC_UPDATED; break; case 0x1B: /* HW_LD (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); { TCGv addr = tcg_temp_new(); vb = load_gpr(ctx, rb); va = dest_gpr(ctx, ra); tcg_gen_addi_i64(addr, vb, disp12); switch ((insn >> 12) & 0xF) { case 0x0: /* Longword physical access (hw_ldl/p) */ gen_helper_ldl_phys(va, cpu_env, addr); break; case 0x1: /* Quadword physical access (hw_ldq/p) */ gen_helper_ldq_phys(va, cpu_env, addr); break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ gen_helper_ldl_l_phys(va, cpu_env, addr); break; case 0x3: /* Quadword physical access with lock (hw_ldq_l/p) */ gen_helper_ldq_l_phys(va, cpu_env, addr); break; case 0x4: /* Longword virtual PTE fetch (hw_ldl/v) */ goto invalid_opc; case 0x5: /* Quadword virtual PTE fetch (hw_ldq/v) */ goto invalid_opc; break; case 0x6: /* Incpu_ir[ra]id */ goto invalid_opc; case 0x7: /* Incpu_ir[ra]id */ goto invalid_opc; case 0x8: /* Longword virtual access (hw_ldl) */ goto invalid_opc; case 0x9: /* Quadword virtual access (hw_ldq) */ goto invalid_opc; case 0xA: /* Longword virtual access with protection check (hw_ldl/w) */ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL); break; case 0xB: /* Quadword virtual access with protection check (hw_ldq/w) */ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEQ); break; case 0xC: /* Longword virtual access with alt access mode (hw_ldl/a)*/ goto invalid_opc; case 0xD: /* Quadword virtual access with alt access mode (hw_ldq/a) */ goto invalid_opc; case 0xE: /* Longword virtual access with alternate access mode and protection checks (hw_ldl/wa) */ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL); break; case 0xF: /* Quadword virtual access with alternate access mode and protection checks (hw_ldq/wa) */ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEQ); break; } tcg_temp_free(addr); break; } #else goto invalid_opc; #endif case 0x1C: vc = dest_gpr(ctx, rc); if (fn7 == 0x70) { /* FTOIT */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_REG_31(rb); va = load_fpr(ctx, ra); tcg_gen_mov_i64(vc, va); break; } else if (fn7 == 0x78) { /* FTOIS */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_REG_31(rb); t32 = tcg_temp_new_i32(); va = load_fpr(ctx, ra); gen_helper_s_to_memory(t32, va); tcg_gen_ext_i32_i64(vc, t32); tcg_temp_free_i32(t32); break; } vb = load_gpr_lit(ctx, rb, lit, islit); switch (fn7) { case 0x00: /* SEXTB */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_REG_31(ra); tcg_gen_ext8s_i64(vc, vb); break; case 0x01: /* SEXTW */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_REG_31(ra); tcg_gen_ext16s_i64(vc, vb); break; case 0x30: /* CTPOP */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_REG_31(ra); gen_helper_ctpop(vc, vb); break; case 0x31: /* PERR */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_perr(vc, va, vb); break; case 0x32: /* CTLZ */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_REG_31(ra); gen_helper_ctlz(vc, vb); break; case 0x33: /* CTTZ */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_REG_31(ra); gen_helper_cttz(vc, vb); break; case 0x34: /* UNPKBW */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_REG_31(ra); gen_helper_unpkbw(vc, vb); break; case 0x35: /* UNPKBL */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_REG_31(ra); gen_helper_unpkbl(vc, vb); break; case 0x36: /* PKWB */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_REG_31(ra); gen_helper_pkwb(vc, vb); break; case 0x37: /* PKLB */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_REG_31(ra); gen_helper_pklb(vc, vb); break; case 0x38: /* MINSB8 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_minsb8(vc, va, vb); break; case 0x39: /* MINSW4 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_minsw4(vc, va, vb); break; case 0x3A: /* MINUB8 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_minub8(vc, va, vb); break; case 0x3B: /* MINUW4 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_minuw4(vc, va, vb); break; case 0x3C: /* MAXUB8 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_maxub8(vc, va, vb); break; case 0x3D: /* MAXUW4 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_maxuw4(vc, va, vb); break; case 0x3E: /* MAXSB8 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_maxsb8(vc, va, vb); break; case 0x3F: /* MAXSW4 */ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); va = load_gpr(ctx, ra); gen_helper_maxsw4(vc, va, vb); break; default: goto invalid_opc; } break; case 0x1D: /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); vb = load_gpr(ctx, rb); ret = gen_mtpr(ctx, vb, insn & 0xffff); break; #else goto invalid_opc; #endif case 0x1E: /* HW_RET (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); if (rb == 31) { /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our emulation PALcode, so continue to accept it. */ tmp = tcg_temp_new(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); gen_helper_hw_ret(cpu_env, tmp); tcg_temp_free(tmp); } else { gen_helper_hw_ret(cpu_env, load_gpr(ctx, rb)); } ret = EXIT_PC_UPDATED; break; #else goto invalid_opc; #endif case 0x1F: /* HW_ST (PALcode) */ #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); { TCGv addr = tcg_temp_new(); va = load_gpr(ctx, ra); vb = load_gpr(ctx, rb); tcg_gen_addi_i64(addr, vb, disp12); switch ((insn >> 12) & 0xF) { case 0x0: /* Longword physical access */ gen_helper_stl_phys(cpu_env, addr, va); break; case 0x1: /* Quadword physical access */ gen_helper_stq_phys(cpu_env, addr, va); break; case 0x2: /* Longword physical access with lock */ gen_helper_stl_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va); break; case 0x3: /* Quadword physical access with lock */ gen_helper_stq_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va); break; case 0x4: /* Longword virtual access */ goto invalid_opc; case 0x5: /* Quadword virtual access */ goto invalid_opc; case 0x6: /* Invalid */ goto invalid_opc; case 0x7: /* Invalid */ goto invalid_opc; case 0x8: /* Invalid */ goto invalid_opc; case 0x9: /* Invalid */ goto invalid_opc; case 0xA: /* Invalid */ goto invalid_opc; case 0xB: /* Invalid */ goto invalid_opc; case 0xC: /* Longword virtual access with alternate access mode */ goto invalid_opc; case 0xD: /* Quadword virtual access with alternate access mode */ goto invalid_opc; case 0xE: /* Invalid */ goto invalid_opc; case 0xF: /* Invalid */ goto invalid_opc; } tcg_temp_free(addr); break; } #else goto invalid_opc; #endif case 0x20: /* LDF */ gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); break; case 0x21: /* LDG */ gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); break; case 0x22: /* LDS */ gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); break; case 0x23: /* LDT */ gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); break; case 0x24: /* STF */ gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); break; case 0x25: /* STG */ gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); break; case 0x26: /* STS */ gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); break; case 0x27: /* STT */ gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); break; case 0x28: /* LDL */ gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); break; case 0x29: /* LDQ */ gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); break; case 0x2A: /* LDL_L */ gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); break; case 0x2B: /* LDQ_L */ gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); break; case 0x2C: /* STL */ gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); break; case 0x2D: /* STQ */ gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); break; case 0x2E: /* STL_C */ ret = gen_store_conditional(ctx, ra, rb, disp16, 0); break; case 0x2F: /* STQ_C */ ret = gen_store_conditional(ctx, ra, rb, disp16, 1); break; case 0x30: /* BR */ ret = gen_bdirect(ctx, ra, disp21); break; case 0x31: /* FBEQ */ ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); break; case 0x32: /* FBLT */ ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21); break; case 0x33: /* FBLE */ ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21); break; case 0x34: /* BSR */ ret = gen_bdirect(ctx, ra, disp21); break; case 0x35: /* FBNE */ ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21); break; case 0x36: /* FBGE */ ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21); break; case 0x37: /* FBGT */ ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21); break; case 0x38: /* BLBC */ ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1); break; case 0x39: /* BEQ */ ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0); break; case 0x3A: /* BLT */ ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0); break; case 0x3B: /* BLE */ ret = gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0); break; case 0x3C: /* BLBS */ ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1); break; case 0x3D: /* BNE */ ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0); break; case 0x3E: /* BGE */ ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0); break; case 0x3F: /* BGT */ ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0); break; invalid_opc: ret = gen_invalid(ctx); break; } return ret; }


CPUMIPSState *cpu_mips_init (const char *cpu_model) { CPUMIPSState *env; const mips_def_t *def; def = cpu_mips_find_by_name(cpu_model); if (!def) return NULL; env = qemu_mallocz(sizeof(CPUMIPSState)); env->cpu_model = def; cpu_exec_init(env); env->cpu_model_str = cpu_model; mips_tcg_init(); cpu_reset(env); qemu_init_vcpu(env); return env; }


static void *qpa_thread_out (void *arg) { PAVoiceOut *pa = arg; HWVoiceOut *hw = &pa->hw; int threshold; threshold = conf.divisor ? hw->samples / conf.divisor : 0; if (audio_pt_lock (&pa->pt, AUDIO_FUNC)) { return NULL; } for (;;) { int decr, to_mix, rpos; for (;;) { if (pa->done) { goto exit; } if (pa->live > threshold) { break; } if (audio_pt_wait (&pa->pt, AUDIO_FUNC)) { goto exit; } } decr = to_mix = pa->live; rpos = hw->rpos; if (audio_pt_unlock (&pa->pt, AUDIO_FUNC)) { return NULL; } while (to_mix) { int error; int chunk = audio_MIN (to_mix, hw->samples - rpos); struct st_sample *src = hw->mix_buf + rpos; hw->clip (pa->pcm_buf, src, chunk); if (pa_simple_write (pa->s, pa->pcm_buf, chunk << hw->info.shift, &error) < 0) { qpa_logerr (error, "pa_simple_write failed\n"); return NULL; } rpos = (rpos + chunk) % hw->samples; to_mix -= chunk; } if (audio_pt_lock (&pa->pt, AUDIO_FUNC)) { return NULL; } pa->rpos = rpos; pa->live -= decr; pa->decr += decr; } exit: audio_pt_unlock (&pa->pt, AUDIO_FUNC); return NULL; }


static void complete_collecting_data(Flash *s) { int i; s->cur_addr = 0; for (i = 0; i < get_addr_length(s); ++i) { s->cur_addr <<= 8; s->cur_addr |= s->data[i]; } if (get_addr_length(s) == 3) { s->cur_addr += s->ear * MAX_3BYTES_SIZE; } s->state = STATE_IDLE; switch (s->cmd_in_progress) { case DPP: case QPP: case PP: case PP4: case PP4_4: s->state = STATE_PAGE_PROGRAM; break; case READ: case READ4: case FAST_READ: case FAST_READ4: case DOR: case DOR4: case QOR: case QOR4: case DIOR: case DIOR4: case QIOR: case QIOR4: s->state = STATE_READ; break; case ERASE_4K: case ERASE4_4K: case ERASE_32K: case ERASE4_32K: case ERASE_SECTOR: case ERASE4_SECTOR: flash_erase(s, s->cur_addr, s->cmd_in_progress); break; case WRSR: switch (get_man(s)) { case MAN_SPANSION: s->quad_enable = !!(s->data[1] & 0x02); break; case MAN_MACRONIX: s->quad_enable = extract32(s->data[0], 6, 1); if (s->len > 1) { s->four_bytes_address_mode = extract32(s->data[1], 5, 1); } break; default: break; } if (s->write_enable) { s->write_enable = false; } break; case EXTEND_ADDR_WRITE: s->ear = s->data[0]; break; case WNVCR: s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); break; case WVCR: s->volatile_cfg = s->data[0]; break; case WEVCR: s->enh_volatile_cfg = s->data[0]; break; default: break; } }


static inline void gen_op_fpexception_im(int fsr_flags) { TCGv r_const; tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); r_const = tcg_const_i32(TT_FP_EXCP); tcg_gen_helper_0_1(raise_exception, r_const); tcg_temp_free(r_const); }


static int msf_probe(AVProbeData *p) { if (memcmp(p->buf, "MSF", 3)) return 0; if (AV_RB32(p->buf+8) <= 0) return 0; if (AV_RB32(p->buf+16) <= 0) return 0; return AVPROBE_SCORE_MAX / 3 * 2; }


static void check_exception(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { uint32_t mask, buf, len, event_len; uint64_t xinfo; sPAPREventLogEntry *event; struct rtas_error_log *hdr; if ((nargs < 6) || (nargs > 7) || nret != 1) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); return; } xinfo = rtas_ld(args, 1); mask = rtas_ld(args, 2); buf = rtas_ld(args, 4); len = rtas_ld(args, 5); if (nargs == 7) { xinfo |= (uint64_t)rtas_ld(args, 6) << 32; } event = rtas_event_log_dequeue(mask); if (!event) { goto out_no_events; } hdr = event->data; event_len = be32_to_cpu(hdr->extended_length) + sizeof(*hdr); if (event_len < len) { len = event_len; } cpu_physical_memory_write(buf, event->data, len); rtas_st(rets, 0, RTAS_OUT_SUCCESS); g_free(event->data); g_free(event); /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if * there are still pending events to be fetched via check-exception. We * do the latter here, since our code relies on edge-triggered * interrupts. */ if (rtas_event_log_contains(mask)) { qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq)); } return; out_no_events: rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); }


static void raw_fd_pool_put(RawAIOCB *acb) { BDRVRawState *s = acb->common.bs->opaque; int i; for (i = 0; i < RAW_FD_POOL_SIZE; i++) { if (s->fd_pool[i] == acb->fd) { close(s->fd_pool[i]); s->fd_pool[i] = -1; } } }


static void test_redirector_rx(void) { int backend_sock[2], send_sock; char *cmdline; uint32_t ret = 0, len = 0; char send_buf[] = "Hello!!"; char sock_path0[] = "filter-redirector0.XXXXXX"; char sock_path1[] = "filter-redirector1.XXXXXX"; char *recv_buf; uint32_t size = sizeof(send_buf); size = htonl(size); ret = socketpair(PF_UNIX, SOCK_STREAM, 0, backend_sock); g_assert_cmpint(ret, !=, -1); ret = mkstemp(sock_path0); g_assert_cmpint(ret, !=, -1); ret = mkstemp(sock_path1); g_assert_cmpint(ret, !=, -1); cmdline = g_strdup_printf("-netdev socket,id=qtest-bn0,fd=%d " "-device rtl8139,netdev=qtest-bn0,id=qtest-e0 " "-chardev socket,id=redirector0,path=%s,server,nowait " "-chardev socket,id=redirector1,path=%s,server,nowait " "-chardev socket,id=redirector2,path=%s,nowait " "-object filter-redirector,id=qtest-f0,netdev=qtest-bn0," "queue=rx,indev=redirector0 " "-object filter-redirector,id=qtest-f1,netdev=qtest-bn0," "queue=rx,outdev=redirector2 " "-object filter-redirector,id=qtest-f2,netdev=qtest-bn0," "queue=rx,indev=redirector1 " , backend_sock[1], sock_path0, sock_path1, sock_path0); qtest_start(cmdline); g_free(cmdline); struct iovec iov[] = { { .iov_base = &size, .iov_len = sizeof(size), }, { .iov_base = send_buf, .iov_len = sizeof(send_buf), }, }; send_sock = unix_connect(sock_path1, NULL); g_assert_cmpint(send_sock, !=, -1); /* send a qmp command to guarantee that 'connected' is setting to true. */ qmp_discard_response("{ 'execute' : 'query-status'}"); ret = iov_send(send_sock, iov, 2, 0, sizeof(size) + sizeof(send_buf)); g_assert_cmpint(ret, ==, sizeof(send_buf) + sizeof(size)); close(send_sock); ret = qemu_recv(backend_sock[0], &len, sizeof(len), 0); g_assert_cmpint(ret, ==, sizeof(len)); len = ntohl(len); g_assert_cmpint(len, ==, sizeof(send_buf)); recv_buf = g_malloc(len); ret = qemu_recv(backend_sock[0], recv_buf, len, 0); g_assert_cmpstr(recv_buf, ==, send_buf); g_free(recv_buf); unlink(sock_path0); unlink(sock_path1); qtest_end(); }


static void cpu_openrisc_load_kernel(ram_addr_t ram_size, const char *kernel_filename, OpenRISCCPU *cpu) { long kernel_size; uint64_t elf_entry; hwaddr entry; if (kernel_filename && !qtest_enabled()) { kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, NULL, NULL, 1, EM_OPENRISC, 1, 0); entry = elf_entry; if (kernel_size < 0) { kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, NULL, NULL); } if (kernel_size < 0) { kernel_size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR, ram_size - KERNEL_LOAD_ADDR); entry = KERNEL_LOAD_ADDR; } if (kernel_size < 0) { fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n", kernel_filename); exit(1); } cpu->env.pc = entry; } }


static void configure_rtc_date_offset(const char *startdate, int legacy) { time_t rtc_start_date; struct tm tm; if (!strcmp(startdate, "now") && legacy) { rtc_date_offset = -1; } else { if (sscanf(startdate, "%d-%d-%dT%d:%d:%d", &tm.tm_year, &tm.tm_mon, &tm.tm_mday, &tm.tm_hour, &tm.tm_min, &tm.tm_sec) == 6) { /* OK */ } else if (sscanf(startdate, "%d-%d-%d", &tm.tm_year, &tm.tm_mon, &tm.tm_mday) == 3) { tm.tm_hour = 0; tm.tm_min = 0; tm.tm_sec = 0; } else { goto date_fail; } tm.tm_year -= 1900; tm.tm_mon--; rtc_start_date = mktimegm(&tm); if (rtc_start_date == -1) { date_fail: fprintf(stderr, "Invalid date format. Valid formats are:\n" "'2006-06-17T16:01:21' or '2006-06-17'\n"); exit(1); } rtc_date_offset = time(NULL) - rtc_start_date; } }


void ppc_slb_invalidate_all (CPUPPCState *env) { /* XXX: TODO */ tlb_flush(env, 1); }


int load_image_targphys(const char *filename, target_phys_addr_t addr, int max_sz) { FILE *f; size_t got; f = fopen(filename, "rb"); if (!f) return -1; got = fread_targphys(addr, max_sz, f); if (ferror(f)) { fclose(f); return -1; } fclose(f); return got; }


int gdbserver_start(int port) { gdbserver_fd = gdbserver_open(port); if (gdbserver_fd < 0) return -1; /* accept connections */ gdb_accept (NULL); return 0; }


CaptureVoiceOut *AUD_add_capture ( AudioState *s, audsettings_t *as, struct audio_capture_ops *ops, void *cb_opaque ) { CaptureVoiceOut *cap; struct capture_callback *cb; if (!s) { /* XXX suppress */ s = &glob_audio_state; } if (audio_validate_settings (as)) { dolog ("Invalid settings were passed when trying to add capture\n"); audio_print_settings (as); goto err0; } cb = audio_calloc (AUDIO_FUNC, 1, sizeof (*cb)); if (!cb) { dolog ("Could not allocate capture callback information, size %zu\n", sizeof (*cb)); goto err0; } cb->ops = *ops; cb->opaque = cb_opaque; cap = audio_pcm_capture_find_specific (s, as); if (cap) { LIST_INSERT_HEAD (&cap->cb_head, cb, entries); return cap; } else { HWVoiceOut *hw; CaptureVoiceOut *cap; cap = audio_calloc (AUDIO_FUNC, 1, sizeof (*cap)); if (!cap) { dolog ("Could not allocate capture voice, size %zu\n", sizeof (*cap)); goto err1; } hw = &cap->hw; LIST_INIT (&hw->sw_head); LIST_INIT (&cap->cb_head); /* XXX find a more elegant way */ hw->samples = 4096 * 4; hw->mix_buf = audio_calloc (AUDIO_FUNC, hw->samples, sizeof (st_sample_t)); if (!hw->mix_buf) { dolog ("Could not allocate capture mix buffer (%d samples)\n", hw->samples); goto err2; } audio_pcm_init_info (&hw->info, as); cap->buf = audio_calloc (AUDIO_FUNC, hw->samples, 1 << hw->info.shift); if (!cap->buf) { dolog ("Could not allocate capture buffer " "(%d samples, each %d bytes)\n", hw->samples, 1 << hw->info.shift); goto err3; } hw->clip = mixeng_clip [hw->info.nchannels == 2] [hw->info.sign] [hw->info.swap_endianness] [audio_bits_to_index (hw->info.bits)]; LIST_INSERT_HEAD (&s->cap_head, cap, entries); LIST_INSERT_HEAD (&cap->cb_head, cb, entries); hw = NULL; while ((hw = audio_pcm_hw_find_any_out (s, hw))) { audio_attach_capture (s, hw); } return cap; err3: qemu_free (cap->hw.mix_buf); err2: qemu_free (cap); err1: qemu_free (cb); err0: return NULL; } }


static int nbd_co_writev(BlockDriverState *bs, int64_t sector_num, int nb_sectors, QEMUIOVector *qiov) { BDRVNBDState *s = bs->opaque; return nbd_client_session_co_writev(&s->client, sector_num, nb_sectors, qiov); }


static void megasas_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { MegasasState *s = opaque; uint64_t frame_addr; uint32_t frame_count; int i; trace_megasas_mmio_writel(addr, val); switch (addr) { case MFI_IDB: if (val & MFI_FWINIT_ABORT) { /* Abort all pending cmds */ for (i = 0; i < s->fw_cmds; i++) { megasas_abort_command(&s->frames[i]); } } if (val & MFI_FWINIT_READY) { /* move to FW READY */ megasas_soft_reset(s); } if (val & MFI_FWINIT_MFIMODE) { /* discard MFIs */ } break; case MFI_OMSK: s->intr_mask = val; if (!megasas_intr_enabled(s) && !msix_enabled(&s->dev)) { trace_megasas_irq_lower(); qemu_irq_lower(s->dev.irq[0]); } if (megasas_intr_enabled(s)) { trace_megasas_intr_enabled(); } else { trace_megasas_intr_disabled(); } break; case MFI_ODCR0: s->doorbell = 0; if (s->producer_pa && megasas_intr_enabled(s)) { /* Update reply queue pointer */ trace_megasas_qf_update(s->reply_queue_head, s->busy); stl_le_phys(s->producer_pa, s->reply_queue_head); if (!msix_enabled(&s->dev)) { trace_megasas_irq_lower(); qemu_irq_lower(s->dev.irq[0]); } } break; case MFI_IQPH: /* Received high 32 bits of a 64 bit MFI frame address */ s->frame_hi = val; break; case MFI_IQPL: /* Received low 32 bits of a 64 bit MFI frame address */ case MFI_IQP: /* Received 32 bit MFI frame address */ frame_addr = (val & ~0x1F); /* Add possible 64 bit offset */ frame_addr |= ((uint64_t)s->frame_hi << 32); s->frame_hi = 0; frame_count = (val >> 1) & 0xF; megasas_handle_frame(s, frame_addr, frame_count); break; default: trace_megasas_mmio_invalid_writel(addr, val); break; } }


static int mpjpeg_read_packet(AVFormatContext *s, AVPacket *pkt) { int size; int ret; MPJPEGDemuxContext *mpjpeg = s->priv_data; if (mpjpeg->boundary == NULL) { mpjpeg->boundary = av_strdup("--"); mpjpeg->searchstr = av_strdup("\r\n--"); if (!mpjpeg->boundary || !mpjpeg->searchstr) { av_freep(&mpjpeg->boundary); av_freep(&mpjpeg->searchstr); return AVERROR(ENOMEM); } mpjpeg->searchstr_len = strlen(mpjpeg->searchstr); } ret = parse_multipart_header(s->pb, &size, mpjpeg->boundary, s); if (ret < 0) return ret; if (size > 0) { /* size has been provided to us in MIME header */ ret = av_get_packet(s->pb, pkt, size); } else { /* no size was given -- we read until the next boundary or end-of-file */ int remaining = 0, len; const int read_chunk = 2048; av_init_packet(pkt); pkt->data = NULL; pkt->size = 0; pkt->pos = avio_tell(s->pb); /* we may need to return as much as all we've read back to the buffer */ ffio_ensure_seekback(s->pb, read_chunk); while ((ret = av_append_packet(s->pb, pkt, read_chunk - remaining)) >= 0) { /* scan the new data */ len = ret + remaining; char *start = pkt->data + pkt->size - len; do { if (!memcmp(start, mpjpeg->searchstr, mpjpeg->searchstr_len)) { // got the boundary! rewind the stream avio_seek(s->pb, -(len-2), SEEK_CUR); pkt->size -= (len-2); return pkt->size; } len--; start++; } while (len >= mpjpeg->searchstr_len); remaining = len; } /* error or EOF occurred */ if (ret == AVERROR_EOF) { ret = pkt->size > 0 ? pkt->size : AVERROR_EOF; } else { av_packet_unref(pkt); } } return ret; }


static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd, int fr, int fs, int ft) { const char *opn = "flt3_arith"; switch (opc) { case OPC_ALNV_PS: check_cp1_64bitmode(ctx); { TCGv t0 = tcg_temp_local_new(); TCGv_i32 fp = tcg_temp_new_i32(); TCGv_i32 fph = tcg_temp_new_i32(); int l1 = gen_new_label(); int l2 = gen_new_label(); gen_load_gpr(t0, fr); tcg_gen_andi_tl(t0, t0, 0x7); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); gen_load_fpr32(fp, fs); gen_load_fpr32h(ctx, fph, fs); gen_store_fpr32(fp, fd); gen_store_fpr32h(ctx, fph, fd); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); tcg_temp_free(t0); #ifdef TARGET_WORDS_BIGENDIAN gen_load_fpr32(fp, fs); gen_load_fpr32h(ctx, fph, ft); gen_store_fpr32h(ctx, fp, fd); gen_store_fpr32(fph, fd); #else gen_load_fpr32h(ctx, fph, fs); gen_load_fpr32(fp, ft); gen_store_fpr32(fph, fd); gen_store_fpr32h(ctx, fp, fd); #endif gen_set_label(l2); tcg_temp_free_i32(fp); tcg_temp_free_i32(fph); } opn = "alnv.ps"; break; case OPC_MADD_S: check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); tcg_temp_free_i32(fp2); } opn = "madd.s"; break; case OPC_MADD_D: check_cop1x(ctx); check_cp1_registers(ctx, fd | fs | ft | fr); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "madd.d"; break; case OPC_MADD_PS: check_cp1_64bitmode(ctx); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "madd.ps"; break; case OPC_MSUB_S: check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); tcg_temp_free_i32(fp2); } opn = "msub.s"; break; case OPC_MSUB_D: check_cop1x(ctx); check_cp1_registers(ctx, fd | fs | ft | fr); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "msub.d"; break; case OPC_MSUB_PS: check_cp1_64bitmode(ctx); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "msub.ps"; break; case OPC_NMADD_S: check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); tcg_temp_free_i32(fp2); } opn = "nmadd.s"; break; case OPC_NMADD_D: check_cop1x(ctx); check_cp1_registers(ctx, fd | fs | ft | fr); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "nmadd.d"; break; case OPC_NMADD_PS: check_cp1_64bitmode(ctx); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "nmadd.ps"; break; case OPC_NMSUB_S: check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); tcg_temp_free_i32(fp2); } opn = "nmsub.s"; break; case OPC_NMSUB_D: check_cop1x(ctx); check_cp1_registers(ctx, fd | fs | ft | fr); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "nmsub.d"; break; case OPC_NMSUB_PS: check_cp1_64bitmode(ctx); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } opn = "nmsub.ps"; break; default: MIPS_INVAL(opn); generate_exception (ctx, EXCP_RI); return; } (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], fregnames[fs], fregnames[ft]); }


static void pc_compat_2_1(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); pc_compat_2_2(machine); pcms->enforce_aligned_dimm = false; smbios_uuid_encoded = false; x86_cpu_change_kvm_default("svm", NULL); }


qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out) { openpic_t *opp; int i, m; struct { const char *name; MemoryRegionOps const *ops; hwaddr start_addr; ram_addr_t size; } const list[] = { {"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, {"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, {"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, {"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, }; /* XXX: for now, only one CPU is supported */ if (nb_cpus != 1) return NULL; opp = g_malloc0(sizeof(openpic_t)); memory_region_init(&opp->mem, "openpic", 0x40000); for (i = 0; i < ARRAY_SIZE(list); i++) { memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp, list[i].name, list[i].size); memory_region_add_subregion(&opp->mem, list[i].start_addr, &opp->sub_io_mem[i]); } // isu_base &= 0xFFFC0000; opp->nb_cpus = nb_cpus; opp->max_irq = OPENPIC_MAX_IRQ; opp->irq_ipi0 = OPENPIC_IRQ_IPI0; opp->irq_tim0 = OPENPIC_IRQ_TIM0; /* Set IRQ types */ for (i = 0; i < OPENPIC_EXT_IRQ; i++) { opp->src[i].type = IRQ_EXTERNAL; } for (; i < OPENPIC_IRQ_TIM0; i++) { opp->src[i].type = IRQ_SPECIAL; } m = OPENPIC_IRQ_IPI0; for (; i < m; i++) { opp->src[i].type = IRQ_TIMER; } for (; i < OPENPIC_MAX_IRQ; i++) { opp->src[i].type = IRQ_INTERNAL; } for (i = 0; i < nb_cpus; i++) opp->dst[i].irqs = irqs[i]; opp->irq_out = irq_out; register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2, openpic_save, openpic_load, opp); qemu_register_reset(openpic_reset, opp); opp->irq_raise = openpic_irq_raise; opp->reset = openpic_reset; if (pmem) *pmem = &opp->mem; return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); }


void do_interrupt(CPUARMState *env) { uint32_t addr; uint32_t mask; int new_mode; uint32_t offset; if (IS_M(env)) { do_interrupt_v7m(env); return; } /* TODO: Vectored interrupt controller. */ switch (env->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; addr = 0x04; mask = CPSR_I; if (env->thumb) offset = 2; else offset = 4; break; case EXCP_SWI: if (semihosting_enabled) { /* Check for semihosting interrupt. */ if (env->thumb) { mask = lduw_code(env->regs[15] - 2) & 0xff; } else { mask = ldl_code(env->regs[15] - 4) & 0xffffff; } /* Only intercept calls from privileged modes, to provide some semblance of security. */ if (((mask == 0x123456 && !env->thumb) || (mask == 0xab && env->thumb)) && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { env->regs[0] = do_arm_semihosting(env); return; } } new_mode = ARM_CPU_MODE_SVC; addr = 0x08; mask = CPSR_I; /* The PC already points to the next instruction. */ offset = 0; break; case EXCP_BKPT: /* See if this is a semihosting syscall. */ if (env->thumb && semihosting_enabled) { mask = lduw_code(env->regs[15]) & 0xff; if (mask == 0xab && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { env->regs[15] += 2; env->regs[0] = do_arm_semihosting(env); return; } } /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: new_mode = ARM_CPU_MODE_ABT; addr = 0x0c; mask = CPSR_A | CPSR_I; offset = 4; break; case EXCP_DATA_ABORT: new_mode = ARM_CPU_MODE_ABT; addr = 0x10; mask = CPSR_A | CPSR_I; offset = 8; break; case EXCP_IRQ: new_mode = ARM_CPU_MODE_IRQ; addr = 0x18; /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; offset = 4; break; default: cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ if (env->cp15.c1_sys & (1 << 13)) { addr += 0xffff0000; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); /* Clear IT bits. */ env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; env->uncached_cpsr |= mask; env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; env->regs[14] = env->regs[15] + offset; env->regs[15] = addr; env->interrupt_request |= CPU_INTERRUPT_EXITTB; }


int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar) { CPUS390XState *env = &cpu->env; uint32_t fh; ZpciFib fib; S390PCIBusDevice *pbdev; uint32_t data; uint64_t cc = ZPCI_PCI_LS_OK; if (env->psw.mask & PSW_MASK_PSTATE) { program_interrupt(env, PGM_PRIVILEGED, 6); return 0; } fh = env->regs[r1] >> 32; if (fiba & 0x7) { program_interrupt(env, PGM_SPECIFICATION, 6); return 0; } pbdev = s390_pci_find_dev_by_fh(fh); if (!pbdev) { setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); return 0; } memset(&fib, 0, sizeof(fib)); stq_p(&fib.pba, pbdev->pba); stq_p(&fib.pal, pbdev->pal); stq_p(&fib.iota, pbdev->g_iota); stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); stq_p(&fib.fmb_addr, pbdev->fmb_addr); data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; stl_p(&fib.data, data); if (pbdev->fh & FH_MASK_ENABLE) { fib.fc |= 0x80; } if (pbdev->error_state) { fib.fc |= 0x40; } if (pbdev->lgstg_blocked) { fib.fc |= 0x20; } if (pbdev->g_iota) { fib.fc |= 0x10; } if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { return 0; } setcc(cpu, cc); return 0; }


static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { }


START_TEST(qint_from_int_test) { QInt *qi; const int value = -42; qi = qint_from_int(value); fail_unless(qi != NULL); fail_unless(qi->value == value); fail_unless(qi->base.refcnt == 1); fail_unless(qobject_type(QOBJECT(qi)) == QTYPE_QINT); // destroy doesn't exit yet g_free(qi); }


static int kvm_s390_store_adtl_status(S390CPU *cpu, hwaddr addr) { void *mem; hwaddr len = ADTL_SAVE_AREA_SIZE; mem = cpu_physical_memory_map(addr, &len, 1); if (!mem) { return -EFAULT; } if (len != ADTL_SAVE_AREA_SIZE) { cpu_physical_memory_unmap(mem, len, 1, 0); return -EFAULT; } memcpy(mem, &cpu->env.vregs, 512); cpu_physical_memory_unmap(mem, len, 1, len); return 0; }


int page_unprotect(target_ulong address, unsigned long pc, void *puc) { unsigned int page_index, prot, pindex; PageDesc *p, *p1; target_ulong host_start, host_end, addr; /* Technically this isn't safe inside a signal handler. However we know this only ever happens in a synchronous SEGV handler, so in practice it seems to be ok. */ mmap_lock(); host_start = address & qemu_host_page_mask; page_index = host_start >> TARGET_PAGE_BITS; p1 = page_find(page_index); if (!p1) { mmap_unlock(); return 0; } host_end = host_start + qemu_host_page_size; p = p1; prot = 0; for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { prot |= p->flags; p++; } /* if the page was really writable, then we change its protection back to writable */ if (prot & PAGE_WRITE_ORG) { pindex = (address - host_start) >> TARGET_PAGE_BITS; if (!(p1[pindex].flags & PAGE_WRITE)) { mprotect((void *)g2h(host_start), qemu_host_page_size, (prot & PAGE_BITS) | PAGE_WRITE); p1[pindex].flags |= PAGE_WRITE; /* and since the content will be modified, we must invalidate the corresponding translated code. */ tb_invalidate_phys_page(address, pc, puc); #ifdef DEBUG_TB_CHECK tb_invalidate_check(address); #endif mmap_unlock(); return 1; } } mmap_unlock(); return 0; }


static int mov_read_enda(MOVContext *c, ByteIOContext *pb, MOVAtom atom) { AVStream *st = c->fc->streams[c->fc->nb_streams-1]; int little_endian = get_be16(pb); dprintf(c->fc, "enda %d\n", little_endian); if (little_endian == 1) { switch (st->codec->codec_id) { case CODEC_ID_PCM_S24BE: st->codec->codec_id = CODEC_ID_PCM_S24LE; break; case CODEC_ID_PCM_S32BE: st->codec->codec_id = CODEC_ID_PCM_S32LE; break; case CODEC_ID_PCM_F32BE: st->codec->codec_id = CODEC_ID_PCM_F32LE; break; case CODEC_ID_PCM_F64BE: st->codec->codec_id = CODEC_ID_PCM_F64LE; break; default: break; } } return 0; }


static inline int decode_scalar(GetBitContext *gb, int k, int limit, int readsamplesize){ int x = get_unary_0_9(gb); if (x > 8) { /* RICE THRESHOLD */ /* use alternative encoding */ x = get_bits(gb, readsamplesize); } else { if (k >= limit) k = limit; if (k != 1) { int extrabits = show_bits(gb, k); /* multiply x by 2^k - 1, as part of their strange algorithm */ x = (x << k) - x; if (extrabits > 1) { x += extrabits - 1; skip_bits(gb, k); } else skip_bits(gb, k - 1); } } return x; }


static void opt_b_frames(const char *arg) { b_frames = atoi(arg); if (b_frames > FF_MAX_B_FRAMES) { fprintf(stderr, "\nCannot have more than %d B frames, increase FF_MAX_B_FRAMES.\n", FF_MAX_B_FRAMES); exit(1); } else if (b_frames < 1) { fprintf(stderr, "\nNumber of B frames must be higher than 0\n"); exit(1); } }


static av_cold int encode_init(AVCodecContext* avc_context) { theora_info t_info; theora_comment t_comment; ogg_packet o_packet; unsigned int offset; TheoraContext *h = avc_context->priv_data; /* Set up the theora_info struct */ theora_info_init( &t_info ); t_info.width = FFALIGN(avc_context->width, 16); t_info.height = FFALIGN(avc_context->height, 16); t_info.frame_width = avc_context->width; t_info.frame_height = avc_context->height; t_info.offset_x = 0; t_info.offset_y = avc_context->height & 0xf; /* Swap numerator and denominator as time_base in AVCodecContext gives the * time period between frames, but theora_info needs the framerate. */ t_info.fps_numerator = avc_context->time_base.den; t_info.fps_denominator = avc_context->time_base.num; if (avc_context->sample_aspect_ratio.num != 0) { t_info.aspect_numerator = avc_context->sample_aspect_ratio.num; t_info.aspect_denominator = avc_context->sample_aspect_ratio.den; } else { t_info.aspect_numerator = 1; t_info.aspect_denominator = 1; } t_info.colorspace = OC_CS_UNSPECIFIED; t_info.pixelformat = OC_PF_420; t_info.target_bitrate = avc_context->bit_rate; t_info.keyframe_frequency = avc_context->gop_size; t_info.keyframe_frequency_force = avc_context->gop_size; t_info.keyframe_mindistance = avc_context->keyint_min; t_info.quality = 0; t_info.quick_p = 1; t_info.dropframes_p = 0; t_info.keyframe_auto_p = 1; t_info.keyframe_data_target_bitrate = t_info.target_bitrate * 1.5; t_info.keyframe_auto_threshold = 80; t_info.noise_sensitivity = 1; t_info.sharpness = 0; /* Now initialise libtheora */ if (theora_encode_init( &(h->t_state), &t_info ) != 0) { av_log(avc_context, AV_LOG_ERROR, "theora_encode_init failed\n"); return -1; } /* Clear up theora_info struct */ theora_info_clear( &t_info ); /* Output first header packet consisting of theora header, comment, and tables. Each one is prefixed with a 16bit size, then they are concatenated together into ffmpeg's extradata. */ offset = 0; /* Header */ theora_encode_header( &(h->t_state), &o_packet ); if (concatenate_packet( &offset, avc_context, &o_packet ) != 0) { return -1; } /* Comment */ theora_comment_init( &t_comment ); theora_encode_comment( &t_comment, &o_packet ); if (concatenate_packet( &offset, avc_context, &o_packet ) != 0) { return -1; } /* Tables */ theora_encode_tables( &(h->t_state), &o_packet ); if (concatenate_packet( &offset, avc_context, &o_packet ) != 0) { return -1; } /* Clear up theora_comment struct */ theora_comment_clear( &t_comment ); /* Set up the output AVFrame */ avc_context->coded_frame= avcodec_alloc_frame(); return 0; }


static int frame_thread_init(AVCodecContext *avctx) { int thread_count = avctx->thread_count; AVCodec *codec = avctx->codec; AVCodecContext *src = avctx; FrameThreadContext *fctx; int i, err = 0; if (thread_count <= 1) { avctx->active_thread_type = 0; return 0; } avctx->thread_opaque = fctx = av_mallocz(sizeof(FrameThreadContext)); fctx->threads = av_mallocz(sizeof(PerThreadContext) * thread_count); pthread_mutex_init(&fctx->buffer_mutex, NULL); fctx->delaying = 1; for (i = 0; i < thread_count; i++) { AVCodecContext *copy = av_malloc(sizeof(AVCodecContext)); PerThreadContext *p = &fctx->threads[i]; pthread_mutex_init(&p->mutex, NULL); pthread_mutex_init(&p->progress_mutex, NULL); pthread_cond_init(&p->input_cond, NULL); pthread_cond_init(&p->progress_cond, NULL); pthread_cond_init(&p->output_cond, NULL); p->parent = fctx; p->avctx = copy; if (!copy) { err = AVERROR(ENOMEM); goto error; } *copy = *src; copy->thread_opaque = p; copy->pkt = &p->avpkt; if (!i) { src = copy; if (codec->init) err = codec->init(copy); update_context_from_thread(avctx, copy, 1); } else { copy->priv_data = av_malloc(codec->priv_data_size); if (!copy->priv_data) { err = AVERROR(ENOMEM); goto error; } memcpy(copy->priv_data, src->priv_data, codec->priv_data_size); copy->internal = av_malloc(sizeof(AVCodecInternal)); if (!copy->internal) { err = AVERROR(ENOMEM); goto error; } *(copy->internal) = *(src->internal); copy->internal->is_copy = 1; if (codec->init_thread_copy) err = codec->init_thread_copy(copy); } if (err) goto error; pthread_create(&p->thread, NULL, frame_worker_thread, p); } return 0; error: frame_thread_free(avctx, i+1); return err; }


static char *shorts2str(int16_t *sp, int count, const char *sep) { int i; char *ap, *ap0; if (!sep) sep = ", "; ap = av_malloc((5 + strlen(sep)) * count); if (!ap) return NULL; ap0 = ap; ap[0] = '\0'; for (i = 0; i < count; i++) { int l = snprintf(ap, 5 + strlen(sep), "%d%s", sp[i], sep); ap += l; } ap0[strlen(ap0) - strlen(sep)] = '\0'; return ap0; }


static int h264_set_parameter_from_sps(H264Context *h) { if (h->flags & CODEC_FLAG_LOW_DELAY || (h->sps.bitstream_restriction_flag && !h->sps.num_reorder_frames)) { if (h->avctx->has_b_frames > 1 || h->delayed_pic[0]) av_log(h->avctx, AV_LOG_WARNING, "Delayed frames seen. " "Reenabling low delay requires a codec flush.\n"); else h->low_delay = 1; if (h->avctx->has_b_frames < 2) h->avctx->has_b_frames = !h->low_delay; if (h->avctx->bits_per_raw_sample != h->sps.bit_depth_luma || h->cur_chroma_format_idc != h->sps.chroma_format_idc) { if (h->avctx->codec && h->avctx->codec->capabilities & CODEC_CAP_HWACCEL_VDPAU && (h->sps.bit_depth_luma != 8 || h->sps.chroma_format_idc > 1)) { av_log(h->avctx, AV_LOG_ERROR, "VDPAU decoding does not support video colorspace.\n"); return AVERROR_INVALIDDATA; if (h->sps.bit_depth_luma >= 8 && h->sps.bit_depth_luma <= 10) { h->avctx->bits_per_raw_sample = h->sps.bit_depth_luma; h->cur_chroma_format_idc = h->sps.chroma_format_idc; h->pixel_shift = h->sps.bit_depth_luma > 8; ff_h264dsp_init(&h->h264dsp, h->sps.bit_depth_luma, h->sps.chroma_format_idc); ff_h264chroma_init(&h->h264chroma, h->sps.bit_depth_chroma); ff_h264qpel_init(&h->h264qpel, h->sps.bit_depth_luma); ff_h264_pred_init(&h->hpc, h->avctx->codec_id, h->sps.bit_depth_luma, h->sps.chroma_format_idc); h->dsp.dct_bits = h->sps.bit_depth_luma > 8 ? 32 : 16; ff_dsputil_init(&h->dsp, h->avctx); ff_videodsp_init(&h->vdsp, h->sps.bit_depth_luma); } else { av_log(h->avctx, AV_LOG_ERROR, "Unsupported bit depth: %d\n", h->sps.bit_depth_luma); return AVERROR_INVALIDDATA; return 0;


static inline int array_roll(array_t* array,int index_to,int index_from,int count) { char* buf; char* from; char* to; int is; if(!array || index_to<0 || index_to>=array->next || index_from<0 || index_from>=array->next) return -1; if(index_to==index_from) return 0; is=array->item_size; from=array->pointer+index_from*is; to=array->pointer+index_to*is; buf=g_malloc(is*count); memcpy(buf,from,is*count); if(index_to<index_from) memmove(to+is*count,to,from-to); else memmove(from,from+is*count,to-from); memcpy(to,buf,is*count); free(buf); return 0; }


int ff_raw_video_read_header(AVFormatContext *s) { AVStream *st; FFRawVideoDemuxerContext *s1 = s->priv_data; AVRational framerate; int ret = 0; st = avformat_new_stream(s, NULL); if (!st) { ret = AVERROR(ENOMEM); goto fail; } st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = s->iformat->raw_codec_id; st->need_parsing = AVSTREAM_PARSE_FULL; if ((ret = av_parse_video_rate(&framerate, s1->framerate)) < 0) { av_log(s, AV_LOG_ERROR, "Could not parse framerate: %s.\n", s1->framerate); goto fail; } st->r_frame_rate = st->avg_frame_rate = framerate; avpriv_set_pts_info(st, 64, framerate.den, framerate.num); fail: return ret; }


static int mov_read_packet(AVFormatContext *s, AVPacket *pkt) { MOVContext *mov = s->priv_data; MOVStreamContext *sc; AVIndexEntry *sample; AVStream *st = NULL; int ret; mov->fc = s; retry: sample = mov_find_next_sample(s, &st); if (!sample) { mov->found_mdat = 0; if (!mov->next_root_atom) return AVERROR_EOF; avio_seek(s->pb, mov->next_root_atom, SEEK_SET); mov->next_root_atom = 0; if (mov_read_default(mov, s->pb, (MOVAtom){ AV_RL32("root"), INT64_MAX }) < 0 || url_feof(s->pb)) return AVERROR_EOF; av_dlog(s, "read fragments, offset 0x%"PRIx64"\n", avio_tell(s->pb)); goto retry; sc = st->priv_data; /* must be done just before reading, to avoid infinite loop on sample */ sc->current_sample++; if (st->discard != AVDISCARD_ALL) { if (avio_seek(sc->pb, sample->pos, SEEK_SET) != sample->pos) { av_log(mov->fc, AV_LOG_ERROR, "stream %d, offset 0x%"PRIx64": partial file\n", sc->ffindex, sample->pos); return AVERROR_INVALIDDATA; ret = av_get_packet(sc->pb, pkt, sample->size); if (ret < 0) return ret; if (sc->has_palette) { uint8_t *pal; pal = av_packet_new_side_data(pkt, AV_PKT_DATA_PALETTE, AVPALETTE_SIZE); if (!pal) { av_log(mov->fc, AV_LOG_ERROR, "Cannot append palette to packet\n"); } else { memcpy(pal, sc->palette, AVPALETTE_SIZE); sc->has_palette = 0; #if CONFIG_DV_DEMUXER if (mov->dv_demux && sc->dv_audio_container) { avpriv_dv_produce_packet(mov->dv_demux, pkt, pkt->data, pkt->size, pkt->pos); av_free(pkt->data); pkt->size = 0; ret = avpriv_dv_get_packet(mov->dv_demux, pkt); if (ret < 0) return ret; #endif pkt->stream_index = sc->ffindex; pkt->dts = sample->timestamp; if (sc->ctts_data && sc->ctts_index < sc->ctts_count) { pkt->pts = pkt->dts + sc->dts_shift + sc->ctts_data[sc->ctts_index].duration; /* update ctts context */ sc->ctts_sample++; if (sc->ctts_index < sc->ctts_count && sc->ctts_data[sc->ctts_index].count == sc->ctts_sample) { sc->ctts_index++; sc->ctts_sample = 0; if (sc->wrong_dts) pkt->dts = AV_NOPTS_VALUE; } else { int64_t next_dts = (sc->current_sample < st->nb_index_entries) ? st->index_entries[sc->current_sample].timestamp : st->duration; pkt->duration = next_dts - pkt->dts; pkt->pts = pkt->dts; if (st->discard == AVDISCARD_ALL) goto retry; pkt->flags |= sample->flags & AVINDEX_KEYFRAME ? AV_PKT_FLAG_KEY : 0; pkt->pos = sample->pos; av_dlog(s, "stream %d, pts %"PRId64", dts %"PRId64", pos 0x%"PRIx64", duration %d\n", pkt->stream_index, pkt->pts, pkt->dts, pkt->pos, pkt->duration); return 0;


QEMUSizedBuffer *qsb_create(const uint8_t *buffer, size_t len) { QEMUSizedBuffer *qsb; size_t alloc_len, num_chunks, i, to_copy; size_t chunk_size = (len > QSB_MAX_CHUNK_SIZE) ? QSB_MAX_CHUNK_SIZE : QSB_CHUNK_SIZE; num_chunks = DIV_ROUND_UP(len ? len : QSB_CHUNK_SIZE, chunk_size); alloc_len = num_chunks * chunk_size; qsb = g_try_new0(QEMUSizedBuffer, 1); if (!qsb) { return NULL; } qsb->iov = g_try_new0(struct iovec, num_chunks); if (!qsb->iov) { g_free(qsb); return NULL; } qsb->n_iov = num_chunks; for (i = 0; i < num_chunks; i++) { qsb->iov[i].iov_base = g_try_malloc0(chunk_size); if (!qsb->iov[i].iov_base) { /* qsb_free is safe since g_free can cope with NULL */ qsb_free(qsb); return NULL; } qsb->iov[i].iov_len = chunk_size; if (buffer) { to_copy = (len - qsb->used) > chunk_size ? chunk_size : (len - qsb->used); memcpy(qsb->iov[i].iov_base, &buffer[qsb->used], to_copy); qsb->used += to_copy; } } qsb->size = alloc_len; return qsb; }


static void virtio_notify_vector(VirtIODevice *vdev, uint16_t vector) { BusState *qbus = qdev_get_parent_bus(DEVICE(vdev)); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); if (k->notify) { k->notify(qbus->parent, vector);


static int svq1_motion_inter_4v_block(DSPContext *dsp, GetBitContext *bitbuf, uint8_t *current, uint8_t *previous, int pitch, svq1_pmv *motion, int x, int y) { uint8_t *src; uint8_t *dst; svq1_pmv mv; svq1_pmv *pmv[4]; int i, result; /* predict and decode motion vector (0) */ pmv[0] = &motion[0]; if (y == 0) { pmv[1] = pmv[2] = pmv[0]; } else { pmv[1] = &motion[(x / 8) + 2]; pmv[2] = &motion[(x / 8) + 4]; } result = svq1_decode_motion_vector(bitbuf, &mv, pmv); if (result != 0) return result; /* predict and decode motion vector (1) */ pmv[0] = &mv; if (y == 0) { pmv[1] = pmv[2] = pmv[0]; } else { pmv[1] = &motion[(x / 8) + 3]; } result = svq1_decode_motion_vector(bitbuf, &motion[0], pmv); if (result != 0) return result; /* predict and decode motion vector (2) */ pmv[1] = &motion[0]; pmv[2] = &motion[(x / 8) + 1]; result = svq1_decode_motion_vector(bitbuf, &motion[(x / 8) + 2], pmv); if (result != 0) return result; /* predict and decode motion vector (3) */ pmv[2] = &motion[(x / 8) + 2]; pmv[3] = &motion[(x / 8) + 3]; result = svq1_decode_motion_vector(bitbuf, pmv[3], pmv); if (result != 0) return result; /* form predictions */ for (i = 0; i < 4; i++) { int mvx = pmv[i]->x + (i & 1) * 16; int mvy = pmv[i]->y + (i >> 1) * 16; // FIXME: clipping or padding? if (y + (mvy >> 1) < 0) mvy = 0; if (x + (mvx >> 1) < 0) mvx = 0; src = &previous[(x + (mvx >> 1)) + (y + (mvy >> 1)) * pitch]; dst = current; dsp->put_pixels_tab[1][((mvy & 1) << 1) | (mvx & 1)](dst, src, pitch, 8); /* select next block */ if (i & 1) current += 8 * (pitch - 1); else current += 8; } return 0; }


CPUState *cpu_create(const char *typename) { Error *err = NULL; CPUState *cpu = CPU(object_new(typename)); object_property_set_bool(OBJECT(cpu), true, "realized", &err); if (err != NULL) { error_report_err(err); object_unref(OBJECT(cpu)); return NULL; } return cpu; }


static int qio_channel_socket_connect_worker(QIOTask *task, Error **errp, gpointer opaque) { QIOChannelSocket *ioc = QIO_CHANNEL_SOCKET(qio_task_get_source(task)); SocketAddress *addr = opaque; int ret; ret = qio_channel_socket_connect_sync(ioc, addr, errp); object_unref(OBJECT(ioc)); return ret; }


static const void *boston_kernel_filter(void *opaque, const void *kernel, hwaddr *load_addr, hwaddr *entry_addr) { BostonState *s = BOSTON(opaque); s->kernel_entry = *entry_addr; return kernel; }


static av_always_inline void idct_mb(VP8Context *s, uint8_t *dst[3], VP8Macroblock *mb) { int x, y, ch; if (mb->mode != MODE_I4x4) { uint8_t *y_dst = dst[0]; for (y = 0; y < 4; y++) { uint32_t nnz4 = AV_RL32(s->non_zero_count_cache[y]); if (nnz4) { if (nnz4&~0x01010101) { for (x = 0; x < 4; x++) { if ((uint8_t)nnz4 == 1) s->vp8dsp.vp8_idct_dc_add(y_dst+4*x, s->block[y][x], s->linesize); else if((uint8_t)nnz4 > 1) s->vp8dsp.vp8_idct_add(y_dst+4*x, s->block[y][x], s->linesize); nnz4 >>= 8; if (!nnz4) break; } } else { s->vp8dsp.vp8_idct_dc_add4y(y_dst, s->block[y], s->linesize); } } y_dst += 4*s->linesize; } } for (ch = 0; ch < 2; ch++) { uint32_t nnz4 = AV_RL32(s->non_zero_count_cache[4+ch]); if (nnz4) { uint8_t *ch_dst = dst[1+ch]; if (nnz4&~0x01010101) { for (y = 0; y < 2; y++) { for (x = 0; x < 2; x++) { if ((uint8_t)nnz4 == 1) s->vp8dsp.vp8_idct_dc_add(ch_dst+4*x, s->block[4+ch][(y<<1)+x], s->uvlinesize); else if((uint8_t)nnz4 > 1) s->vp8dsp.vp8_idct_add(ch_dst+4*x, s->block[4+ch][(y<<1)+x], s->uvlinesize); nnz4 >>= 8; if (!nnz4) break; } ch_dst += 4*s->uvlinesize; } } else { s->vp8dsp.vp8_idct_dc_add4uv(ch_dst, s->block[4+ch], s->uvlinesize); } } } }


PCIDevice *virtio_net_init(PCIBus *bus, NICInfo *nd, int devfn) { VirtIONet *n; static int virtio_net_id; n = (VirtIONet *)virtio_init_pci(bus, "virtio-net", PCI_VENDOR_ID_REDHAT_QUMRANET, PCI_DEVICE_ID_VIRTIO_NET, PCI_VENDOR_ID_REDHAT_QUMRANET, VIRTIO_ID_NET, PCI_CLASS_NETWORK_ETHERNET, 0x00, sizeof(struct virtio_net_config), sizeof(VirtIONet)); if (!n) return NULL; n->vdev.get_config = virtio_net_get_config; n->vdev.set_config = virtio_net_set_config; n->vdev.get_features = virtio_net_get_features; n->vdev.set_features = virtio_net_set_features; n->vdev.bad_features = virtio_net_bad_features; n->vdev.reset = virtio_net_reset; n->rx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_rx); n->tx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_tx); n->ctrl_vq = virtio_add_queue(&n->vdev, 16, virtio_net_handle_ctrl); memcpy(n->mac, nd->macaddr, ETH_ALEN); n->status = VIRTIO_NET_S_LINK_UP; n->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, virtio_net_receive, virtio_net_can_receive, n); n->vc->link_status_changed = virtio_net_set_link_status; qemu_format_nic_info_str(n->vc, n->mac); n->tx_timer = qemu_new_timer(vm_clock, virtio_net_tx_timer, n); n->tx_timer_active = 0; n->mergeable_rx_bufs = 0; n->promisc = 1; /* for compatibility */ n->mac_table.macs = qemu_mallocz(MAC_TABLE_ENTRIES * ETH_ALEN); n->vlans = qemu_mallocz(MAX_VLAN >> 3); register_savevm("virtio-net", virtio_net_id++, VIRTIO_NET_VM_VERSION, virtio_net_save, virtio_net_load, n); return (PCIDevice *)n; }


static inline void RENAME(rgb15to16)(const uint8_t *src, uint8_t *dst, int src_size) { register const uint8_t* s=src; register uint8_t* d=dst; register const uint8_t *end; const uint8_t *mm_end; end = s + src_size; __asm__ volatile(PREFETCH" %0"::"m"(*s)); __asm__ volatile("movq %0, %%mm4"::"m"(mask15s)); mm_end = end - 15; while (s<mm_end) { __asm__ volatile( PREFETCH" 32%1 \n\t" "movq %1, %%mm0 \n\t" "movq 8%1, %%mm2 \n\t" "movq %%mm0, %%mm1 \n\t" "movq %%mm2, %%mm3 \n\t" "pand %%mm4, %%mm0 \n\t" "pand %%mm4, %%mm2 \n\t" "paddw %%mm1, %%mm0 \n\t" "paddw %%mm3, %%mm2 \n\t" MOVNTQ" %%mm0, %0 \n\t" MOVNTQ" %%mm2, 8%0" :"=m"(*d) :"m"(*s) ); d+=16; s+=16; } __asm__ volatile(SFENCE:::"memory"); __asm__ volatile(EMMS:::"memory"); mm_end = end - 3; while (s < mm_end) { register unsigned x= *((const uint32_t *)s); *((uint32_t *)d) = (x&0x7FFF7FFF) + (x&0x7FE07FE0); d+=4; s+=4; } if (s < end) { register unsigned short x= *((const uint16_t *)s); *((uint16_t *)d) = (x&0x7FFF) + (x&0x7FE0); } }


static inline void RENAME(rgb15to32)(const uint8_t *src, uint8_t *dst, long src_size) { const uint16_t *end; #ifdef HAVE_MMX const uint16_t *mm_end; #endif uint8_t *d = (uint8_t *)dst; const uint16_t *s = (const uint16_t *)src; end = s + src_size/2; #ifdef HAVE_MMX __asm __volatile(PREFETCH" %0"::"m"(*s):"memory"); __asm __volatile("pxor %%mm7,%%mm7\n\t":::"memory"); mm_end = end - 3; while(s < mm_end) { __asm __volatile( PREFETCH" 32%1\n\t" "movq %1, %%mm0\n\t" "movq %1, %%mm1\n\t" "movq %1, %%mm2\n\t" "pand %2, %%mm0\n\t" "pand %3, %%mm1\n\t" "pand %4, %%mm2\n\t" "psllq $3, %%mm0\n\t" "psrlq $2, %%mm1\n\t" "psrlq $7, %%mm2\n\t" "movq %%mm0, %%mm3\n\t" "movq %%mm1, %%mm4\n\t" "movq %%mm2, %%mm5\n\t" "punpcklwd %%mm7, %%mm0\n\t" "punpcklwd %%mm7, %%mm1\n\t" "punpcklwd %%mm7, %%mm2\n\t" "punpckhwd %%mm7, %%mm3\n\t" "punpckhwd %%mm7, %%mm4\n\t" "punpckhwd %%mm7, %%mm5\n\t" "psllq $8, %%mm1\n\t" "psllq $16, %%mm2\n\t" "por %%mm1, %%mm0\n\t" "por %%mm2, %%mm0\n\t" "psllq $8, %%mm4\n\t" "psllq $16, %%mm5\n\t" "por %%mm4, %%mm3\n\t" "por %%mm5, %%mm3\n\t" MOVNTQ" %%mm0, %0\n\t" MOVNTQ" %%mm3, 8%0\n\t" :"=m"(*d) :"m"(*s),"m"(mask15b),"m"(mask15g),"m"(mask15r) :"memory"); d += 16; s += 4; } __asm __volatile(SFENCE:::"memory"); __asm __volatile(EMMS:::"memory"); #endif while(s < end) { #if 0 //slightly slower on athlon int bgr= *s++; *((uint32_t*)d)++ = ((bgr&0x1F)<<3) + ((bgr&0x3E0)<<6) + ((bgr&0x7C00)<<9); #else register uint16_t bgr; bgr = *s++; #ifdef WORDS_BIGENDIAN *d++ = 0; *d++ = (bgr&0x7C00)>>7; *d++ = (bgr&0x3E0)>>2; *d++ = (bgr&0x1F)<<3; #else *d++ = (bgr&0x1F)<<3; *d++ = (bgr&0x3E0)>>2; *d++ = (bgr&0x7C00)>>7; *d++ = 0; #endif #endif } }


static void tap_send(void *opaque) { TAPState *s = opaque; int size; do { uint8_t *buf = s->buf; size = tap_read_packet(s->fd, s->buf, sizeof(s->buf)); if (size <= 0) { break; } if (s->host_vnet_hdr_len && !s->using_vnet_hdr) { buf += s->host_vnet_hdr_len; size -= s->host_vnet_hdr_len; } size = qemu_send_packet_async(&s->nc, buf, size, tap_send_completed); if (size == 0) { tap_read_poll(s, false); } } while (size > 0 && qemu_can_send_packet(&s->nc)); }


int decode_splitmvs(VP8Context *s, VP56RangeCoder *c, VP8Macroblock *mb, int layout) { int part_idx; int n, num; VP8Macroblock *top_mb; VP8Macroblock *left_mb = &mb[-1]; const uint8_t *mbsplits_left = vp8_mbsplits[left_mb->partitioning]; const uint8_t *mbsplits_top, *mbsplits_cur, *firstidx; VP56mv *top_mv; VP56mv *left_mv = left_mb->bmv; VP56mv *cur_mv = mb->bmv; if (!layout) // layout is inlined, s->mb_layout is not top_mb = &mb[2]; else top_mb = &mb[-s->mb_width - 1]; mbsplits_top = vp8_mbsplits[top_mb->partitioning]; top_mv = top_mb->bmv; if (vp56_rac_get_prob_branchy(c, vp8_mbsplit_prob[0])) { if (vp56_rac_get_prob_branchy(c, vp8_mbsplit_prob[1])) part_idx = VP8_SPLITMVMODE_16x8 + vp56_rac_get_prob(c, vp8_mbsplit_prob[2]); else part_idx = VP8_SPLITMVMODE_8x8; } else { part_idx = VP8_SPLITMVMODE_4x4; } num = vp8_mbsplit_count[part_idx]; mbsplits_cur = vp8_mbsplits[part_idx], firstidx = vp8_mbfirstidx[part_idx]; mb->partitioning = part_idx; for (n = 0; n < num; n++) { int k = firstidx[n]; uint32_t left, above; const uint8_t *submv_prob; if (!(k & 3)) left = AV_RN32A(&left_mv[mbsplits_left[k + 3]]); else left = AV_RN32A(&cur_mv[mbsplits_cur[k - 1]]); if (k <= 3) above = AV_RN32A(&top_mv[mbsplits_top[k + 12]]); else above = AV_RN32A(&cur_mv[mbsplits_cur[k - 4]]); submv_prob = get_submv_prob(left, above); if (vp56_rac_get_prob_branchy(c, submv_prob[0])) { if (vp56_rac_get_prob_branchy(c, submv_prob[1])) { if (vp56_rac_get_prob_branchy(c, submv_prob[2])) { mb->bmv[n].y = mb->mv.y + read_mv_component(c, s->prob->mvc[0]); mb->bmv[n].x = mb->mv.x + read_mv_component(c, s->prob->mvc[1]); } else { AV_ZERO32(&mb->bmv[n]); } } else { AV_WN32A(&mb->bmv[n], above); } } else { AV_WN32A(&mb->bmv[n], left); } } return num; }


static inline void FUNC(idctSparseColPut)(pixel *dest, int line_size, DCTELEM *col) { int a0, a1, a2, a3, b0, b1, b2, b3; INIT_CLIP; IDCT_COLS; dest[0] = CLIP((a0 + b0) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a1 + b1) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a2 + b2) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a3 + b3) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a3 - b3) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a2 - b2) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a1 - b1) >> COL_SHIFT); dest += line_size; dest[0] = CLIP((a0 - b0) >> COL_SHIFT); }


void hbitmap_reset(HBitmap *hb, uint64_t start, uint64_t count) { /* Compute range in the last layer. */ uint64_t last = start + count - 1; trace_hbitmap_reset(hb, start, count, start >> hb->granularity, last >> hb->granularity); start >>= hb->granularity; last >>= hb->granularity; hb->count -= hb_count_between(hb, start, last); hb_reset_between(hb, HBITMAP_LEVELS - 1, start, last); }


static int raw_create(const char *filename, QemuOpts *opts, Error **errp) { int fd; int result = 0; int64_t total_size = 0; bool nocow = false; PreallocMode prealloc; char *buf = NULL; Error *local_err = NULL; strstart(filename, "file:", &filename); /* Read out options */ total_size = ROUND_UP(qemu_opt_get_size_del(opts, BLOCK_OPT_SIZE, 0), BDRV_SECTOR_SIZE); nocow = qemu_opt_get_bool(opts, BLOCK_OPT_NOCOW, false); buf = qemu_opt_get_del(opts, BLOCK_OPT_PREALLOC); prealloc = qapi_enum_parse(PreallocMode_lookup, buf, PREALLOC_MODE__MAX, PREALLOC_MODE_OFF, &local_err); g_free(buf); if (local_err) { error_propagate(errp, local_err); result = -EINVAL; goto out; } fd = qemu_open(filename, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0644); if (fd < 0) { result = -errno; error_setg_errno(errp, -result, "Could not create file"); goto out; } if (nocow) { #ifdef __linux__ /* Set NOCOW flag to solve performance issue on fs like btrfs. * This is an optimisation. The FS_IOC_SETFLAGS ioctl return value * will be ignored since any failure of this operation should not * block the left work. */ int attr; if (ioctl(fd, FS_IOC_GETFLAGS, &attr) == 0) { attr |= FS_NOCOW_FL; ioctl(fd, FS_IOC_SETFLAGS, &attr); } #endif } if (ftruncate(fd, total_size) != 0) { result = -errno; error_setg_errno(errp, -result, "Could not resize file"); goto out_close; } switch (prealloc) { #ifdef CONFIG_POSIX_FALLOCATE case PREALLOC_MODE_FALLOC: /* posix_fallocate() doesn't set errno. */ result = -posix_fallocate(fd, 0, total_size); if (result != 0) { error_setg_errno(errp, -result, "Could not preallocate data for the new file"); } break; #endif case PREALLOC_MODE_FULL: { int64_t num = 0, left = total_size; buf = g_malloc0(65536); while (left > 0) { num = MIN(left, 65536); result = write(fd, buf, num); if (result < 0) { result = -errno; error_setg_errno(errp, -result, "Could not write to the new file"); break; } left -= result; } if (result >= 0) { result = fsync(fd); if (result < 0) { result = -errno; error_setg_errno(errp, -result, "Could not flush new file to disk"); } } g_free(buf); break; } case PREALLOC_MODE_OFF: break; default: result = -EINVAL; error_setg(errp, "Unsupported preallocation mode: %s", PreallocMode_lookup[prealloc]); break; } out_close: if (qemu_close(fd) != 0 && result == 0) { result = -errno; error_setg_errno(errp, -result, "Could not close the new file"); } out: return result; }


static int aasc_decode_frame(AVCodecContext *avctx, void *data, int *got_frame, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; AascContext *s = avctx->priv_data; int compr, i, stride, ret; if (buf_size < 4) if ((ret = ff_reget_buffer(avctx, s->frame)) < 0) { av_log(avctx, AV_LOG_ERROR, "reget_buffer() failed\n"); return ret; } compr = AV_RL32(buf); buf += 4; buf_size -= 4; switch (compr) { case 0: stride = (avctx->width * 3 + 3) & ~3; for (i = avctx->height - 1; i >= 0; i--) { memcpy(s->frame->data[0] + i * s->frame->linesize[0], buf, avctx->width * 3); buf += stride; } break; case 1: bytestream2_init(&s->gb, buf, buf_size); ff_msrle_decode(avctx, (AVPicture*)s->frame, 8, &s->gb); break; default: av_log(avctx, AV_LOG_ERROR, "Unknown compression type %d\n", compr); } *got_frame = 1; if ((ret = av_frame_ref(data, s->frame)) < 0) return ret; /* report that the buffer was completely consumed */ return buf_size; }


void mips_malta_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; ram_addr_t ram_low_size; const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; char *filename; pflash_t *fl; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *ram_high = g_new(MemoryRegion, 1); MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); MemoryRegion *ram_low_postio; MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); target_long bios_size = FLASH_SIZE; const size_t smbus_eeprom_size = 8 * 256; uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); int64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; MIPSCPU *cpu; CPUMIPSState *env; qemu_irq *isa_irq; qemu_irq *cpu_exit_irq; int piix4_devfn; I2CBus *smbus; int i; DriveInfo *dinfo; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *fd[MAX_FD]; int fl_idx = 0; int fl_sectors = bios_size >> 16; int be; DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); MaltaState *s = MIPS_MALTA(dev); /* The whole address space decoded by the GT-64120A doesn't generate exception when accessing invalid memory. Create an empty slot to emulate this feature. */ empty_slot_init(0, 0x20000000); qdev_init_nofail(dev); /* Make sure the first 3 serial ports are associated with a device. */ for(i = 0; i < 3; i++) { if (!serial_hds[i]) { char label[32]; snprintf(label, sizeof(label), "serial%d", i); serial_hds[i] = qemu_chr_new(label, "null", NULL); } } /* init CPUs */ if (cpu_model == NULL) { #ifdef TARGET_MIPS64 cpu_model = "20Kc"; #else cpu_model = "24Kf"; #endif } for (i = 0; i < smp_cpus; i++) { cpu = cpu_mips_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } env = &cpu->env; /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); qemu_register_reset(main_cpu_reset, cpu); } cpu = MIPS_CPU(first_cpu); env = &cpu->env; /* allocate RAM */ if (ram_size > (2048u << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 2048 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } /* register RAM at high address where it is undisturbed by IO */ memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram", ram_size); memory_region_add_subregion(system_memory, 0x80000000, ram_high); /* alias for pre IO hole access */ memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", ram_high, 0, MIN(ram_size, (256 << 20))); memory_region_add_subregion(system_memory, 0, ram_low_preio); /* alias for post IO hole access, if there is enough RAM */ if (ram_size > (512 << 20)) { ram_low_postio = g_new(MemoryRegion, 1); memory_region_init_alias(ram_low_postio, NULL, "mips_malta_low_postio.ram", ram_high, 512 << 20, ram_size - (512 << 20)); memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio); } /* generate SPD EEPROM data */ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); #ifdef TARGET_WORDS_BIGENDIAN be = 1; #else be = 0; #endif /* FPGA */ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); #ifdef DEBUG_BOARD_INIT if (dinfo) { printf("Register parallel flash %d size " TARGET_FMT_lx " at " "addr %08llx '%s' %x\n", fl_idx, bios_size, FLASH_ADDRESS, blk_name(dinfo->bdrv), fl_sectors); } #endif fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios", BIOS_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 65536, fl_sectors, 4, 0x0000, 0x0000, 0x0000, 0x0000, be); bios = pflash_cfi01_get_memory(fl); fl_idx++; if (kernel_filename) { ram_low_size = MIN(ram_size, 256 << 20); /* For KVM we reserve 1MB of RAM for running bootloader */ if (kvm_enabled()) { ram_low_size -= 0x100000; bootloader_run_addr = 0x40000000 + ram_low_size; } else { bootloader_run_addr = 0xbfc00000; } /* Write a small bootloader to the flash location. */ loaderparams.ram_size = ram_low_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); write_bootloader(env, memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); if (kvm_enabled()) { /* Write the bootloader code @ the end of RAM, 1MB reserved */ write_bootloader(env, memory_region_get_ram_ptr(ram_low_preio) + ram_low_size, bootloader_run_addr, kernel_entry); } } else { /* The flash region isn't executable from a KVM guest */ if (kvm_enabled()) { error_report("KVM enabled but no -kernel argument was specified. " "Booting from flash is not supported with KVM."); exit(1); } /* Load firmware from flash. */ if (!dinfo) { /* Load a BIOS image. */ if (bios_name == NULL) { bios_name = BIOS_FILENAME; } filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { bios_size = load_image_targphys(filename, FLASH_ADDRESS, BIOS_SIZE); g_free(filename); } else { bios_size = -1; } if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename && !qtest_enabled()) { error_report("Could not load MIPS bios '%s', and no " "-kernel argument was specified", bios_name); exit(1); } } /* In little endian mode the 32bit words in the bios are swapped, a neat trick which allows bi-endian firmware. */ #ifndef TARGET_WORDS_BIGENDIAN { uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS); if (!addr) { addr = memory_region_get_ram_ptr(bios); } end = (void *)addr + MIN(bios_size, 0x3e0000); while (addr < end) { bswap32s(addr); addr++; } } #endif } /* * Map the BIOS at a 2nd physical location, as on the real board. * Copy it so that we can patch in the MIPS revision, which cannot be * handled by an overlapping region as the resulting ROM code subpage * regions are not executable. */ memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, &error_abort); if (!rom_copy(memory_region_get_ram_ptr(bios_copy), FLASH_ADDRESS, BIOS_SIZE)) { memcpy(memory_region_get_ram_ptr(bios_copy), memory_region_get_ram_ptr(bios), BIOS_SIZE); } memory_region_set_readonly(bios_copy, true); memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); /* Board ID = 0x420 (Malta Board with CoreLV) */ stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); /* * We have a circular dependency problem: pci_bus depends on isa_irq, * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends * on piix4, and piix4 depends on pci_bus. To stop the cycle we have * qemu_irq_proxy() adds an extra bit of indirection, allowing us * to resolve the isa_irq -> i8259 dependency after i8259 is initialized. */ isa_irq = qemu_irq_proxy(&s->i8259, 16); /* Northbridge */ pci_bus = gt64120_register(isa_irq); /* Southbridge */ ide_drive_get(hd, ARRAY_SIZE(hd)); piix4_devfn = piix4_init(pci_bus, &isa_bus, 80); /* Interrupt controller */ /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */ s->i8259 = i8259_init(isa_bus, env->irq[2]); isa_bus_irqs(isa_bus, s->i8259); pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL, NULL); smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); g_free(smbus_eeprom_buf); pit = pit_init(isa_bus, 0x40, 0, NULL); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); /* Super I/O */ isa_create_simple(isa_bus, "i8042"); rtc_init(isa_bus, 2000, NULL); serial_hds_isa_init(isa_bus, 2); parallel_hds_isa_init(isa_bus, 1); for(i = 0; i < MAX_FD; i++) { fd[i] = drive_get(IF_FLOPPY, 0, i); } fdctrl_init_isa(isa_bus, fd); /* Network card */ network_init(pci_bus); /* Optional PCI video card */ pci_vga_init(pci_bus); }