static av_always_inline void blend_image_packed_rgb(AVFilterContext *ctx, AVFrame *dst, const AVFrame *src, int main_has_alpha, int x, int y, int is_straight) { OverlayContext *s = ctx->priv; int i, imax, j, jmax; const int src_w = src->width; const int src_h = src->height; const int dst_w = dst->width; const int dst_h = dst->height; uint8_t alpha; ///< the amount of overlay to blend on to main const int dr = s->main_rgba_map[R]; const int dg = s->main_rgba_map[G]; const int db = s->main_rgba_map[B]; const int da = s->main_rgba_map[A]; const int dstep = s->main_pix_step[0]; const int sr = s->overlay_rgba_map[R]; const int sg = s->overlay_rgba_map[G]; const int sb = s->overlay_rgba_map[B]; const int sa = s->overlay_rgba_map[A]; const int sstep = s->overlay_pix_step[0]; uint8_t *S, *sp, *d, *dp; i = FFMAX(-y, 0); sp = src->data[0] + i * src->linesize[0]; dp = dst->data[0] + (y+i) * dst->linesize[0]; for (imax = FFMIN(-y + dst_h, src_h); i < imax; i++) { j = FFMAX(-x, 0); S = sp + j * sstep; d = dp + (x+j) * dstep; for (jmax = FFMIN(-x + dst_w, src_w); j < jmax; j++) { alpha = S[sa]; // if the main channel has an alpha channel, alpha has to be calculated // to create an un-premultiplied (straight) alpha value if (main_has_alpha && alpha != 0 && alpha != 255) { uint8_t alpha_d = d[da]; alpha = UNPREMULTIPLY_ALPHA(alpha, alpha_d); } switch (alpha) { case 0: break; case 255: d[dr] = S[sr]; d[dg] = S[sg]; d[db] = S[sb]; break; default: // main_value = main_value * (1 - alpha) + overlay_value * alpha // since alpha is in the range 0-255, the result must divided by 255 d[dr] = is_straight ? FAST_DIV255(d[dr] * (255 - alpha) + S[sr] * alpha) : FAST_DIV255(d[dr] * (255 - alpha) + S[sr]); d[dg] = is_straight ? FAST_DIV255(d[dg] * (255 - alpha) + S[sg] * alpha) : FAST_DIV255(d[dr] * (255 - alpha) + S[sr]); d[db] = is_straight ? FAST_DIV255(d[db] * (255 - alpha) + S[sb] * alpha) : FAST_DIV255(d[dr] * (255 - alpha) + S[sr]); } if (main_has_alpha) { switch (alpha) { case 0: break; case 255: d[da] = S[sa]; break; default: // apply alpha compositing: main_alpha += (1-main_alpha) * overlay_alpha d[da] += FAST_DIV255((255 - d[da]) * S[sa]); } } d += dstep; S += sstep; } dp += dst->linesize[0]; sp += src->linesize[0]; } }


static int qemu_rdma_exchange_send(RDMAContext *rdma, RDMAControlHeader *head, uint8_t *data, RDMAControlHeader *resp, int *resp_idx, int (*callback)(RDMAContext *rdma)) { int ret = 0; /* * Wait until the dest is ready before attempting to deliver the message * by waiting for a READY message. */ if (rdma->control_ready_expected) { RDMAControlHeader resp; ret = qemu_rdma_exchange_get_response(rdma, &resp, RDMA_CONTROL_READY, RDMA_WRID_READY); if (ret < 0) { return ret; } } /* * If the user is expecting a response, post a WR in anticipation of it. */ if (resp) { ret = qemu_rdma_post_recv_control(rdma, RDMA_WRID_DATA); if (ret) { fprintf(stderr, "rdma migration: error posting" " extra control recv for anticipated result!"); return ret; } } /* * Post a WR to replace the one we just consumed for the READY message. */ ret = qemu_rdma_post_recv_control(rdma, RDMA_WRID_READY); if (ret) { fprintf(stderr, "rdma migration: error posting first control recv!"); return ret; } /* * Deliver the control message that was requested. */ ret = qemu_rdma_post_send_control(rdma, data, head); if (ret < 0) { fprintf(stderr, "Failed to send control buffer!\n"); return ret; } /* * If we're expecting a response, block and wait for it. */ if (resp) { if (callback) { DDPRINTF("Issuing callback before receiving response...\n"); ret = callback(rdma); if (ret < 0) { return ret; } } DDPRINTF("Waiting for response %s\n", control_desc[resp->type]); ret = qemu_rdma_exchange_get_response(rdma, resp, resp->type, RDMA_WRID_DATA); if (ret < 0) { return ret; } qemu_rdma_move_header(rdma, RDMA_WRID_DATA, resp); if (resp_idx) { *resp_idx = RDMA_WRID_DATA; } DDPRINTF("Response %s received.\n", control_desc[resp->type]); } rdma->control_ready_expected = 1; return 0; }


static int configure_accelerator(void) { const char *p = NULL; char buf[10]; int i, ret; bool accel_initialised = false; bool init_failed = false; QemuOptsList *list = qemu_find_opts("machine"); if (!QTAILQ_EMPTY(&list->head)) { p = qemu_opt_get(QTAILQ_FIRST(&list->head), "accel"); } if (p == NULL) { /* Use the default "accelerator", tcg */ p = "tcg"; } while (!accel_initialised && *p != '\0') { if (*p == ':') { p++; } p = get_opt_name(buf, sizeof (buf), p, ':'); for (i = 0; i < ARRAY_SIZE(accel_list); i++) { if (strcmp(accel_list[i].opt_name, buf) == 0) { if (!accel_list[i].available()) { printf("%s not supported for this target\n", accel_list[i].name); continue; } *(accel_list[i].allowed) = true; ret = accel_list[i].init(); if (ret < 0) { init_failed = true; fprintf(stderr, "failed to initialize %s: %s\n", accel_list[i].name, strerror(-ret)); *(accel_list[i].allowed) = false; } else { accel_initialised = true; } break; } } if (i == ARRAY_SIZE(accel_list)) { fprintf(stderr, "\"%s\" accelerator does not exist.\n", buf); } } if (!accel_initialised) { if (!init_failed) { fprintf(stderr, "No accelerator found!\n"); } exit(1); } if (init_failed) { fprintf(stderr, "Back to %s accelerator.\n", accel_list[i].name); } return !accel_initialised; }


void qemu_chr_add_handlers(CharDriverState *s, IOCanReadHandler *fd_can_read, IOReadHandler *fd_read, IOEventHandler *fd_event, void *opaque) { if (!opaque) { /* chr driver being released. */ s->assigned = 0; } s->chr_can_read = fd_can_read; s->chr_read = fd_read; s->chr_event = fd_event; s->handler_opaque = opaque; if (s->chr_update_read_handler) s->chr_update_read_handler(s); /* We're connecting to an already opened device, so let's make sure we also get the open event */ if (s->opened) { qemu_chr_generic_open(s); } }


static int decode_block_refinement(MJpegDecodeContext *s, int16_t *block, uint8_t *last_nnz, int ac_index, int16_t *quant_matrix, int ss, int se, int Al, int *EOBRUN) { int code, i = ss, j, sign, val, run; int last = FFMIN(se, *last_nnz); OPEN_READER(re, &s->gb); if (*EOBRUN) { (*EOBRUN)--; } else { for (; ; i++) { UPDATE_CACHE(re, &s->gb); GET_VLC(code, re, &s->gb, s->vlcs[2][ac_index].table, 9, 2); if (code & 0xF) { run = ((unsigned) code) >> 4; UPDATE_CACHE(re, &s->gb); val = SHOW_UBITS(re, &s->gb, 1); LAST_SKIP_BITS(re, &s->gb, 1); ZERO_RUN; j = s->scantable.permutated[i]; val--; block[j] = ((quant_matrix[j]^val) - val) << Al; if (i == se) { if (i > *last_nnz) *last_nnz = i; CLOSE_READER(re, &s->gb); return 0; } } else { run = ((unsigned) code) >> 4; if (run == 0xF) { ZERO_RUN; } else { val = run; run = (1 << run); if (val) { UPDATE_CACHE(re, &s->gb); run += SHOW_UBITS(re, &s->gb, val); LAST_SKIP_BITS(re, &s->gb, val); } *EOBRUN = run - 1; break; } } } if (i > *last_nnz) *last_nnz = i; } for (; i <= last; i++) { j = s->scantable.permutated[i]; if (block[j]) REFINE_BIT(j) } CLOSE_READER(re, &s->gb); return 0; }


int ff_mov_lang_to_iso639(int code, char *to) { int i; /* is it the mangled iso code? */ /* see http://www.geocities.com/xhelmboyx/quicktime/formats/mp4-layout.txt */ if (code > 138) { for (i = 2; i >= 0; i--) { to[i] = 0x60 + (code & 0x1f); code >>= 5; } return 1; } /* old fashion apple lang code */ if (code >= FF_ARRAY_ELEMS(mov_mdhd_language_map)) return 0; if (!mov_mdhd_language_map[code]) return 0; strncpy(to, mov_mdhd_language_map[code], 4); return 1; }


static void ohci_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ohci_realize_pxa; set_bit(DEVICE_CATEGORY_USB, dc->categories); dc->desc = "OHCI USB Controller"; dc->props = ohci_sysbus_properties; dc->reset = usb_ohci_reset_sysbus; }


av_cold void ff_vp3dsp_init_x86(VP3DSPContext *c, int flags) { #if HAVE_YASM int cpuflags = av_get_cpu_flags(); #if ARCH_X86_32 if (HAVE_MMX && cpuflags & AV_CPU_FLAG_MMX) { c->idct_put = ff_vp3_idct_put_mmx; c->idct_add = ff_vp3_idct_add_mmx; c->idct_perm = FF_PARTTRANS_IDCT_PERM; } #endif if (HAVE_MMXEXT && cpuflags & AV_CPU_FLAG_MMXEXT) { c->idct_dc_add = ff_vp3_idct_dc_add_mmx2; if (!(flags & CODEC_FLAG_BITEXACT)) { c->v_loop_filter = ff_vp3_v_loop_filter_mmx2; c->h_loop_filter = ff_vp3_h_loop_filter_mmx2; } } if (cpuflags & AV_CPU_FLAG_SSE2) { c->idct_put = ff_vp3_idct_put_sse2; c->idct_add = ff_vp3_idct_add_sse2; c->idct_perm = FF_TRANSPOSE_IDCT_PERM; } #endif }


void memory_region_init(MemoryRegion *mr, const char *name, uint64_t size) { mr->ops = NULL; mr->parent = NULL; mr->size = int128_make64(size); if (size == UINT64_MAX) { mr->size = int128_2_64(); } mr->addr = 0; mr->subpage = false; mr->enabled = true; mr->terminates = false; mr->ram = false; mr->romd_mode = true; mr->readonly = false; mr->rom_device = false; mr->destructor = memory_region_destructor_none; mr->priority = 0; mr->may_overlap = false; mr->alias = NULL; QTAILQ_INIT(&mr->subregions); memset(&mr->subregions_link, 0, sizeof mr->subregions_link); QTAILQ_INIT(&mr->coalesced); mr->name = g_strdup(name); mr->dirty_log_mask = 0; mr->ioeventfd_nb = 0; mr->ioeventfds = NULL; mr->flush_coalesced_mmio = false; }


float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1) { /* ??? This may incorrectly raise exceptions. */ /* ??? Should flush denormals to zero. */ float64 res; res = float64_sub(src0, src1, &env->fp_status); if (float64_is_nan(res)) { /* +/-inf compares equal against itself, but sub returns nan. */ if (!float64_is_nan(src0) && !float64_is_nan(src1)) { res = 0; if (float64_lt_quiet(src0, res, &env->fp_status)) res = float64_chs(res); } } return res; }


bool write_list_to_kvmstate(ARMCPU *cpu) { CPUState *cs = CPU(cpu); int i; bool ok = true; for (i = 0; i < cpu->cpreg_array_len; i++) { struct kvm_one_reg r; uint64_t regidx = cpu->cpreg_indexes[i]; uint32_t v32; int ret; r.id = regidx; switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: v32 = cpu->cpreg_values[i]; r.addr = (uintptr_t)&v32; break; case KVM_REG_SIZE_U64: r.addr = (uintptr_t)(cpu->cpreg_values + i); break; default: abort(); } ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with * a different value from what it actually contains". */ ok = false; } } return ok; }


static void do_mchk_interrupt(CPUS390XState *env) { S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; MchkQueue *q; int i; if (!(env->psw.mask & PSW_MASK_MCHECK)) { cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n"); } if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) { cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index); } q = &env->mchk_queue[env->mchk_index]; if (q->type != 1) { /* Don't know how to handle this... */ cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type); } if (!(env->cregs[14] & (1 << 28))) { /* CRW machine checks disabled */ return; } lowcore = cpu_map_lowcore(env); for (i = 0; i < 16; i++) { lowcore->floating_pt_save_area[i] = cpu_to_be64(get_freg(env, i)->ll); lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]); lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]); lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]); } lowcore->prefixreg_save_area = cpu_to_be32(env->psa); lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc); lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr); lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32); lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm); lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32); lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc); lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d); lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000); lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->mcck_new_psw.mask); addr = be64_to_cpu(lowcore->mcck_new_psw.addr); cpu_unmap_lowcore(lowcore); env->mchk_index--; if (env->mchk_index == -1) { env->pending_int &= ~INTERRUPT_MCHK; } DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, env->psw.mask, env->psw.addr); load_psw(env, mask, addr); }


static void bochs_bios_init(void) { void *fw_cfg; uint8_t *smbios_table; size_t smbios_len; uint64_t *numa_fw_cfg; int i, j; register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, acpi_tables_len); smbios_table = smbios_get_table(&smbios_len); if (smbios_table) fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, smbios_table, smbios_len); /* allocate memory for the NUMA channel: one (64bit) word for the number * of nodes, one word for each VCPU->node and one word for each node to * hold the amount of memory. */ numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); for (i = 0; i < smp_cpus; i++) { for (j = 0; j < nb_numa_nodes; j++) { if (node_cpumask[j] & (1 << i)) { numa_fw_cfg[i + 1] = cpu_to_le64(j); break; } } } for (i = 0; i < nb_numa_nodes; i++) { numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); } fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, (1 + smp_cpus + nb_numa_nodes) * 8); }


check_host_key_hash(BDRVSSHState *s, const char *hash, int hash_type, size_t fingerprint_len) { const char *fingerprint; fingerprint = libssh2_hostkey_hash(s->session, hash_type); if (!fingerprint) { session_error_report(s, "failed to read remote host key"); return -EINVAL; } if(compare_fingerprint((unsigned char *) fingerprint, fingerprint_len, hash) != 0) { error_report("remote host key does not match host_key_check '%s'", hash); return -EPERM; } return 0; }


static uint64_t get_cluster_offset(BlockDriverState *bs, uint64_t offset, int allocate, int compressed_size, int n_start, int n_end) { BDRVQcowState *s = bs->opaque; int min_index, i, j, l1_index, l2_index; uint64_t l2_offset, *l2_table, cluster_offset, tmp; uint32_t min_count; int new_l2_table; l1_index = offset >> (s->l2_bits + s->cluster_bits); l2_offset = s->l1_table[l1_index]; new_l2_table = 0; if (!l2_offset) { if (!allocate) return 0; /* allocate a new l2 entry */ l2_offset = bdrv_getlength(bs->file->bs); /* round to cluster size */ l2_offset = (l2_offset + s->cluster_size - 1) & ~(s->cluster_size - 1); /* update the L1 entry */ s->l1_table[l1_index] = l2_offset; tmp = cpu_to_be64(l2_offset); if (bdrv_pwrite_sync(bs->file, s->l1_table_offset + l1_index * sizeof(tmp), &tmp, sizeof(tmp)) < 0) return 0; new_l2_table = 1; } for(i = 0; i < L2_CACHE_SIZE; i++) { if (l2_offset == s->l2_cache_offsets[i]) { /* increment the hit count */ if (++s->l2_cache_counts[i] == 0xffffffff) { for(j = 0; j < L2_CACHE_SIZE; j++) { s->l2_cache_counts[j] >>= 1; } } l2_table = s->l2_cache + (i << s->l2_bits); goto found; } } /* not found: load a new entry in the least used one */ min_index = 0; min_count = 0xffffffff; for(i = 0; i < L2_CACHE_SIZE; i++) { if (s->l2_cache_counts[i] < min_count) { min_count = s->l2_cache_counts[i]; min_index = i; } } l2_table = s->l2_cache + (min_index << s->l2_bits); if (new_l2_table) { memset(l2_table, 0, s->l2_size * sizeof(uint64_t)); if (bdrv_pwrite_sync(bs->file, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) < 0) return 0; } else { if (bdrv_pread(bs->file, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return 0; } s->l2_cache_offsets[min_index] = l2_offset; s->l2_cache_counts[min_index] = 1; found: l2_index = (offset >> s->cluster_bits) & (s->l2_size - 1); cluster_offset = be64_to_cpu(l2_table[l2_index]); if (!cluster_offset || ((cluster_offset & QCOW_OFLAG_COMPRESSED) && allocate == 1)) { if (!allocate) return 0; /* allocate a new cluster */ if ((cluster_offset & QCOW_OFLAG_COMPRESSED) && (n_end - n_start) < s->cluster_sectors) { /* if the cluster is already compressed, we must decompress it in the case it is not completely overwritten */ if (decompress_cluster(bs, cluster_offset) < 0) return 0; cluster_offset = bdrv_getlength(bs->file->bs); cluster_offset = (cluster_offset + s->cluster_size - 1) & ~(s->cluster_size - 1); /* write the cluster content */ if (bdrv_pwrite(bs->file, cluster_offset, s->cluster_cache, s->cluster_size) != s->cluster_size) return -1; } else { cluster_offset = bdrv_getlength(bs->file->bs); if (allocate == 1) { /* round to cluster size */ cluster_offset = (cluster_offset + s->cluster_size - 1) & ~(s->cluster_size - 1); bdrv_truncate(bs->file, cluster_offset + s->cluster_size, NULL); /* if encrypted, we must initialize the cluster content which won't be written */ if (bs->encrypted && (n_end - n_start) < s->cluster_sectors) { uint64_t start_sect; assert(s->cipher); start_sect = (offset & ~(s->cluster_size - 1)) >> 9; for(i = 0; i < s->cluster_sectors; i++) { if (i < n_start || i >= n_end) { Error *err = NULL; memset(s->cluster_data, 0x00, 512); if (encrypt_sectors(s, start_sect + i, s->cluster_data, 1, true, &err) < 0) { error_free(err); errno = EIO; return -1; } if (bdrv_pwrite(bs->file, cluster_offset + i * 512, s->cluster_data, 512) != 512) return -1; } } } } else if (allocate == 2) { cluster_offset |= QCOW_OFLAG_COMPRESSED | (uint64_t)compressed_size << (63 - s->cluster_bits); } } /* update L2 table */ tmp = cpu_to_be64(cluster_offset); l2_table[l2_index] = tmp; if (bdrv_pwrite_sync(bs->file, l2_offset + l2_index * sizeof(tmp), &tmp, sizeof(tmp)) < 0) return 0; } return cluster_offset; }


static int decode_hrd(VC9Context *v, GetBitContext *gb) { int i, num; num = get_bits(gb, 5); if (v->hrd_rate || num != v->hrd_num_leaky_buckets) { av_freep(&v->hrd_rate); } if (!v->hrd_rate) v->hrd_rate = av_malloc(num); if (!v->hrd_rate) return -1; if (v->hrd_buffer || num != v->hrd_num_leaky_buckets) { av_freep(&v->hrd_buffer); } if (!v->hrd_buffer) v->hrd_buffer = av_malloc(num); if (!v->hrd_buffer) return -1; v->hrd_num_leaky_buckets = num; //exponent in base-2 for rate v->bit_rate_exponent = get_bits(gb, 4); //exponent in base-2 for buffer_size v->buffer_size_exponent = get_bits(gb, 4); for (i=0; i<num; i++) { //mantissae, ordered (if not, use a function ? v->hrd_rate[i] = get_bits(gb, 16); if (i && v->hrd_rate[i-1]>=v->hrd_rate[i]) { av_log(v, AV_LOG_ERROR, "HDR Rates aren't strictly increasing:" "%i vs %i\n", v->hrd_rate[i-1], v->hrd_rate[i]); return -1; } v->hrd_buffer[i] = get_bits(gb, 16); if (i && v->hrd_buffer[i-1]<v->hrd_buffer[i]) { av_log(v, AV_LOG_ERROR, "HDR Buffers aren't decreasing:" "%i vs %i\n", v->hrd_buffer[i-1], v->hrd_buffer[i]); return -1; } } return 0; }


static int handle_utimensat(FsContext *ctx, V9fsPath *fs_path, const struct timespec *buf) { int fd, ret; struct handle_data *data = (struct handle_data *)ctx->private; fd = open_by_handle(data->mountfd, fs_path->data, O_NONBLOCK); if (fd < 0) { return fd; } ret = futimens(fd, buf); close(fd); return ret; }


int kqemu_cpu_exec(CPUState *env) { struct kqemu_cpu_state kcpu_state, *kenv = &kcpu_state; int ret, cpl, i; #ifdef CONFIG_PROFILER int64_t ti; #endif #ifdef _WIN32 DWORD temp; #endif #ifdef CONFIG_PROFILER ti = profile_getclock(); #endif LOG_INT("kqemu: cpu_exec: enter\n"); LOG_INT_STATE(env); for(i = 0; i < CPU_NB_REGS; i++) kenv->regs[i] = env->regs[i]; kenv->eip = env->eip; kenv->eflags = env->eflags; for(i = 0; i < 6; i++) kqemu_load_seg(&kenv->segs[i], &env->segs[i]); kqemu_load_seg(&kenv->ldt, &env->ldt); kqemu_load_seg(&kenv->tr, &env->tr); kqemu_load_seg(&kenv->gdt, &env->gdt); kqemu_load_seg(&kenv->idt, &env->idt); kenv->cr0 = env->cr[0]; kenv->cr2 = env->cr[2]; kenv->cr3 = env->cr[3]; kenv->cr4 = env->cr[4]; kenv->a20_mask = env->a20_mask; kenv->efer = env->efer; kenv->tsc_offset = 0; kenv->star = env->star; kenv->sysenter_cs = env->sysenter_cs; kenv->sysenter_esp = env->sysenter_esp; kenv->sysenter_eip = env->sysenter_eip; #ifdef TARGET_X86_64 kenv->lstar = env->lstar; kenv->cstar = env->cstar; kenv->fmask = env->fmask; kenv->kernelgsbase = env->kernelgsbase; #endif if (env->dr[7] & 0xff) { kenv->dr7 = env->dr[7]; kenv->dr0 = env->dr[0]; kenv->dr1 = env->dr[1]; kenv->dr2 = env->dr[2]; kenv->dr3 = env->dr[3]; } else { kenv->dr7 = 0; } kenv->dr6 = env->dr[6]; cpl = (env->hflags & HF_CPL_MASK); kenv->cpl = cpl; kenv->nb_pages_to_flush = nb_pages_to_flush; kenv->user_only = (env->kqemu_enabled == 1); kenv->nb_ram_pages_to_update = nb_ram_pages_to_update; nb_ram_pages_to_update = 0; kenv->nb_modified_ram_pages = nb_modified_ram_pages; kqemu_reset_modified_ram_pages(); if (env->cpuid_features & CPUID_FXSR) restore_native_fp_fxrstor(env); else restore_native_fp_frstor(env); #ifdef _WIN32 if (DeviceIoControl(kqemu_fd, KQEMU_EXEC, kenv, sizeof(struct kqemu_cpu_state), kenv, sizeof(struct kqemu_cpu_state), &temp, NULL)) { ret = kenv->retval; } else { ret = -1; } #else ioctl(kqemu_fd, KQEMU_EXEC, kenv); ret = kenv->retval; #endif if (env->cpuid_features & CPUID_FXSR) save_native_fp_fxsave(env); else save_native_fp_fsave(env); for(i = 0; i < CPU_NB_REGS; i++) env->regs[i] = kenv->regs[i]; env->eip = kenv->eip; env->eflags = kenv->eflags; for(i = 0; i < 6; i++) kqemu_save_seg(&env->segs[i], &kenv->segs[i]); cpu_x86_set_cpl(env, kenv->cpl); kqemu_save_seg(&env->ldt, &kenv->ldt); env->cr[0] = kenv->cr0; env->cr[4] = kenv->cr4; env->cr[3] = kenv->cr3; env->cr[2] = kenv->cr2; env->dr[6] = kenv->dr6; #ifdef TARGET_X86_64 env->kernelgsbase = kenv->kernelgsbase; #endif /* flush pages as indicated by kqemu */ if (kenv->nb_pages_to_flush >= KQEMU_FLUSH_ALL) { tlb_flush(env, 1); } else { for(i = 0; i < kenv->nb_pages_to_flush; i++) { tlb_flush_page(env, pages_to_flush[i]); } } nb_pages_to_flush = 0; #ifdef CONFIG_PROFILER kqemu_time += profile_getclock() - ti; kqemu_exec_count++; #endif if (kenv->nb_ram_pages_to_update > 0) { cpu_tlb_update_dirty(env); } if (kenv->nb_modified_ram_pages > 0) { for(i = 0; i < kenv->nb_modified_ram_pages; i++) { unsigned long addr; addr = modified_ram_pages[i]; tb_invalidate_phys_page_range(addr, addr + TARGET_PAGE_SIZE, 0); } } /* restore the hidden flags */ { unsigned int new_hflags; #ifdef TARGET_X86_64 if ((env->hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { /* long mode */ new_hflags = HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; } else #endif { /* legacy / compatibility case */ new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) >> (DESC_B_SHIFT - HF_CS32_SHIFT); new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> (DESC_B_SHIFT - HF_SS32_SHIFT); if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || !(env->hflags & HF_CS32_MASK)) { /* XXX: try to avoid this test. The problem comes from the fact that is real mode or vm86 mode we only modify the 'base' and 'selector' fields of the segment cache to go faster. A solution may be to force addseg to one in translate-i386.c. */ new_hflags |= HF_ADDSEG_MASK; } else { new_hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; } } env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)) | new_hflags; } /* update FPU flags */ env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | ((env->cr[0] << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)); if (env->cr[4] & CR4_OSFXSR_MASK) env->hflags |= HF_OSFXSR_MASK; else env->hflags &= ~HF_OSFXSR_MASK; LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret); if (ret == KQEMU_RET_SYSCALL) { /* syscall instruction */ return do_syscall(env, kenv); } else if ((ret & 0xff00) == KQEMU_RET_INT) { env->exception_index = ret & 0xff; env->error_code = 0; env->exception_is_int = 1; env->exception_next_eip = kenv->next_eip; #ifdef CONFIG_PROFILER kqemu_ret_int_count++; #endif LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index); LOG_INT_STATE(env); return 1; } else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) { env->exception_index = ret & 0xff; env->error_code = kenv->error_code; env->exception_is_int = 0; env->exception_next_eip = 0; #ifdef CONFIG_PROFILER kqemu_ret_excp_count++; #endif LOG_INT("kqemu: exception v=%02x e=%04x:\n", env->exception_index, env->error_code); LOG_INT_STATE(env); return 1; } else if (ret == KQEMU_RET_INTR) { #ifdef CONFIG_PROFILER kqemu_ret_intr_count++; #endif LOG_INT_STATE(env); return 0; } else if (ret == KQEMU_RET_SOFTMMU) { #ifdef CONFIG_PROFILER { unsigned long pc = env->eip + env->segs[R_CS].base; kqemu_record_pc(pc); } #endif LOG_INT_STATE(env); return 2; } else { cpu_dump_state(env, stderr, fprintf, 0); fprintf(stderr, "Unsupported return value: 0x%x\n", ret); exit(1); } return 0; }


static void cpu_handle_ioreq(void *opaque) { XenIOState *state = opaque; ioreq_t *req = cpu_get_ioreq(state); handle_buffered_iopage(state); if (req) { handle_ioreq(state, req); if (req->state != STATE_IOREQ_INPROCESS) { fprintf(stderr, "Badness in I/O request ... not in service?!: " "%x, ptr: %x, port: %"PRIx64", " "data: %"PRIx64", count: %" FMT_ioreq_size ", size: %" FMT_ioreq_size ", type: %"FMT_ioreq_size"\n", req->state, req->data_is_ptr, req->addr, req->data, req->count, req->size, req->type); destroy_hvm_domain(false); return; } xen_wmb(); /* Update ioreq contents /then/ update state. */ /* * We do this before we send the response so that the tools * have the opportunity to pick up on the reset before the * guest resumes and does a hlt with interrupts disabled which * causes Xen to powerdown the domain. */ if (runstate_is_running()) { if (qemu_shutdown_requested_get()) { destroy_hvm_domain(false); } if (qemu_reset_requested_get()) { qemu_system_reset(VMRESET_REPORT); destroy_hvm_domain(true); } } req->state = STATE_IORESP_READY; xc_evtchn_notify(state->xce_handle, state->ioreq_local_port[state->send_vcpu]); } }


int float64_is_nan( float64 a1 ) { float64u u; uint64_t a; u.f = a1; a = u.i; return ( LIT64( 0xFFF0000000000000 ) < (bits64) ( a<<1 ) ); }


uint32_t helper_efdctsf (uint64_t val) { CPU_DoubleU u; float64 tmp; u.ll = val; /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float64_is_nan(u.d))) return 0; tmp = uint64_to_float64(1ULL << 32, &env->vec_status); u.d = float64_mul(u.d, tmp, &env->vec_status); return float64_to_int32(u.d, &env->vec_status); }


static void char_socket_class_init(ObjectClass *oc, void *data) { ChardevClass *cc = CHARDEV_CLASS(oc); cc->parse = qemu_chr_parse_socket; cc->open = qmp_chardev_open_socket; cc->chr_wait_connected = tcp_chr_wait_connected; cc->chr_write = tcp_chr_write; cc->chr_sync_read = tcp_chr_sync_read; cc->chr_disconnect = tcp_chr_disconnect; cc->get_msgfds = tcp_get_msgfds; cc->set_msgfds = tcp_set_msgfds; cc->chr_add_client = tcp_chr_add_client; cc->chr_add_watch = tcp_chr_add_watch; cc->chr_update_read_handler = tcp_chr_update_read_handler; object_class_property_add(oc, "addr", "SocketAddressLegacy", char_socket_get_addr, NULL, NULL, NULL, &error_abort); object_class_property_add_bool(oc, "connected", char_socket_get_connected, NULL, &error_abort); }


static void hb_regs_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { uint32_t *regs = opaque; if (offset == 0xf00) { if (value == 1 || value == 2) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } else if (value == 3) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } } regs[offset/4] = value; }


static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr, unsigned size, bool is_write) { return is_write && size == 2; }


static ssize_t net_socket_receive(NetClientState *nc, const uint8_t *buf, size_t size) { NetSocketState *s = DO_UPCAST(NetSocketState, nc, nc); uint32_t len; len = htonl(size); send_all(s->fd, (const uint8_t *)&len, sizeof(len)); return send_all(s->fd, buf, size); }


static SocketAddress *nbd_config(BDRVNBDState *s, QDict *options, Error **errp) { SocketAddress *saddr = NULL; QDict *addr = NULL; QObject *crumpled_addr = NULL; Visitor *iv = NULL; Error *local_err = NULL; qdict_extract_subqdict(options, &addr, "server."); if (!qdict_size(addr)) { error_setg(errp, "NBD server address missing"); goto done; } crumpled_addr = qdict_crumple(addr, errp); if (!crumpled_addr) { goto done; } /* * FIXME .numeric, .to, .ipv4 or .ipv6 don't work with -drive * server.type=inet. .to doesn't matter, it's ignored anyway. * That's because when @options come from -blockdev or * blockdev_add, members are typed according to the QAPI schema, * but when they come from -drive, they're all QString. The * visitor expects the former. */ iv = qobject_input_visitor_new(crumpled_addr); visit_type_SocketAddress(iv, NULL, &saddr, &local_err); if (local_err) { error_propagate(errp, local_err); goto done; } done: QDECREF(addr); qobject_decref(crumpled_addr); visit_free(iv); return saddr; }


static int local_mkdir(FsContext *ctx, const char *path, mode_t mode) { return mkdir(rpath(ctx, path), mode); }


static int vnc_client_io_error(VncState *vs, int ret, int last_errno) { if (ret == 0 || ret == -1) { if (ret == -1) { switch (last_errno) { case EINTR: case EAGAIN: #ifdef _WIN32 case WSAEWOULDBLOCK: #endif return 0; default: break; } } VNC_DEBUG("Closing down client sock %d %d\n", ret, ret < 0 ? last_errno : 0); qemu_set_fd_handler2(vs->csock, NULL, NULL, NULL, NULL); closesocket(vs->csock); qemu_del_timer(vs->timer); qemu_free_timer(vs->timer); if (vs->input.buffer) qemu_free(vs->input.buffer); if (vs->output.buffer) qemu_free(vs->output.buffer); #ifdef CONFIG_VNC_TLS if (vs->tls_session) { gnutls_deinit(vs->tls_session); vs->tls_session = NULL; } #endif /* CONFIG_VNC_TLS */ audio_del(vs); VncState *p, *parent = NULL; for (p = vs->vd->clients; p != NULL; p = p->next) { if (p == vs) { if (parent) parent->next = p->next; else vs->vd->clients = p->next; break; } parent = p; } if (!vs->vd->clients) dcl->idle = 1; qemu_free(vs->old_data); qemu_free(vs); return 0; } return ret; }


static void qemu_event_increment(void) { /* Write 8 bytes to be compatible with eventfd. */ static const uint64_t val = 1; ssize_t ret; if (io_thread_fd == -1) return; do { ret = write(io_thread_fd, &val, sizeof(val)); } while (ret < 0 && errno == EINTR); /* EAGAIN is fine, a read must be pending. */ if (ret < 0 && errno != EAGAIN) { fprintf(stderr, "qemu_event_increment: write() filed: %s\n", strerror(errno)); exit (1); } }


static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset, unsigned size) { switch (offset) { /* Workaround to allow loading the binary-only wlandrv.ko crap * from the original Freecom firmware. */ case MP_WLAN_MAGIC1: return ~3; case MP_WLAN_MAGIC2: return -1; default: return 0; } }


static av_cold int oggvorbis_encode_close(AVCodecContext *avccontext) { OggVorbisContext *context = avccontext->priv_data; /* ogg_packet op ; */ vorbis_analysis_wrote(&context->vd, 0); /* notify vorbisenc this is EOF */ vorbis_block_clear(&context->vb); vorbis_dsp_clear(&context->vd); vorbis_info_clear(&context->vi); av_freep(&avccontext->coded_frame); av_freep(&avccontext->extradata); return 0; }


static int dxtory_decode_v2_565(AVCodecContext *avctx, AVFrame *pic, const uint8_t *src, int src_size, int is_565) { GetByteContext gb; GetBitContext gb2; int nslices, slice, slice_height; uint32_t off, slice_size; uint8_t *dst; int ret; bytestream2_init(&gb, src, src_size); nslices = bytestream2_get_le16(&gb); off = FFALIGN(nslices * 4 + 2, 16); if (src_size < off) { av_log(avctx, AV_LOG_ERROR, "no slice data\n"); return AVERROR_INVALIDDATA; } if (!nslices || avctx->height % nslices) { avpriv_request_sample(avctx, "%d slices for %dx%d", nslices, avctx->width, avctx->height); return AVERROR_PATCHWELCOME; } slice_height = avctx->height / nslices; avctx->pix_fmt = AV_PIX_FMT_RGB24; if ((ret = ff_get_buffer(avctx, pic, 0)) < 0) return ret; dst = pic->data[0]; for (slice = 0; slice < nslices; slice++) { slice_size = bytestream2_get_le32(&gb); ret = check_slice_size(avctx, src, src_size, slice_size, off); if (ret < 0) return ret; init_get_bits(&gb2, src + off + 16, (slice_size - 16) * 8); dx2_decode_slice_565(&gb2, avctx->width, slice_height, dst, pic->linesize[0], is_565); dst += pic->linesize[0] * slice_height; off += slice_size; } return 0; }


static void gen_icread(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); #else if (unlikely(ctx->pr)) { gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } /* interpreted as no-op */ #endif }


static inline void RENAME(rgb32to16)(const uint8_t *src, uint8_t *dst, long src_size) { const uint8_t *s = src; const uint8_t *end; #ifdef HAVE_MMX const uint8_t *mm_end; #endif uint16_t *d = (uint16_t *)dst; end = s + src_size; #ifdef HAVE_MMX mm_end = end - 15; #if 1 //is faster only if multiplies are reasonable fast (FIXME figure out on which cpus this is faster, on Athlon its slightly faster) asm volatile( "movq %3, %%mm5 \n\t" "movq %4, %%mm6 \n\t" "movq %5, %%mm7 \n\t" "jmp 2f \n\t" ASMALIGN(4) "1: \n\t" PREFETCH" 32(%1) \n\t" "movd (%1), %%mm0 \n\t" "movd 4(%1), %%mm3 \n\t" "punpckldq 8(%1), %%mm0 \n\t" "punpckldq 12(%1), %%mm3 \n\t" "movq %%mm0, %%mm1 \n\t" "movq %%mm3, %%mm4 \n\t" "pand %%mm6, %%mm0 \n\t" "pand %%mm6, %%mm3 \n\t" "pmaddwd %%mm7, %%mm0 \n\t" "pmaddwd %%mm7, %%mm3 \n\t" "pand %%mm5, %%mm1 \n\t" "pand %%mm5, %%mm4 \n\t" "por %%mm1, %%mm0 \n\t" "por %%mm4, %%mm3 \n\t" "psrld $5, %%mm0 \n\t" "pslld $11, %%mm3 \n\t" "por %%mm3, %%mm0 \n\t" MOVNTQ" %%mm0, (%0) \n\t" "add $16, %1 \n\t" "add $8, %0 \n\t" "2: \n\t" "cmp %2, %1 \n\t" " jb 1b \n\t" : "+r" (d), "+r"(s) : "r" (mm_end), "m" (mask3216g), "m" (mask3216br), "m" (mul3216) ); #else __asm __volatile(PREFETCH" %0"::"m"(*src):"memory"); __asm __volatile( "movq %0, %%mm7\n\t" "movq %1, %%mm6\n\t" ::"m"(red_16mask),"m"(green_16mask)); while(s < mm_end) { __asm __volatile( PREFETCH" 32%1\n\t" "movd %1, %%mm0\n\t" "movd 4%1, %%mm3\n\t" "punpckldq 8%1, %%mm0\n\t" "punpckldq 12%1, %%mm3\n\t" "movq %%mm0, %%mm1\n\t" "movq %%mm0, %%mm2\n\t" "movq %%mm3, %%mm4\n\t" "movq %%mm3, %%mm5\n\t" "psrlq $3, %%mm0\n\t" "psrlq $3, %%mm3\n\t" "pand %2, %%mm0\n\t" "pand %2, %%mm3\n\t" "psrlq $5, %%mm1\n\t" "psrlq $5, %%mm4\n\t" "pand %%mm6, %%mm1\n\t" "pand %%mm6, %%mm4\n\t" "psrlq $8, %%mm2\n\t" "psrlq $8, %%mm5\n\t" "pand %%mm7, %%mm2\n\t" "pand %%mm7, %%mm5\n\t" "por %%mm1, %%mm0\n\t" "por %%mm4, %%mm3\n\t" "por %%mm2, %%mm0\n\t" "por %%mm5, %%mm3\n\t" "psllq $16, %%mm3\n\t" "por %%mm3, %%mm0\n\t" MOVNTQ" %%mm0, %0\n\t" :"=m"(*d):"m"(*s),"m"(blue_16mask):"memory"); d += 4; s += 16; } #endif __asm __volatile(SFENCE:::"memory"); __asm __volatile(EMMS:::"memory"); #endif while(s < end) { register int rgb = *(uint32_t*)s; s += 4; *d++ = ((rgb&0xFF)>>3) + ((rgb&0xFC00)>>5) + ((rgb&0xF80000)>>8); } }


static void print_formats(AVFilterContext *filter_ctx) { int i, j; #define PRINT_FMTS(inout, outin, INOUT) \ for (i = 0; i < filter_ctx->nb_##inout##puts; i++) { \ if (filter_ctx->inout##puts[i]->type == AVMEDIA_TYPE_VIDEO) { \ AVFilterFormats *fmts = \ filter_ctx->inout##puts[i]->outin##_formats; \ for (j = 0; j < fmts->nb_formats; j++) \ if(av_get_pix_fmt_name(fmts->formats[j])) \ printf(#INOUT "PUT[%d] %s: fmt:%s\n", \ i, filter_ctx->filter->inout##puts[i].name, \ av_get_pix_fmt_name(fmts->formats[j])); \ } else if (filter_ctx->inout##puts[i]->type == AVMEDIA_TYPE_AUDIO) { \ AVFilterFormats *fmts; \ AVFilterChannelLayouts *layouts; \ \ fmts = filter_ctx->inout##puts[i]->outin##_formats; \ for (j = 0; j < fmts->nb_formats; j++) \ printf(#INOUT "PUT[%d] %s: fmt:%s\n", \ i, filter_ctx->filter->inout##puts[i].name, \ av_get_sample_fmt_name(fmts->formats[j])); \ \ layouts = filter_ctx->inout##puts[i]->outin##_channel_layouts; \ for (j = 0; j < layouts->nb_channel_layouts; j++) { \ char buf[256]; \ av_get_channel_layout_string(buf, sizeof(buf), -1, \ layouts->channel_layouts[j]); \ printf(#INOUT "PUT[%d] %s: chlayout:%s\n", \ i, filter_ctx->filter->inout##puts[i].name, buf); \ } \ } \ } \ PRINT_FMTS(in, out, IN); PRINT_FMTS(out, in, OUT); }


static void imx6_defer_clear_reset_bit(int cpuid, IMX6SRCState *s, unsigned long reset_shift) { struct SRCSCRResetInfo *ri; ri = g_malloc(sizeof(struct SRCSCRResetInfo)); ri->s = s; ri->reset_bit = reset_shift; async_run_on_cpu(arm_get_cpu_by_id(cpuid), imx6_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); }


static void fsl_imx6_realize(DeviceState *dev, Error **errp) { FslIMX6State *s = FSL_IMX6(dev); uint16_t i; Error *err = NULL; for (i = 0; i < smp_cpus; i++) { /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, "reset-cbar", &error_abort); } /* All CPU but CPU 0 start in power off mode */ if (i) { object_property_set_bool(OBJECT(&s->cpu[i]), true, "start-powered-off", &error_abort); } object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } } object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", &error_abort); object_property_set_int(OBJECT(&s->a9mpcore), FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", &error_abort); object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); for (i = 0; i < smp_cpus; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); } object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); object_property_set_bool(OBJECT(&s->src), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); /* Initialize all UARTs */ for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { static const struct { hwaddr addr; unsigned int irq; } serial_table[FSL_IMX6_NUM_UARTS] = { { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, }; if (i < MAX_SERIAL_PORTS) { Chardev *chr; chr = serial_hds[i]; if (!chr) { char *label = g_strdup_printf("imx6.uart%d", i + 1); chr = qemu_chr_new(label, "null"); g_free(label); serial_hds[i] = chr; } qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), serial_table[i].irq)); } s->gpt.ccm = IMX_CCM(&s->ccm); object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_GPT_IRQ)); /* Initialize all EPIT timers */ for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { static const struct { hwaddr addr; unsigned int irq; } epit_table[FSL_IMX6_NUM_EPITS] = { { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, }; s->epit[i].ccm = IMX_CCM(&s->ccm); object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), epit_table[i].irq)); } /* Initialize all I2C */ for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { static const struct { hwaddr addr; unsigned int irq; } i2c_table[FSL_IMX6_NUM_I2CS] = { { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } }; object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), i2c_table[i].irq)); } /* Initialize all GPIOs */ for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { static const struct { hwaddr addr; unsigned int irq_low; unsigned int irq_high; } gpio_table[FSL_IMX6_NUM_GPIOS] = { { FSL_IMX6_GPIO1_ADDR, FSL_IMX6_GPIO1_LOW_IRQ, FSL_IMX6_GPIO1_HIGH_IRQ }, { FSL_IMX6_GPIO2_ADDR, FSL_IMX6_GPIO2_LOW_IRQ, FSL_IMX6_GPIO2_HIGH_IRQ }, { FSL_IMX6_GPIO3_ADDR, FSL_IMX6_GPIO3_LOW_IRQ, FSL_IMX6_GPIO3_HIGH_IRQ }, { FSL_IMX6_GPIO4_ADDR, FSL_IMX6_GPIO4_LOW_IRQ, FSL_IMX6_GPIO4_HIGH_IRQ }, { FSL_IMX6_GPIO5_ADDR, FSL_IMX6_GPIO5_LOW_IRQ, FSL_IMX6_GPIO5_HIGH_IRQ }, { FSL_IMX6_GPIO6_ADDR, FSL_IMX6_GPIO6_LOW_IRQ, FSL_IMX6_GPIO6_HIGH_IRQ }, { FSL_IMX6_GPIO7_ADDR, FSL_IMX6_GPIO7_LOW_IRQ, FSL_IMX6_GPIO7_HIGH_IRQ }, }; object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", &error_abort); object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", &error_abort); object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), gpio_table[i].irq_low)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, qdev_get_gpio_in(DEVICE(&s->a9mpcore), gpio_table[i].irq_high)); } /* Initialize all SDHC */ for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { static const struct { hwaddr addr; unsigned int irq; } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, }; object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), esdhc_table[i].irq)); } /* Initialize all ECSPI */ for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { static const struct { hwaddr addr; unsigned int irq; } spi_table[FSL_IMX6_NUM_ECSPIS] = { { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, }; /* Initialize the SPI */ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), spi_table[i].irq)); } object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_ENET_MAC_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_ENET_MAC_1588_IRQ)); /* ROM memory */ memory_region_init_rom_nomigrate(&s->rom, NULL, "imx6.rom", FSL_IMX6_ROM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, &s->rom); /* CAAM memory */ memory_region_init_rom_nomigrate(&s->caam, NULL, "imx6.caam", FSL_IMX6_CAAM_MEM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, &s->caam); /* OCRAM memory */ memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, &s->ocram); /* internal OCRAM (256 KB) is aliased over 1 MB */ memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias", &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, &s->ocram_alias); }


static int hls_slice_data_wpp(HEVCContext *s, const uint8_t *nal, int length) { HEVCLocalContext *lc = s->HEVClc; int *ret = av_malloc_array(s->sh.num_entry_point_offsets + 1, sizeof(int)); int *arg = av_malloc_array(s->sh.num_entry_point_offsets + 1, sizeof(int)); int offset; int startheader, cmpt = 0; int i, j, res = 0; if (!s->sList[1]) { ff_alloc_entries(s->avctx, s->sh.num_entry_point_offsets + 1); for (i = 1; i < s->threads_number; i++) { s->sList[i] = av_malloc(sizeof(HEVCContext)); memcpy(s->sList[i], s, sizeof(HEVCContext)); s->HEVClcList[i] = av_mallocz(sizeof(HEVCLocalContext)); s->sList[i]->HEVClc = s->HEVClcList[i]; offset = (lc->gb.index >> 3); for (j = 0, cmpt = 0, startheader = offset + s->sh.entry_point_offset[0]; j < s->skipped_bytes; j++) { if (s->skipped_bytes_pos[j] >= offset && s->skipped_bytes_pos[j] < startheader) { startheader--; cmpt++; for (i = 1; i < s->sh.num_entry_point_offsets; i++) { offset += (s->sh.entry_point_offset[i - 1] - cmpt); for (j = 0, cmpt = 0, startheader = offset + s->sh.entry_point_offset[i]; j < s->skipped_bytes; j++) { if (s->skipped_bytes_pos[j] >= offset && s->skipped_bytes_pos[j] < startheader) { startheader--; cmpt++; s->sh.size[i - 1] = s->sh.entry_point_offset[i] - cmpt; s->sh.offset[i - 1] = offset; if (s->sh.num_entry_point_offsets != 0) { offset += s->sh.entry_point_offset[s->sh.num_entry_point_offsets - 1] - cmpt; s->sh.size[s->sh.num_entry_point_offsets - 1] = length - offset; s->sh.offset[s->sh.num_entry_point_offsets - 1] = offset; s->data = nal; for (i = 1; i < s->threads_number; i++) { s->sList[i]->HEVClc->first_qp_group = 1; s->sList[i]->HEVClc->qp_y = s->sList[0]->HEVClc->qp_y; memcpy(s->sList[i], s, sizeof(HEVCContext)); s->sList[i]->HEVClc = s->HEVClcList[i]; avpriv_atomic_int_set(&s->wpp_err, 0); ff_reset_entries(s->avctx); for (i = 0; i <= s->sh.num_entry_point_offsets; i++) { arg[i] = i; ret[i] = 0; if (s->pps->entropy_coding_sync_enabled_flag) s->avctx->execute2(s->avctx, (void *) hls_decode_entry_wpp, arg, ret, s->sh.num_entry_point_offsets + 1); for (i = 0; i <= s->sh.num_entry_point_offsets; i++) res += ret[i]; return res;


ssize_t v9fs_iov_vunmarshal(struct iovec *out_sg, int out_num, size_t offset, int bswap, const char *fmt, va_list ap) { int i; ssize_t copied = 0; size_t old_offset = offset; for (i = 0; fmt[i]; i++) { switch (fmt[i]) { case 'b': { uint8_t *valp = va_arg(ap, uint8_t *); copied = v9fs_unpack(valp, out_sg, out_num, offset, sizeof(*valp)); break; } case 'w': { uint16_t val, *valp; valp = va_arg(ap, uint16_t *); copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); if (bswap) { *valp = le16_to_cpu(val); } else { *valp = val; } break; } case 'd': { uint32_t val, *valp; valp = va_arg(ap, uint32_t *); copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); if (bswap) { *valp = le32_to_cpu(val); } else { *valp = val; } break; } case 'q': { uint64_t val, *valp; valp = va_arg(ap, uint64_t *); copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); if (bswap) { *valp = le64_to_cpu(val); } else { *valp = val; } break; } case 's': { V9fsString *str = va_arg(ap, V9fsString *); copied = v9fs_iov_unmarshal(out_sg, out_num, offset, bswap, "w", &str->size); if (copied > 0) { offset += copied; str->data = g_malloc(str->size + 1); copied = v9fs_unpack(str->data, out_sg, out_num, offset, str->size); if (copied > 0) { str->data[str->size] = 0; } else { v9fs_string_free(str); } } break; } case 'Q': { V9fsQID *qidp = va_arg(ap, V9fsQID *); copied = v9fs_iov_unmarshal(out_sg, out_num, offset, bswap, "bdq", &qidp->type, &qidp->version, &qidp->path); break; } case 'S': { V9fsStat *statp = va_arg(ap, V9fsStat *); copied = v9fs_iov_unmarshal(out_sg, out_num, offset, bswap, "wwdQdddqsssssddd", &statp->size, &statp->type, &statp->dev, &statp->qid, &statp->mode, &statp->atime, &statp->mtime, &statp->length, &statp->name, &statp->uid, &statp->gid, &statp->muid, &statp->extension, &statp->n_uid, &statp->n_gid, &statp->n_muid); break; } case 'I': { V9fsIattr *iattr = va_arg(ap, V9fsIattr *); copied = v9fs_iov_unmarshal(out_sg, out_num, offset, bswap, "ddddqqqqq", &iattr->valid, &iattr->mode, &iattr->uid, &iattr->gid, &iattr->size, &iattr->atime_sec, &iattr->atime_nsec, &iattr->mtime_sec, &iattr->mtime_nsec); break; } default: break; } if (copied < 0) { return copied; } offset += copied; } return offset - old_offset; }


static void decode_p_block(FourXContext *f, uint16_t *dst, uint16_t *src, int log2w, int log2h, int stride) { const int index = size2index[log2h][log2w]; const int h = 1 << log2h; int code = get_vlc2(&f->gb, block_type_vlc[1 - (f->version > 1)][index].table, BLOCK_TYPE_VLC_BITS, 1); uint16_t *start = (uint16_t *)f->last_picture.data[0]; uint16_t *end = start + stride * (f->avctx->height - h + 1) - (1 << log2w); av_assert2(code >= 0 && code <= 6); if (code == 0) { if (bytestream2_get_bytes_left(&f->g) < 1) { av_log(f->avctx, AV_LOG_ERROR, "bytestream overread\n"); return; } src += f->mv[bytestream2_get_byteu(&f->g)]; if (start > src || src > end) { av_log(f->avctx, AV_LOG_ERROR, "mv out of pic\n"); return; } mcdc(dst, src, log2w, h, stride, 1, 0); } else if (code == 1) { log2h--; decode_p_block(f, dst, src, log2w, log2h, stride); decode_p_block(f, dst + (stride << log2h), src + (stride << log2h), log2w, log2h, stride); } else if (code == 2) { log2w--; decode_p_block(f, dst , src, log2w, log2h, stride); decode_p_block(f, dst + (1 << log2w), src + (1 << log2w), log2w, log2h, stride); } else if (code == 3 && f->version < 2) { mcdc(dst, src, log2w, h, stride, 1, 0); } else if (code == 4) { if (bytestream2_get_bytes_left(&f->g) < 1) { av_log(f->avctx, AV_LOG_ERROR, "bytestream overread\n"); return; } src += f->mv[bytestream2_get_byteu(&f->g)]; if (start > src || src > end) { av_log(f->avctx, AV_LOG_ERROR, "mv out of pic\n"); return; } if (bytestream2_get_bytes_left(&f->g) < 2){ av_log(f->avctx, AV_LOG_ERROR, "wordstream overread\n"); return; } mcdc(dst, src, log2w, h, stride, 1, bytestream2_get_le16u(&f->g2)); } else if (code == 5) { if (bytestream2_get_bytes_left(&f->g) < 2) { av_log(f->avctx, AV_LOG_ERROR, "wordstream overread\n"); return; } mcdc(dst, src, log2w, h, stride, 0, bytestream2_get_le16u(&f->g2)); } else if (code == 6) { if (bytestream2_get_bytes_left(&f->g) < 4) { av_log(f->avctx, AV_LOG_ERROR, "wordstream overread\n"); return; } if (log2w) { dst[0] = bytestream2_get_le16u(&f->g2); dst[1] = bytestream2_get_le16u(&f->g2); } else { dst[0] = bytestream2_get_le16u(&f->g2); dst[stride] = bytestream2_get_le16u(&f->g2); } } }


static void generate_coupling_coordinates(AC3DecodeContext * ctx) { ac3_audio_block *ab = &ctx->audio_block; uint8_t exp, mstrcplco; int16_t mant; uint32_t cplbndstrc = (1 << ab->ncplsubnd) >> 1; int ch, bnd, sbnd; float cplco; if (ab->cplcoe) for (ch = 0; ch < ctx->bsi.nfchans; ch++) if (ab->cplcoe & (1 << ch)) { mstrcplco = 3 * ab->mstrcplco[ch]; sbnd = ab->cplbegf; for (bnd = 0; bnd < ab->ncplbnd; bnd++) { exp = ab->cplcoexp[ch][bnd]; if (exp == 15) mant = ab->cplcomant[ch][bnd] <<= 14; else mant = (ab->cplcomant[ch][bnd] | 0x10) << 13; cplco = to_float(exp + mstrcplco, mant); if (ctx->bsi.acmod == 0x02 && (ab->flags & AC3_AB_PHSFLGINU) && ch == 1 && (ab->phsflg & (1 << bnd))) cplco = -cplco; /* invert the right channel */ ab->cplco[ch][sbnd++] = cplco; while (cplbndstrc & ab->cplbndstrc) { cplbndstrc >>= 1; ab->cplco[ch][sbnd++] = cplco; } cplbndstrc >>= 1; } } }


static void usb_serial_event(void *opaque, int event) { USBSerialState *s = opaque; switch (event) { case CHR_EVENT_BREAK: s->event_trigger |= FTDI_BI; break; case CHR_EVENT_FOCUS: break; case CHR_EVENT_OPENED: usb_serial_reset(s); /* TODO: Reset USB port */ break; } }


static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) { gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); s->is_jmp = DISAS_TB_JUMP; }


uint32_t helper_efdctsiz (uint64_t val) { CPU_DoubleU u; u.ll = val; /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float64_is_nan(u.d))) return 0; return float64_to_int32_round_to_zero(u.d, &env->vec_status); }


static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); assert(disp == (int16_t)disp); return disp & 0xffff; }


static int update_streams_from_subdemuxer(AVFormatContext *s, struct playlist *pls) { while (pls->n_main_streams < pls->ctx->nb_streams) { int ist_idx = pls->n_main_streams; AVStream *st = avformat_new_stream(s, NULL); AVStream *ist = pls->ctx->streams[ist_idx]; if (!st) return AVERROR(ENOMEM); st->id = pls->index; set_stream_info_from_input_stream(st, pls, ist); dynarray_add(&pls->main_streams, &pls->n_main_streams, st); add_stream_to_programs(s, pls, st); } return 0; }


static uint16_t pxb_bus_numa_node(PCIBus *bus) { PXBDev *pxb = PXB_DEV(bus->parent_dev); return pxb->numa_node; }


void ptimer_run(ptimer_state *s, int oneshot) { bool was_disabled = !s->enabled; if (was_disabled && s->period == 0) { fprintf(stderr, "Timer with period zero, disabling\n"); return; } s->enabled = oneshot ? 2 : 1; if (was_disabled) { s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ptimer_reload(s); } }


static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); assert(disp == (int16_t) disp); return disp & 0xfffc; }


static void qemu_sgl_init_external(VirtIOSCSIReq *req, struct iovec *sg, hwaddr *addr, int num) { QEMUSGList *qsgl = &req->qsgl; qemu_sglist_init(qsgl, DEVICE(req->dev), num, &address_space_memory); while (num--) { qemu_sglist_add(qsgl, *(addr++), (sg++)->iov_len); } }


bool vring_setup(Vring *vring, VirtIODevice *vdev, int n) { hwaddr vring_addr = virtio_queue_get_ring_addr(vdev, n); hwaddr vring_size = virtio_queue_get_ring_size(vdev, n); void *vring_ptr; vring->broken = false; hostmem_init(&vring->hostmem); vring_ptr = hostmem_lookup(&vring->hostmem, vring_addr, vring_size, true); if (!vring_ptr) { error_report("Failed to map vring " "addr %#" HWADDR_PRIx " size %" HWADDR_PRIu, vring_addr, vring_size); vring->broken = true; return false; } vring_init(&vring->vr, virtio_queue_get_num(vdev, n), vring_ptr, 4096); vring->last_avail_idx = 0; vring->last_used_idx = 0; vring->signalled_used = 0; vring->signalled_used_valid = false; trace_vring_setup(virtio_queue_get_ring_addr(vdev, n), vring->vr.desc, vring->vr.avail, vring->vr.used); return true; }


static uint32_t drc_set_usable(sPAPRDRConnector *drc) { /* if there's no resource/device associated with the DRC, there's * no way for us to put it in an allocation state consistent with * being 'USABLE'. PAPR 2.7, 13.5.3.4 documents that this should * result in an RTAS return code of -3 / "no such indicator" */ if (!drc->dev) { return RTAS_OUT_NO_SUCH_INDICATOR; } if (drc->awaiting_release) { /* Don't allow the guest to move a device away from UNUSABLE * state when we want to unplug it */ return RTAS_OUT_NO_SUCH_INDICATOR; } drc->allocation_state = SPAPR_DR_ALLOCATION_STATE_USABLE; return RTAS_OUT_SUCCESS; }


static uint32_t gt64120_readl (void *opaque, target_phys_addr_t addr) { GT64120State *s = opaque; uint32_t val; uint32_t saddr; val = 0; saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ case GT_MULTI: /* Only one GT64xxx is present on the CPU bus, return the initial value */ val = s->regs[saddr]; break; /* CPU Error Report */ case GT_CPUERR_ADDRLO: case GT_CPUERR_ADDRHI: case GT_CPUERR_DATALO: case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: /* Emulated memory has no error, always return the initial values */ val = s->regs[saddr]; break; /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: /* Reading those register should empty all FIFO on the PCI bus, which are not emulated. The return value should be a random value that should be ignored. */ val = 0xc000ffee; break; /* ECC */ case GT_ECC_ERRDATALO: case GT_ECC_ERRDATAHI: case GT_ECC_MEM: case GT_ECC_CALC: case GT_ECC_ERRADDR: /* Emulated memory has no error, always return the initial values */ val = s->regs[saddr]; break; case GT_CPU: case GT_SCS10LD: case GT_SCS10HD: case GT_SCS32LD: case GT_SCS32HD: case GT_CS20LD: case GT_CS20HD: case GT_CS3BOOTLD: case GT_CS3BOOTHD: case GT_SCS10AR: case GT_SCS32AR: case GT_CS20R: case GT_CS3BOOTR: case GT_PCI0IOLD: case GT_PCI0M0LD: case GT_PCI0M1LD: case GT_PCI1IOLD: case GT_PCI1M0LD: case GT_PCI1M1LD: case GT_PCI0IOHD: case GT_PCI0M0HD: case GT_PCI0M1HD: case GT_PCI1IOHD: case GT_PCI1M0HD: case GT_PCI1M1HD: case GT_PCI0IOREMAP: case GT_PCI0M0REMAP: case GT_PCI0M1REMAP: case GT_PCI1IOREMAP: case GT_PCI1M0REMAP: case GT_PCI1M1REMAP: case GT_ISD: val = s->regs[saddr]; break; case GT_PCI0_IACK: /* Read the IRQ number */ val = pic_read_irq(isa_pic); break; /* SDRAM and Device Address Decode */ case GT_SCS0LD: case GT_SCS0HD: case GT_SCS1LD: case GT_SCS1HD: case GT_SCS2LD: case GT_SCS2HD: case GT_SCS3LD: case GT_SCS3HD: case GT_CS0LD: case GT_CS0HD: case GT_CS1LD: case GT_CS1HD: case GT_CS2LD: case GT_CS2HD: case GT_CS3LD: case GT_CS3HD: case GT_BOOTLD: case GT_BOOTHD: case GT_ADERR: val = s->regs[saddr]; break; /* SDRAM Configuration */ case GT_SDRAM_CFG: case GT_SDRAM_OPMODE: case GT_SDRAM_BM: case GT_SDRAM_ADDRDECODE: val = s->regs[saddr]; break; /* SDRAM Parameters */ case GT_SDRAM_B0: case GT_SDRAM_B1: case GT_SDRAM_B2: case GT_SDRAM_B3: /* We don't simulate electrical parameters of the SDRAM. Just return the last written value. */ val = s->regs[saddr]; break; /* Device Parameters */ case GT_DEV_B0: case GT_DEV_B1: case GT_DEV_B2: case GT_DEV_B3: case GT_DEV_BOOT: val = s->regs[saddr]; break; /* DMA Record */ case GT_DMA0_CNT: case GT_DMA1_CNT: case GT_DMA2_CNT: case GT_DMA3_CNT: case GT_DMA0_SA: case GT_DMA1_SA: case GT_DMA2_SA: case GT_DMA3_SA: case GT_DMA0_DA: case GT_DMA1_DA: case GT_DMA2_DA: case GT_DMA3_DA: case GT_DMA0_NEXT: case GT_DMA1_NEXT: case GT_DMA2_NEXT: case GT_DMA3_NEXT: case GT_DMA0_CUR: case GT_DMA1_CUR: case GT_DMA2_CUR: case GT_DMA3_CUR: val = s->regs[saddr]; break; /* DMA Channel Control */ case GT_DMA0_CTRL: case GT_DMA1_CTRL: case GT_DMA2_CTRL: case GT_DMA3_CTRL: val = s->regs[saddr]; break; /* DMA Arbiter */ case GT_DMA_ARB: val = s->regs[saddr]; break; /* Timer/Counter */ case GT_TC0: case GT_TC1: case GT_TC2: case GT_TC3: case GT_TC_CONTROL: val = s->regs[saddr]; break; /* PCI Internal */ case GT_PCI0_CFGADDR: val = s->pci->config_reg; break; case GT_PCI0_CFGDATA: if (!(s->pci->config_reg & (1u << 31))) val = 0xffffffff; else val = pci_host_data_readl(s->pci, 0); break; case GT_PCI0_CMD: case GT_PCI0_TOR: case GT_PCI0_BS_SCS10: case GT_PCI0_BS_SCS32: case GT_PCI0_BS_CS20: case GT_PCI0_BS_CS3BT: case GT_PCI1_IACK: case GT_PCI0_BARE: case GT_PCI0_PREFMBR: case GT_PCI0_SCS10_BAR: case GT_PCI0_SCS32_BAR: case GT_PCI0_CS20_BAR: case GT_PCI0_CS3BT_BAR: case GT_PCI0_SSCS10_BAR: case GT_PCI0_SSCS32_BAR: case GT_PCI0_SCS3BT_BAR: case GT_PCI1_CMD: case GT_PCI1_TOR: case GT_PCI1_BS_SCS10: case GT_PCI1_BS_SCS32: case GT_PCI1_BS_CS20: case GT_PCI1_BS_CS3BT: case GT_PCI1_BARE: case GT_PCI1_PREFMBR: case GT_PCI1_SCS10_BAR: case GT_PCI1_SCS32_BAR: case GT_PCI1_CS20_BAR: case GT_PCI1_CS3BT_BAR: case GT_PCI1_SSCS10_BAR: case GT_PCI1_SSCS32_BAR: case GT_PCI1_SCS3BT_BAR: case GT_PCI1_CFGADDR: case GT_PCI1_CFGDATA: val = s->regs[saddr]; break; /* Interrupts */ case GT_INTRCAUSE: val = s->regs[saddr]; dprintf("INTRCAUSE %x\n", val); break; case GT_INTRMASK: val = s->regs[saddr]; dprintf("INTRMASK %x\n", val); break; case GT_PCI0_ICMASK: val = s->regs[saddr]; dprintf("ICMASK %x\n", val); break; case GT_PCI0_SERR0MASK: val = s->regs[saddr]; dprintf("SERR0MASK %x\n", val); break; /* Reserved when only PCI_0 is configured. */ case GT_HINTRCAUSE: case GT_CPU_INTSEL: case GT_PCI0_INTSEL: case GT_HINTRMASK: case GT_PCI0_HICMASK: case GT_PCI1_SERR1MASK: val = s->regs[saddr]; break; default: val = s->regs[saddr]; dprintf ("Bad register offset 0x%x\n", (int)addr); break; } #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif return val; }


static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) { CPUX86State *env = &cpu->env; FeatureWord w; GList *l; Error *local_err = NULL; /*TODO: cpu->max_features incorrectly overwrites features * set using "feat=on|off". Once we fix this, we can convert * plus_features & minus_features to global properties * inside x86_cpu_parse_featurestr() too. */ if (cpu->max_features) { for (w = 0; w < FEATURE_WORDS; w++) { env->features[w] = x86_cpu_get_supported_feature_word(w, cpu->migratable); } } for (l = plus_features; l; l = l->next) { const char *prop = l->data; object_property_set_bool(OBJECT(cpu), true, prop, &local_err); if (local_err) { goto out; } } for (l = minus_features; l; l = l->next) { const char *prop = l->data; object_property_set_bool(OBJECT(cpu), false, prop, &local_err); if (local_err) { goto out; } } if (!kvm_enabled() || !cpu->expose_kvm) { env->features[FEAT_KVM] = 0; } x86_cpu_enable_xsave_components(cpu); /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); if (cpu->full_cpuid_auto_level) { x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ if (env->cpuid_level == UINT32_MAX) { env->cpuid_level = env->cpuid_min_level; } if (env->cpuid_xlevel == UINT32_MAX) { env->cpuid_xlevel = env->cpuid_min_xlevel; } if (env->cpuid_xlevel2 == UINT32_MAX) { env->cpuid_xlevel2 = env->cpuid_min_xlevel2; } out: if (local_err != NULL) { error_propagate(errp, local_err); } }


static BusState *qbus_find_bus(DeviceState *dev, char *elem) { BusState *child; LIST_FOREACH(child, &dev->child_bus, sibling) { if (strcmp(child->name, elem) == 0) { return child; } } return NULL; }


static inline void h264_loop_filter_luma_c(uint8_t *pix, int xstride, int ystride, int alpha, int beta, int8_t *tc0) { int i, d; for( i = 0; i < 4; i++ ) { if( tc0[i] < 0 ) { pix += 4*ystride; continue; } for( d = 0; d < 4; d++ ) { const int p0 = pix[-1*xstride]; const int p1 = pix[-2*xstride]; const int p2 = pix[-3*xstride]; const int q0 = pix[0]; const int q1 = pix[1*xstride]; const int q2 = pix[2*xstride]; if( FFABS( p0 - q0 ) < alpha && FFABS( p1 - p0 ) < beta && FFABS( q1 - q0 ) < beta ) { int tc = tc0[i]; int i_delta; if( FFABS( p2 - p0 ) < beta ) { if(tc0[i]) pix[-2*xstride] = p1 + av_clip( (( p2 + ( ( p0 + q0 + 1 ) >> 1 ) ) >> 1) - p1, -tc0[i], tc0[i] ); tc++; } if( FFABS( q2 - q0 ) < beta ) { if(tc0[i]) pix[ xstride] = q1 + av_clip( (( q2 + ( ( p0 + q0 + 1 ) >> 1 ) ) >> 1) - q1, -tc0[i], tc0[i] ); tc++; } i_delta = av_clip( (((q0 - p0 ) << 2) + (p1 - q1) + 4) >> 3, -tc, tc ); pix[-xstride] = av_clip_uint8( p0 + i_delta ); /* p0' */ pix[0] = av_clip_uint8( q0 - i_delta ); /* q0' */ } pix += ystride; } } }


static int open_f(BlockBackend *blk, int argc, char **argv) { int flags = BDRV_O_UNMAP; int readonly = 0; bool writethrough = true; int c; QemuOpts *qopts; QDict *opts; bool force_share = false; while ((c = getopt(argc, argv, "snro:kt:d:U")) != -1) { switch (c) { case 's': flags |= BDRV_O_SNAPSHOT; break; case 'n': flags |= BDRV_O_NOCACHE; writethrough = false; break; case 'r': readonly = 1; break; case 'k': flags |= BDRV_O_NATIVE_AIO; break; case 't': if (bdrv_parse_cache_mode(optarg, &flags, &writethrough) < 0) { error_report("Invalid cache option: %s", optarg); qemu_opts_reset(&empty_opts); return 0; } break; case 'd': if (bdrv_parse_discard_flags(optarg, &flags) < 0) { error_report("Invalid discard option: %s", optarg); qemu_opts_reset(&empty_opts); return 0; } break; case 'o': if (imageOpts) { printf("--image-opts and 'open -o' are mutually exclusive\n"); qemu_opts_reset(&empty_opts); return 0; } if (!qemu_opts_parse_noisily(&empty_opts, optarg, false)) { qemu_opts_reset(&empty_opts); return 0; } break; case 'U': force_share = true; break; default: qemu_opts_reset(&empty_opts); return qemuio_command_usage(&open_cmd); } } if (!readonly) { flags |= BDRV_O_RDWR; } if (imageOpts && (optind == argc - 1)) { if (!qemu_opts_parse_noisily(&empty_opts, argv[optind], false)) { qemu_opts_reset(&empty_opts); return 0; } optind++; } qopts = qemu_opts_find(&empty_opts, NULL); opts = qopts ? qemu_opts_to_qdict(qopts, NULL) : NULL; qemu_opts_reset(&empty_opts); if (optind == argc - 1) { openfile(argv[optind], flags, writethrough, force_share, opts); } else if (optind == argc) { openfile(NULL, flags, writethrough, force_share, opts); } else { QDECREF(opts); qemuio_command_usage(&open_cmd); } return 0; }


static bool iscsi_allocationmap_is_allocated(IscsiLun *iscsilun, int64_t sector_num, int nb_sectors) { unsigned long size; if (iscsilun->allocationmap == NULL) { return true; } size = DIV_ROUND_UP(sector_num + nb_sectors, iscsilun->cluster_sectors); return !(find_next_bit(iscsilun->allocationmap, size, sector_num / iscsilun->cluster_sectors) == size); }


static void disas_ldst_pair(DisasContext *s, uint32_t insn) { int rt = extract32(insn, 0, 5); int rn = extract32(insn, 5, 5); int rt2 = extract32(insn, 10, 5); int64_t offset = sextract32(insn, 15, 7); int index = extract32(insn, 23, 2); bool is_vector = extract32(insn, 26, 1); bool is_load = extract32(insn, 22, 1); int opc = extract32(insn, 30, 2); bool is_signed = false; bool postindex = false; bool wback = false; TCGv_i64 tcg_addr; /* calculated address */ int size; if (opc == 3) { unallocated_encoding(s); return; } if (is_vector) { size = 2 + opc; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); if (!is_load && is_signed) { unallocated_encoding(s); return; } } switch (index) { case 1: /* post-index */ postindex = true; wback = true; break; case 0: /* signed offset with "non-temporal" hint. Since we don't emulate * caches we don't care about hints to the cache system about * data access patterns, and handle this identically to plain * signed offset. */ if (is_signed) { /* There is no non-temporal-hint version of LDPSW */ unallocated_encoding(s); return; } postindex = false; break; case 2: /* signed offset, rn not updated */ postindex = false; break; case 3: /* pre-index */ postindex = false; wback = true; break; } if (is_vector && !fp_access_check(s)) { return; } offset <<= size; if (rn == 31) { gen_check_sp_alignment(s); } tcg_addr = read_cpu_reg_sp(s, rn, 1); if (!postindex) { tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); } if (is_vector) { if (is_load) { do_fp_ld(s, rt, tcg_addr, size); } else { do_fp_st(s, rt, tcg_addr, size); } } else { TCGv_i64 tcg_rt = cpu_reg(s, rt); if (is_load) { do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); } else { do_gpr_st(s, tcg_rt, tcg_addr, size); } } tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); if (is_vector) { if (is_load) { do_fp_ld(s, rt2, tcg_addr, size); } else { do_fp_st(s, rt2, tcg_addr, size); } } else { TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); if (is_load) { do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false); } else { do_gpr_st(s, tcg_rt2, tcg_addr, size); } } if (wback) { if (postindex) { tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); } else { tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); } tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); } }


static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, qemu_irq *irq, omap_clk clk) { int iomemtype; struct omap_rtc_s *s = (struct omap_rtc_s *) qemu_mallocz(sizeof(struct omap_rtc_s)); s->irq = irq[0]; s->alarm = irq[1]; s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); omap_rtc_reset(s); iomemtype = cpu_register_io_memory(omap_rtc_readfn, omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; }


static int mov_write_udta_tag(ByteIOContext *pb, MOVContext* mov, AVFormatContext *s) { offset_t pos = url_ftell(pb); int i; put_be32(pb, 0); /* size */ put_tag(pb, "udta"); /* iTunes meta data */ mov_write_meta_tag(pb, mov, s); if(mov->mode == MODE_MOV){ // the title field breaks gtkpod with mp4 and my suspicion is that stuff isnt valid in mp4 /* Requirements */ for (i=0; i<MAX_STREAMS; i++) { if(mov->tracks[i].entry <= 0) continue; if (mov->tracks[i].enc->codec_id == CODEC_ID_AAC || mov->tracks[i].enc->codec_id == CODEC_ID_MPEG4) { mov_write_string_tag(pb, "\251req", "QuickTime 6.0 or greater", 0); break; } } mov_write_string_tag(pb, "\251nam", s->title , 0); mov_write_string_tag(pb, "\251aut", s->author , 0); mov_write_string_tag(pb, "\251alb", s->album , 0); mov_write_day_tag(pb, s->year, 0); if(mov->tracks[0].enc && !(mov->tracks[0].enc->flags & CODEC_FLAG_BITEXACT)) mov_write_string_tag(pb, "\251enc", LIBAVFORMAT_IDENT, 0); mov_write_string_tag(pb, "\251des", s->comment , 0); mov_write_string_tag(pb, "\251gen", s->genre , 0); } return updateSize(pb, pos); }


static void selfTest(uint8_t *ref[4], int refStride[4], int w, int h) { const int flags[] = { SWS_FAST_BILINEAR, SWS_BILINEAR, SWS_BICUBIC, SWS_X , SWS_POINT , SWS_AREA, 0 }; const int srcW = w; const int srcH = h; const int dstW[] = { srcW - srcW/3, srcW, srcW + srcW/3, 0 }; const int dstH[] = { srcH - srcH/3, srcH, srcH + srcH/3, 0 }; enum PixelFormat srcFormat, dstFormat; for (srcFormat = 0; srcFormat < PIX_FMT_NB; srcFormat++) { for (dstFormat = 0; dstFormat < PIX_FMT_NB; dstFormat++) { int i, j, k; int res = 0; printf("%s -> %s\n", sws_format_name(srcFormat), sws_format_name(dstFormat)); fflush(stdout); for (i = 0; dstW[i] && !res; i++) for (j = 0; dstH[j] && !res; j++) for (k = 0; flags[k] && !res; k++) res = doTest(ref, refStride, w, h, srcFormat, dstFormat, srcW, srcH, dstW[i], dstH[j], flags[k]); } } }


static void avc_biwgt_4width_msa(uint8_t *src, int32_t src_stride, uint8_t *dst, int32_t dst_stride, int32_t height, int32_t log2_denom, int32_t src_weight, int32_t dst_weight, int32_t offset_in) { if (2 == height) { avc_biwgt_4x2_msa(src, src_stride, dst, dst_stride, log2_denom, src_weight, dst_weight, offset_in); } else { avc_biwgt_4x4multiple_msa(src, src_stride, dst, dst_stride, height, log2_denom, src_weight, dst_weight, offset_in); } }


static inline int decode_vui_parameters(GetBitContext *gb, AVCodecContext *avctx, SPS *sps) { int aspect_ratio_info_present_flag; unsigned int aspect_ratio_idc; aspect_ratio_info_present_flag = get_bits1(gb); if (aspect_ratio_info_present_flag) { aspect_ratio_idc = get_bits(gb, 8); if (aspect_ratio_idc == EXTENDED_SAR) { sps->sar.num = get_bits(gb, 16); sps->sar.den = get_bits(gb, 16); } else if (aspect_ratio_idc < FF_ARRAY_ELEMS(pixel_aspect)) { sps->sar = pixel_aspect[aspect_ratio_idc]; } else { av_log(avctx, AV_LOG_ERROR, "illegal aspect ratio\n"); return AVERROR_INVALIDDATA; } } else { sps->sar.num = sps->sar.den = 0; } if (get_bits1(gb)) /* overscan_info_present_flag */ get_bits1(gb); /* overscan_appropriate_flag */ sps->video_signal_type_present_flag = get_bits1(gb); if (sps->video_signal_type_present_flag) { get_bits(gb, 3); /* video_format */ sps->full_range = get_bits1(gb); /* video_full_range_flag */ sps->colour_description_present_flag = get_bits1(gb); if (sps->colour_description_present_flag) { sps->color_primaries = get_bits(gb, 8); /* colour_primaries */ sps->color_trc = get_bits(gb, 8); /* transfer_characteristics */ sps->colorspace = get_bits(gb, 8); /* matrix_coefficients */ if (sps->color_primaries >= AVCOL_PRI_NB) sps->color_primaries = AVCOL_PRI_UNSPECIFIED; if (sps->color_trc >= AVCOL_TRC_NB) sps->color_trc = AVCOL_TRC_UNSPECIFIED; if (sps->colorspace >= AVCOL_SPC_NB) sps->colorspace = AVCOL_SPC_UNSPECIFIED; } } /* chroma_location_info_present_flag */ if (get_bits1(gb)) { /* chroma_sample_location_type_top_field */ avctx->chroma_sample_location = get_ue_golomb(gb) + 1; get_ue_golomb(gb); /* chroma_sample_location_type_bottom_field */ } sps->timing_info_present_flag = get_bits1(gb); if (sps->timing_info_present_flag) { sps->num_units_in_tick = get_bits_long(gb, 32); sps->time_scale = get_bits_long(gb, 32); if (!sps->num_units_in_tick || !sps->time_scale) { av_log(avctx, AV_LOG_ERROR, "time_scale/num_units_in_tick invalid or unsupported (%"PRIu32"/%"PRIu32")\n", sps->time_scale, sps->num_units_in_tick); return AVERROR_INVALIDDATA; } sps->fixed_frame_rate_flag = get_bits1(gb); } sps->nal_hrd_parameters_present_flag = get_bits1(gb); if (sps->nal_hrd_parameters_present_flag) if (decode_hrd_parameters(gb, avctx, sps) < 0) return AVERROR_INVALIDDATA; sps->vcl_hrd_parameters_present_flag = get_bits1(gb); if (sps->vcl_hrd_parameters_present_flag) if (decode_hrd_parameters(gb, avctx, sps) < 0) return AVERROR_INVALIDDATA; if (sps->nal_hrd_parameters_present_flag || sps->vcl_hrd_parameters_present_flag) get_bits1(gb); /* low_delay_hrd_flag */ sps->pic_struct_present_flag = get_bits1(gb); sps->bitstream_restriction_flag = get_bits1(gb); if (sps->bitstream_restriction_flag) { get_bits1(gb); /* motion_vectors_over_pic_boundaries_flag */ get_ue_golomb(gb); /* max_bytes_per_pic_denom */ get_ue_golomb(gb); /* max_bits_per_mb_denom */ get_ue_golomb(gb); /* log2_max_mv_length_horizontal */ get_ue_golomb(gb); /* log2_max_mv_length_vertical */ sps->num_reorder_frames = get_ue_golomb(gb); get_ue_golomb(gb); /*max_dec_frame_buffering*/ if (get_bits_left(gb) < 0) { sps->num_reorder_frames = 0; sps->bitstream_restriction_flag = 0; } if (sps->num_reorder_frames > 16U /* max_dec_frame_buffering || max_dec_frame_buffering > 16 */) { av_log(avctx, AV_LOG_ERROR, "Clipping illegal num_reorder_frames %d\n", sps->num_reorder_frames); sps->num_reorder_frames = 16; return AVERROR_INVALIDDATA; } } if (get_bits_left(gb) < 0) { av_log(avctx, AV_LOG_ERROR, "Overread VUI by %d bits\n", -get_bits_left(gb)); return AVERROR_INVALIDDATA; } return 0; }


static int buffer_needs_copy(PadContext *s, AVFrame *frame, AVBufferRef *buf) { int planes[4] = { -1, -1, -1, -1}, *p = planes; int i, j; /* get all planes in this buffer */ for (i = 0; i < FF_ARRAY_ELEMS(planes) && frame->data[i]; i++) { if (av_frame_get_plane_buffer(frame, i) == buf) *p++ = i; } /* for each plane in this buffer, check that it can be padded without * going over buffer bounds or other planes */ for (i = 0; i < FF_ARRAY_ELEMS(planes) && planes[i] >= 0; i++) { int hsub = s->draw.hsub[planes[i]]; int vsub = s->draw.vsub[planes[i]]; uint8_t *start = frame->data[planes[i]]; uint8_t *end = start + (frame->height >> vsub) * frame->linesize[planes[i]]; /* amount of free space needed before the start and after the end * of the plane */ ptrdiff_t req_start = (s->x >> hsub) * s->draw.pixelstep[planes[i]] + (s->y >> vsub) * frame->linesize[planes[i]]; ptrdiff_t req_end = ((s->w - s->x - frame->width) >> hsub) * s->draw.pixelstep[planes[i]] + (s->y >> vsub) * frame->linesize[planes[i]]; if (frame->linesize[planes[i]] < (s->w >> hsub) * s->draw.pixelstep[planes[i]]) return 1; if (start - buf->data < req_start || (buf->data + buf->size) - end < req_end) return 1; for (j = 0; j < FF_ARRAY_ELEMS(planes) && planes[j] >= 0; j++) { int vsub1 = s->draw.vsub[planes[j]]; uint8_t *start1 = frame->data[planes[j]]; uint8_t *end1 = start1 + (frame->height >> vsub1) * frame->linesize[planes[j]]; if (i == j) continue; if (FFSIGN(start - end1) != FFSIGN(start - end1 - req_start) || FFSIGN(end - start1) != FFSIGN(end - start1 + req_end)) return 1; } } return 0; }


static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, unsigned size) { uint32_t val; PCIBonitoState *s = opaque; val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; return val;


static void integratorcp_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; ram_addr_t ram_offset; qemu_irq pic[32]; qemu_irq *cpu_pic; DeviceState *dev; int i; if (!cpu_model) cpu_model = "arm926"; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } ram_offset = qemu_ram_alloc(ram_size); /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero*/ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); /* And again at address 0x80000000 */ cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM); dev = qdev_create(NULL, "integrator_core"); qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); qdev_init(dev); sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("integrator_pic", 0x14000000, cpu_pic[ARM_PIC_CPU_IRQ], cpu_pic[ARM_PIC_CPU_FIQ], NULL); for (i = 0; i < 32; i++) { pic[i] = qdev_get_gpio_in(dev, i); } sysbus_create_simple("integrator_pic", 0xca000000, pic[26]); sysbus_create_varargs("integrator_pit", 0x13000000, pic[5], pic[6], pic[7], NULL); sysbus_create_simple("pl031", 0x15000000, pic[8]); sysbus_create_simple("pl011", 0x16000000, pic[1]); sysbus_create_simple("pl011", 0x17000000, pic[2]); icp_control_init(0xcb000000); sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); if (nd_table[0].vlan) smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); sysbus_create_simple("pl110", 0xc0000000, pic[22]); integrator_binfo.ram_size = ram_size; integrator_binfo.kernel_filename = kernel_filename; integrator_binfo.kernel_cmdline = kernel_cmdline; integrator_binfo.initrd_filename = initrd_filename; arm_load_kernel(env, &integrator_binfo); }


static void ich9_apm_ctrl_changed(uint32_t val, void *arg) { ICH9LPCState *lpc = arg; /* ACPI specs 3.0, 4.7.2.5 */ acpi_pm1_cnt_update(&lpc->pm.acpi_regs, val == ICH9_APM_ACPI_ENABLE, val == ICH9_APM_ACPI_DISABLE); if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { return; } /* SMI_EN = PMBASE + 30. SMI control and enable register */ if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); } }


static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s, direntry_t* direntry, const char* path) { /* * This is a little bit tricky: * IF the guest OS just inserts a cluster into the file chain, * and leaves the rest alone, (i.e. the original file had clusters * 15 -> 16, but now has 15 -> 32 -> 16), then the following happens: * * - do_commit will write the cluster into the file at the given * offset, but * * - the cluster which is overwritten should be moved to a later * position in the file. * * I am not aware that any OS does something as braindead, but this * situation could happen anyway when not committing for a long time. * Just to be sure that this does not bite us, detect it, and copy the * contents of the clusters to-be-overwritten into the qcow. */ int copy_it = 0; int was_modified = 0; int32_t ret = 0; uint32_t cluster_num = begin_of_direntry(direntry); uint32_t offset = 0; int first_mapping_index = -1; mapping_t* mapping = NULL; const char* basename2 = NULL; vvfat_close_current_file(s); /* the root directory */ if (cluster_num == 0) return 0; /* write support */ if (s->qcow) { basename2 = get_basename(path); mapping = find_mapping_for_cluster(s, cluster_num); if (mapping) { const char* basename; assert(mapping->mode & MODE_DELETED); mapping->mode &= ~MODE_DELETED; basename = get_basename(mapping->path); assert(mapping->mode & MODE_NORMAL); /* rename */ if (strcmp(basename, basename2)) schedule_rename(s, cluster_num, strdup(path)); } else if (is_file(direntry)) /* new file */ schedule_new_file(s, strdup(path), cluster_num); else { assert(0); return 0; } } while(1) { if (s->qcow) { if (!copy_it && cluster_was_modified(s, cluster_num)) { if (mapping == NULL || mapping->begin > cluster_num || mapping->end <= cluster_num) mapping = find_mapping_for_cluster(s, cluster_num); if (mapping && (mapping->mode & MODE_DIRECTORY) == 0) { /* was modified in qcow */ if (offset != mapping->info.file.offset + s->cluster_size * (cluster_num - mapping->begin)) { /* offset of this cluster in file chain has changed */ assert(0); copy_it = 1; } else if (offset == 0) { const char* basename = get_basename(mapping->path); if (strcmp(basename, basename2)) copy_it = 1; first_mapping_index = array_index(&(s->mapping), mapping); } if (mapping->first_mapping_index != first_mapping_index && mapping->info.file.offset > 0) { assert(0); copy_it = 1; } /* need to write out? */ if (!was_modified && is_file(direntry)) { was_modified = 1; schedule_writeout(s, mapping->dir_index, offset); } } } if (copy_it) { int i, dummy; /* * This is horribly inefficient, but that is okay, since * it is rarely executed, if at all. */ int64_t offset = cluster2sector(s, cluster_num); vvfat_close_current_file(s); for (i = 0; i < s->sectors_per_cluster; i++) if (!s->qcow->drv->bdrv_is_allocated(s->qcow, offset + i, 1, &dummy)) { if (vvfat_read(s->bs, offset, s->cluster_buffer, 1)) return -1; if (s->qcow->drv->bdrv_write(s->qcow, offset, s->cluster_buffer, 1)) return -2; } } } ret++; if (s->used_clusters[cluster_num] & USED_ANY) return 0; s->used_clusters[cluster_num] = USED_FILE; cluster_num = modified_fat_get(s, cluster_num); if (fat_eof(s, cluster_num)) return ret; else if (cluster_num < 2 || cluster_num > s->max_fat_value - 16) return -1; offset += s->cluster_size; } }


void visit_type_str(Visitor *v, const char *name, char **obj, Error **errp) { v->type_str(v, name, obj, errp); }


static void decode_pitch_lag_high(int *lag_int, int *lag_frac, int pitch_index, uint8_t *base_lag_int, int subframe) { if (subframe == 0 || subframe == 2) { if (pitch_index < 376) { *lag_int = (pitch_index + 137) >> 2; *lag_frac = pitch_index - (*lag_int << 2) + 136; } else if (pitch_index < 440) { *lag_int = (pitch_index + 257 - 376) >> 1; *lag_frac = (pitch_index - (*lag_int << 1) + 256 - 376) << 1; /* the actual resolution is 1/2 but expressed as 1/4 */ } else { *lag_int = pitch_index - 280; *lag_frac = 0; } /* minimum lag for next subframe */ *base_lag_int = av_clip(*lag_int - 8 - (*lag_frac < 0), AMRWB_P_DELAY_MIN, AMRWB_P_DELAY_MAX - 15); // XXX: the spec states clearly that *base_lag_int should be // the nearest integer to *lag_int (minus 8), but the ref code // actually always uses its floor, I'm following the latter } else { *lag_int = (pitch_index + 1) >> 2; *lag_frac = pitch_index - (*lag_int << 2); *lag_int += *base_lag_int; } }


static bool invalid_qmp_mode(const Monitor *mon, const char *cmd, Error **errp) { bool is_cap = g_str_equal(cmd, "qmp_capabilities"); if (is_cap && mon->qmp.in_command_mode) { error_set(errp, ERROR_CLASS_COMMAND_NOT_FOUND, "Capabilities negotiation is already complete, command " "'%s' ignored", cmd); return true; } if (!is_cap && !mon->qmp.in_command_mode) { error_set(errp, ERROR_CLASS_COMMAND_NOT_FOUND, "Expecting capabilities negotiation with " "'qmp_capabilities' before command '%s'", cmd); return true; } return false; }


static void migration_completion(MigrationState *s, int current_active_state, bool *old_vm_running, int64_t *start_time) { int ret; if (s->state == MIGRATION_STATUS_ACTIVE) { qemu_mutex_lock_iothread(); *start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME); qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); *old_vm_running = runstate_is_running(); ret = global_state_store(); if (!ret) { ret = vm_stop_force_state(RUN_STATE_FINISH_MIGRATE); if (ret >= 0) { ret = bdrv_inactivate_all(); } if (ret >= 0) { qemu_file_set_rate_limit(s->to_dst_file, INT64_MAX); qemu_savevm_state_complete_precopy(s->to_dst_file, false); } } qemu_mutex_unlock_iothread(); if (ret < 0) { goto fail; } } else if (s->state == MIGRATION_STATUS_POSTCOPY_ACTIVE) { trace_migration_completion_postcopy_end(); qemu_savevm_state_complete_postcopy(s->to_dst_file); trace_migration_completion_postcopy_end_after_complete(); } /* * If rp was opened we must clean up the thread before * cleaning everything else up (since if there are no failures * it will wait for the destination to send it's status in * a SHUT command). * Postcopy opens rp if enabled (even if it's not avtivated) */ if (migrate_postcopy_ram()) { int rp_error; trace_migration_completion_postcopy_end_before_rp(); rp_error = await_return_path_close_on_source(s); trace_migration_completion_postcopy_end_after_rp(rp_error); if (rp_error) { goto fail; } } if (qemu_file_get_error(s->to_dst_file)) { trace_migration_completion_file_err(); goto fail; } migrate_set_state(&s->state, current_active_state, MIGRATION_STATUS_COMPLETED); return; fail: migrate_set_state(&s->state, current_active_state, MIGRATION_STATUS_FAILED); }