static void blockdev_mirror_common(BlockDriverState *bs, BlockDriverState *target, bool has_replaces, const char *replaces, enum MirrorSyncMode sync, bool has_speed, int64_t speed, bool has_granularity, uint32_t granularity, bool has_buf_size, int64_t buf_size, bool has_on_source_error, BlockdevOnError on_source_error, bool has_on_target_error, BlockdevOnError on_target_error, bool has_unmap, bool unmap, Error **errp) { if (!has_speed) { speed = 0; } if (!has_on_source_error) { on_source_error = BLOCKDEV_ON_ERROR_REPORT; } if (!has_on_target_error) { on_target_error = BLOCKDEV_ON_ERROR_REPORT; } if (!has_granularity) { granularity = 0; } if (!has_buf_size) { buf_size = 0; } if (!has_unmap) { unmap = true; } if (granularity != 0 && (granularity < 512 || granularity > 1048576 * 64)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "granularity", "a value in range [512B, 64MB]"); return; } if (granularity & (granularity - 1)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "granularity", "power of 2"); return; } if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_MIRROR_SOURCE, errp)) { return; } if (bdrv_op_is_blocked(target, BLOCK_OP_TYPE_MIRROR_TARGET, errp)) { return; } if (target->blk) { error_setg(errp, "Cannot mirror to an attached block device"); return; } if (!bs->backing && sync == MIRROR_SYNC_MODE_TOP) { sync = MIRROR_SYNC_MODE_FULL; } /* pass the node name to replace to mirror start since it's loose coupling * and will allow to check whether the node still exist at mirror completion */ mirror_start(bs, target, has_replaces ? replaces : NULL, speed, granularity, buf_size, sync, on_source_error, on_target_error, unmap, block_job_cb, bs, errp); }


void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) { int num = 1; unsigned int tmp = env->tlb->nb_tlb; do { tmp >>= 1; num <<= 1; } while (tmp); env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); }


static ram_addr_t kqemu_ram_alloc(ram_addr_t size) { ram_addr_t addr; if ((last_ram_offset + size) > kqemu_phys_ram_size) { fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n", (uint64_t)size, (uint64_t)kqemu_phys_ram_size); abort(); } addr = last_ram_offset; last_ram_offset = TARGET_PAGE_ALIGN(last_ram_offset + size); return addr; }


void do_cpu_init(X86CPU *cpu) { CPUX86State *env = &cpu->env; int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI; uint64_t pat = env->pat; cpu_reset(CPU(cpu)); env->interrupt_request = sipi; env->pat = pat; apic_init_reset(env->apic_state); env->halted = !cpu_is_bsp(env); }


static inline int show_tags(WriterContext *wctx, AVDictionary *tags, int section_id) { AVDictionaryEntry *tag = NULL; int ret = 0; if (!tags) return 0; writer_print_section_header(wctx, section_id); while ((tag = av_dict_get(tags, "", tag, AV_DICT_IGNORE_SUFFIX))) { ret = writer_print_string(wctx, tag->key, tag->value, 0); if (ret < 0) break; } writer_print_section_footer(wctx); return ret; }


static void gen_dozi(DisasContext *ctx) { target_long simm = SIMM(ctx->opcode); int l1 = gen_new_label(); int l2 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); gen_set_label(l2); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); }


static inline void t_gen_swapb(TCGv d, TCGv s) { TCGv t, org_s; t = tcg_temp_new(TCG_TYPE_TL); org_s = tcg_temp_new(TCG_TYPE_TL); /* d and s may refer to the same object. */ tcg_gen_mov_tl(org_s, s); tcg_gen_shli_tl(t, org_s, 8); tcg_gen_andi_tl(d, t, 0xff00ff00); tcg_gen_shri_tl(t, org_s, 8); tcg_gen_andi_tl(t, t, 0x00ff00ff); tcg_gen_or_tl(d, d, t); tcg_temp_free(t); tcg_temp_free(org_s); }


static inline int get_symbol(RangeCoder *c, uint8_t *state, int is_signed){ if(get_rac(c, state+0)) return 0; else{ int i, e, a; e= 0; while(get_rac(c, state+1 + e)){ //1..10 e++; } assert(e<=9); a= 1; for(i=e-1; i>=0; i--){ a += a + get_rac(c, state+22 + i); //22..31 } if(is_signed && get_rac(c, state+11 + e)) //11..21 return -a; else return a; } }


static int asink_query_formats(AVFilterContext *ctx) { BufferSinkContext *buf = ctx->priv; AVFilterFormats *formats = NULL; AVFilterChannelLayouts *layouts = NULL; unsigned i; int ret; CHECK_LIST_SIZE(sample_fmts) CHECK_LIST_SIZE(sample_rates) CHECK_LIST_SIZE(channel_layouts) CHECK_LIST_SIZE(channel_counts) if (buf->sample_fmts_size) { for (i = 0; i < NB_ITEMS(buf->sample_fmts); i++) if ((ret = ff_add_format(&formats, buf->sample_fmts[i])) < 0) return ret; ff_set_common_formats(ctx, formats); } if (buf->channel_layouts_size || buf->channel_counts_size || buf->all_channel_counts) { for (i = 0; i < NB_ITEMS(buf->channel_layouts); i++) if ((ret = ff_add_channel_layout(&layouts, buf->channel_layouts[i])) < 0) return ret; for (i = 0; i < NB_ITEMS(buf->channel_counts); i++) if ((ret = ff_add_channel_layout(&layouts, FF_COUNT2LAYOUT(buf->channel_counts[i]))) < 0) return ret; if (buf->all_channel_counts) { if (layouts) av_log(ctx, AV_LOG_WARNING, "Conflicting all_channel_counts and list in options\n"); else if (!(layouts = ff_all_channel_counts())) return AVERROR(ENOMEM); } ff_set_common_channel_layouts(ctx, layouts); } if (buf->sample_rates_size) { formats = NULL; for (i = 0; i < NB_ITEMS(buf->sample_rates); i++) if ((ret = ff_add_format(&formats, buf->sample_rates[i])) < 0) return ret; ff_set_common_samplerates(ctx, formats); } return 0; }


static int mxf_read_source_package(void *arg, AVIOContext *pb, int tag, int size, UID uid) { MXFPackage *package = arg; switch(tag) { case 0x4403: package->tracks_count = avio_rb32(pb); if (package->tracks_count >= UINT_MAX / sizeof(UID)) return -1; package->tracks_refs = av_malloc(package->tracks_count * sizeof(UID)); if (!package->tracks_refs) return -1; avio_skip(pb, 4); /* useless size of objects, always 16 according to specs */ avio_read(pb, (uint8_t *)package->tracks_refs, package->tracks_count * sizeof(UID)); break; case 0x4401: /* UMID, only get last 16 bytes */ avio_skip(pb, 16); avio_read(pb, package->package_uid, 16); break; case 0x4701: avio_read(pb, package->descriptor_ref, 16); break; } return 0; }


int ff_lzf_uncompress(GetByteContext *gb, uint8_t **buf, int64_t *size) { int ret = 0; uint8_t *p = *buf; int64_t len = 0; while (bytestream2_get_bytes_left(gb) > 2) { uint8_t s = bytestream2_get_byte(gb); if (s < LZF_LITERAL_MAX) { s++; if (s > *size - len) { *size += *size /2; ret = av_reallocp(buf, *size); if (ret < 0) return ret; } bytestream2_get_buffer(gb, p, s); p += s; len += s; } else { int l = 2 + (s >> 5); int off = ((s & 0x1f) << 8) + 1; if (l == LZF_LONG_BACKREF) l += bytestream2_get_byte(gb); off += bytestream2_get_byte(gb); if (off > len) return AVERROR_INVALIDDATA; if (l > *size - len) { *size += *size / 2; ret = av_reallocp(buf, *size); if (ret < 0) return ret; } av_memcpy_backptr(p, off, l); p += l; len += l; } } *size = len; return 0; }


static int inject_fake_duration_metadata(RTMPContext *rt) { // We need to insert the metdata packet directly after the FLV // header, i.e. we need to move all other already read data by the // size of our fake metadata packet. uint8_t* p; // Keep old flv_data pointer uint8_t* old_flv_data = rt->flv_data; // Allocate a new flv_data pointer with enough space for the additional package if (!(rt->flv_data = av_malloc(rt->flv_size + 55))) { rt->flv_data = old_flv_data; return AVERROR(ENOMEM); } // Copy FLV header memcpy(rt->flv_data, old_flv_data, 13); // Copy remaining packets memcpy(rt->flv_data + 13 + 55, old_flv_data + 13, rt->flv_size - 13); // Increase the size by the injected packet rt->flv_size += 55; // Delete the old FLV data av_free(old_flv_data); p = rt->flv_data + 13; bytestream_put_byte(&p, FLV_TAG_TYPE_META); bytestream_put_be24(&p, 40); // size of data part (sum of all parts below) bytestream_put_be24(&p, 0); // timestamp bytestream_put_be32(&p, 0); // reserved // first event name as a string bytestream_put_byte(&p, AMF_DATA_TYPE_STRING); // "onMetaData" as AMF string bytestream_put_be16(&p, 10); bytestream_put_buffer(&p, "onMetaData", 10); // mixed array (hash) with size and string/type/data tuples bytestream_put_byte(&p, AMF_DATA_TYPE_MIXEDARRAY); bytestream_put_be32(&p, 1); // metadata_count // "duration" as AMF string bytestream_put_be16(&p, 8); bytestream_put_buffer(&p, "duration", 8); bytestream_put_byte(&p, AMF_DATA_TYPE_NUMBER); bytestream_put_be64(&p, av_double2int(rt->duration)); // Finalise object bytestream_put_be16(&p, 0); // Empty string bytestream_put_byte(&p, AMF_END_OF_OBJECT); bytestream_put_be32(&p, 40); // size of data part (sum of all parts below) return 0; }


static int dmg_open(BlockDriverState *bs, int flags) { BDRVDMGState *s = bs->opaque; off_t info_begin,info_end,last_in_offset,last_out_offset; uint32_t count; uint32_t max_compressed_size=1,max_sectors_per_chunk=1,i; int64_t offset; bs->read_only = 1; s->n_chunks = 0; s->offsets = s->lengths = s->sectors = s->sectorcounts = NULL; /* read offset of info blocks */ offset = bdrv_getlength(bs->file); if (offset < 0) { goto fail; } offset -= 0x1d8; info_begin = read_off(bs, offset); if (info_begin == 0) { goto fail; } if (read_uint32(bs, info_begin) != 0x100) { goto fail; } count = read_uint32(bs, info_begin + 4); if (count == 0) { goto fail; } info_end = info_begin + count; offset = info_begin + 0x100; /* read offsets */ last_in_offset = last_out_offset = 0; while (offset < info_end) { uint32_t type; count = read_uint32(bs, offset); if(count==0) goto fail; offset += 4; type = read_uint32(bs, offset); if (type == 0x6d697368 && count >= 244) { int new_size, chunk_count; offset += 4; offset += 200; chunk_count = (count-204)/40; new_size = sizeof(uint64_t) * (s->n_chunks + chunk_count); s->types = g_realloc(s->types, new_size/2); s->offsets = g_realloc(s->offsets, new_size); s->lengths = g_realloc(s->lengths, new_size); s->sectors = g_realloc(s->sectors, new_size); s->sectorcounts = g_realloc(s->sectorcounts, new_size); for(i=s->n_chunks;i<s->n_chunks+chunk_count;i++) { s->types[i] = read_uint32(bs, offset); offset += 4; if(s->types[i]!=0x80000005 && s->types[i]!=1 && s->types[i]!=2) { if(s->types[i]==0xffffffff) { last_in_offset = s->offsets[i-1]+s->lengths[i-1]; last_out_offset = s->sectors[i-1]+s->sectorcounts[i-1]; } chunk_count--; i--; offset += 36; continue; } offset += 4; s->sectors[i] = last_out_offset+read_off(bs, offset); offset += 8; s->sectorcounts[i] = read_off(bs, offset); offset += 8; s->offsets[i] = last_in_offset+read_off(bs, offset); offset += 8; s->lengths[i] = read_off(bs, offset); offset += 8; if(s->lengths[i]>max_compressed_size) max_compressed_size = s->lengths[i]; if(s->sectorcounts[i]>max_sectors_per_chunk) max_sectors_per_chunk = s->sectorcounts[i]; } s->n_chunks+=chunk_count; } } /* initialize zlib engine */ s->compressed_chunk = g_malloc(max_compressed_size+1); s->uncompressed_chunk = g_malloc(512*max_sectors_per_chunk); if(inflateInit(&s->zstream) != Z_OK) goto fail; s->current_chunk = s->n_chunks; qemu_co_mutex_init(&s->lock); return 0; fail: return -1; }


static int ac3_decode_frame(AVCodecContext * avctx, void *data, int *data_size, const uint8_t *buf, int buf_size) { AC3DecodeContext *s = avctx->priv_data; int16_t *out_samples = (int16_t *)data; int i, blk, ch, err; /* initialize the GetBitContext with the start of valid AC-3 Frame */ if (s->input_buffer) { /* copy input buffer to decoder context to avoid reading past the end of the buffer, which can be caused by a damaged input stream. */ memcpy(s->input_buffer, buf, FFMIN(buf_size, AC3_MAX_FRAME_SIZE)); init_get_bits(&s->gbc, s->input_buffer, buf_size * 8); } else { init_get_bits(&s->gbc, buf, buf_size * 8); } /* parse the syncinfo */ err = ac3_parse_header(s); if(err) { switch(err) { case AC3_PARSE_ERROR_SYNC: av_log(avctx, AV_LOG_ERROR, "frame sync error : cannot use error concealment\n"); return -1; case AC3_PARSE_ERROR_BSID: av_log(avctx, AV_LOG_ERROR, "invalid bitstream id\n"); break; case AC3_PARSE_ERROR_SAMPLE_RATE: av_log(avctx, AV_LOG_ERROR, "invalid sample rate\n"); break; case AC3_PARSE_ERROR_FRAME_SIZE: av_log(avctx, AV_LOG_ERROR, "invalid frame size\n"); break; case AC3_PARSE_ERROR_FRAME_TYPE: av_log(avctx, AV_LOG_ERROR, "invalid frame type\n"); break; default: av_log(avctx, AV_LOG_ERROR, "invalid header\n"); break; } } /* check that reported frame size fits in input buffer */ if(s->frame_size > buf_size) { av_log(avctx, AV_LOG_ERROR, "incomplete frame\n"); return -1; } /* check for crc mismatch */ if(!err && avctx->error_resilience >= FF_ER_CAREFUL) { if(av_crc(av_crc_get_table(AV_CRC_16_ANSI), 0, &buf[2], s->frame_size-2)) { av_log(avctx, AV_LOG_ERROR, "frame CRC mismatch\n"); err = 1; } } /* if frame is ok, set audio parameters */ if (!err) { avctx->sample_rate = s->sample_rate; avctx->bit_rate = s->bit_rate; /* channel config */ s->out_channels = s->channels; s->output_mode = s->channel_mode; if(s->lfe_on) s->output_mode |= AC3_OUTPUT_LFEON; if (avctx->request_channels > 0 && avctx->request_channels <= 2 && avctx->request_channels < s->channels) { s->out_channels = avctx->request_channels; s->output_mode = avctx->request_channels == 1 ? AC3_CHMODE_MONO : AC3_CHMODE_STEREO; } avctx->channels = s->out_channels; /* set downmixing coefficients if needed */ if(s->channels != s->out_channels && !((s->output_mode & AC3_OUTPUT_LFEON) && s->fbw_channels == s->out_channels)) { set_downmix_coeffs(s); } } else if (!s->out_channels) { s->out_channels = avctx->channels; if(s->out_channels < s->channels) s->output_mode = s->out_channels == 1 ? AC3_CHMODE_MONO : AC3_CHMODE_STEREO; } /* parse the audio blocks */ for (blk = 0; blk < NB_BLOCKS; blk++) { if (!err && ac3_parse_audio_block(s, blk)) { av_log(avctx, AV_LOG_ERROR, "error parsing the audio block\n"); } for (i = 0; i < 256; i++) for (ch = 0; ch < s->out_channels; ch++) *(out_samples++) = s->int_output[ch][i]; } *data_size = NB_BLOCKS * 256 * avctx->channels * sizeof (int16_t); return s->frame_size; }


static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) { PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); SerialState *s; Error *err = NULL; int i; switch (pc->device_id) { case 0x0003: pci->ports = 2; break; case 0x0004: pci->ports = 4; break; } assert(pci->ports > 0); assert(pci->ports <= PCI_SERIAL_MAX_PORTS); pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports); pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, pci->ports); for (i = 0; i < pci->ports; i++) { s = pci->state + i; s->baudbase = 115200; serial_realize_core(s, &err); if (err != NULL) { error_propagate(errp, err); return; } s->irq = pci->irqs[i]; pci->name[i] = g_strdup_printf("uart #%d", i+1); memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, pci->name[i], 8); memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); } }


int ff_h264_decode_picture_parameter_set(H264Context *h, int bit_length){ MpegEncContext * const s = &h->s; unsigned int pps_id= get_ue_golomb(&s->gb); PPS *pps; const int qp_bd_offset = 6*(h->sps.bit_depth_luma-8); int bits_left; if(pps_id >= MAX_PPS_COUNT) { av_log(h->s.avctx, AV_LOG_ERROR, "pps_id (%d) out of range\n", pps_id); return -1; } pps= av_mallocz(sizeof(PPS)); if(pps == NULL) return -1; pps->sps_id= get_ue_golomb_31(&s->gb); if((unsigned)pps->sps_id>=MAX_SPS_COUNT || h->sps_buffers[pps->sps_id] == NULL){ av_log(h->s.avctx, AV_LOG_ERROR, "sps_id out of range\n"); goto fail; } pps->cabac= get_bits1(&s->gb); pps->pic_order_present= get_bits1(&s->gb); pps->slice_group_count= get_ue_golomb(&s->gb) + 1; if(pps->slice_group_count > 1 ){ pps->mb_slice_group_map_type= get_ue_golomb(&s->gb); av_log(h->s.avctx, AV_LOG_ERROR, "FMO not supported\n"); switch(pps->mb_slice_group_map_type){ case 0: #if 0 | for( i = 0; i <= num_slice_groups_minus1; i++ ) | | | | run_length[ i ] |1 |ue(v) | #endif break; case 2: #if 0 | for( i = 0; i < num_slice_groups_minus1; i++ ) | | | |{ | | | | top_left_mb[ i ] |1 |ue(v) | | bottom_right_mb[ i ] |1 |ue(v) | | } | | | #endif break; case 3: case 4: case 5: #if 0 | slice_group_change_direction_flag |1 |u(1) | | slice_group_change_rate_minus1 |1 |ue(v) | #endif break; case 6: #if 0 | slice_group_id_cnt_minus1 |1 |ue(v) | | for( i = 0; i <= slice_group_id_cnt_minus1; i++ | | | |) | | | | slice_group_id[ i ] |1 |u(v) | #endif break; } } pps->ref_count[0]= get_ue_golomb(&s->gb) + 1; pps->ref_count[1]= get_ue_golomb(&s->gb) + 1; if(pps->ref_count[0]-1 > 32-1 || pps->ref_count[1]-1 > 32-1){ av_log(h->s.avctx, AV_LOG_ERROR, "reference overflow (pps)\n"); goto fail; } pps->weighted_pred= get_bits1(&s->gb); pps->weighted_bipred_idc= get_bits(&s->gb, 2); pps->init_qp= get_se_golomb(&s->gb) + 26 + qp_bd_offset; pps->init_qs= get_se_golomb(&s->gb) + 26 + qp_bd_offset; pps->chroma_qp_index_offset[0]= get_se_golomb(&s->gb); pps->deblocking_filter_parameters_present= get_bits1(&s->gb); pps->constrained_intra_pred= get_bits1(&s->gb); pps->redundant_pic_cnt_present = get_bits1(&s->gb); pps->transform_8x8_mode= 0; h->dequant_coeff_pps= -1; //contents of sps/pps can change even if id doesn't, so reinit memcpy(pps->scaling_matrix4, h->sps_buffers[pps->sps_id]->scaling_matrix4, sizeof(pps->scaling_matrix4)); memcpy(pps->scaling_matrix8, h->sps_buffers[pps->sps_id]->scaling_matrix8, sizeof(pps->scaling_matrix8)); bits_left = bit_length - get_bits_count(&s->gb); if (bits_left && (bits_left > 8 || show_bits(&s->gb, bits_left) != 1 << (bits_left - 1))) { pps->transform_8x8_mode= get_bits1(&s->gb); decode_scaling_matrices(h, h->sps_buffers[pps->sps_id], pps, 0, pps->scaling_matrix4, pps->scaling_matrix8); pps->chroma_qp_index_offset[1]= get_se_golomb(&s->gb); //second_chroma_qp_index_offset } else { pps->chroma_qp_index_offset[1]= pps->chroma_qp_index_offset[0]; } build_qp_table(pps, 0, pps->chroma_qp_index_offset[0], h->sps.bit_depth_luma); build_qp_table(pps, 1, pps->chroma_qp_index_offset[1], h->sps.bit_depth_luma); if(pps->chroma_qp_index_offset[0] != pps->chroma_qp_index_offset[1]) pps->chroma_qp_diff= 1; if(s->avctx->debug&FF_DEBUG_PICT_INFO){ av_log(h->s.avctx, AV_LOG_DEBUG, "pps:%u sps:%u %s slice_groups:%d ref:%d/%d %s qp:%d/%d/%d/%d %s %s %s %s\n", pps_id, pps->sps_id, pps->cabac ? "CABAC" : "CAVLC", pps->slice_group_count, pps->ref_count[0], pps->ref_count[1], pps->weighted_pred ? "weighted" : "", pps->init_qp, pps->init_qs, pps->chroma_qp_index_offset[0], pps->chroma_qp_index_offset[1], pps->deblocking_filter_parameters_present ? "LPAR" : "", pps->constrained_intra_pred ? "CONSTR" : "", pps->redundant_pic_cnt_present ? "REDU" : "", pps->transform_8x8_mode ? "8x8DCT" : "" ); } av_free(h->pps_buffers[pps_id]); h->pps_buffers[pps_id]= pps; return 0; fail: av_free(pps); return -1; }


int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, hwaddr rtas_size) { int ret; int i; ret = fdt_add_mem_rsv(fdt, rtas_addr, rtas_size); if (ret < 0) { fprintf(stderr, "Couldn't add RTAS reserve entry: %s\n", fdt_strerror(ret)); return ret; } ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-base", rtas_addr); if (ret < 0) { fprintf(stderr, "Couldn't add linux,rtas-base property: %s\n", fdt_strerror(ret)); return ret; } ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-entry", rtas_addr); if (ret < 0) { fprintf(stderr, "Couldn't add linux,rtas-entry property: %s\n", fdt_strerror(ret)); return ret; } ret = qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", rtas_size); if (ret < 0) { fprintf(stderr, "Couldn't add rtas-size property: %s\n", fdt_strerror(ret)); return ret; } for (i = 0; i < TOKEN_MAX; i++) { struct rtas_call *call = &rtas_table[i]; if (!call->name) { continue; } ret = qemu_fdt_setprop_cell(fdt, "/rtas", call->name, i + TOKEN_BASE); if (ret < 0) { fprintf(stderr, "Couldn't add rtas token for %s: %s\n", call->name, fdt_strerror(ret)); return ret; } } return 0; }


static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type, int is_user, hwaddr *phys_ptr, int *prot) { int n; uint32_t mask; uint32_t base; *phys_ptr = address; for (n = 7; n >= 0; n--) { base = env->cp15.c6_region[n]; if ((base & 1) == 0) continue; mask = 1 << ((base >> 1) & 0x1f); /* Keep this shift separate from the above to avoid an (undefined) << 32. */ mask = (mask << 1) - 1; if (((base ^ address) & ~mask) == 0) break; } if (n < 0) return 2; if (access_type == 2) { mask = env->cp15.c5_insn; } else { mask = env->cp15.c5_data; } mask = (mask >> (n * 4)) & 0xf; switch (mask) { case 0: return 1; case 1: if (is_user) return 1; *prot = PAGE_READ | PAGE_WRITE; break; case 2: *prot = PAGE_READ; if (!is_user) *prot |= PAGE_WRITE; break; case 3: *prot = PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) return 1; *prot = PAGE_READ; break; case 6: *prot = PAGE_READ; break; default: /* Bad permission. */ return 1; } *prot |= PAGE_EXEC; return 0; }


static int huff_build(VLC *vlc, uint8_t *len) { HuffEntry he[256]; uint32_t codes[256]; uint8_t bits[256]; uint8_t syms[256]; uint32_t code; int i; for (i = 0; i < 256; i++) { he[i].sym = 255 - i; he[i].len = len[i]; if (len[i] == 0) return AVERROR_INVALIDDATA; } AV_QSORT(he, 256, HuffEntry, huff_cmp_len); code = 1; for (i = 255; i >= 0; i--) { codes[i] = code >> (32 - he[i].len); bits[i] = he[i].len; syms[i] = he[i].sym; code += 0x80000000u >> (he[i].len - 1); } ff_free_vlc(vlc); return ff_init_vlc_sparse(vlc, FFMIN(he[255].len, 12), 256, bits, sizeof(*bits), sizeof(*bits), codes, sizeof(*codes), sizeof(*codes), syms, sizeof(*syms), sizeof(*syms), 0); }


static int get_cox(Jpeg2000DecoderContext *s, Jpeg2000CodingStyle *c) { uint8_t byte; if (s->buf_end - s->buf < 5) return AVERROR(EINVAL); /* nreslevels = number of resolution levels = number of decomposition level +1 */ c->nreslevels = bytestream_get_byte(&s->buf) + 1; if (c->nreslevels > JPEG2000_MAX_RESLEVELS) return AVERROR_INVALIDDATA; /* compute number of resolution levels to decode */ if (c->nreslevels < s->reduction_factor) c->nreslevels2decode = 1; else c->nreslevels2decode = c->nreslevels - s->reduction_factor; c->log2_cblk_width = bytestream_get_byte(&s->buf) + 2; // cblk width c->log2_cblk_height = bytestream_get_byte(&s->buf) + 2; // cblk height if (c->log2_cblk_width > 10 || c->log2_cblk_height > 10 || c->log2_cblk_width + c->log2_cblk_height > 12) { av_log(s->avctx, AV_LOG_ERROR, "cblk size invalid\n"); return AVERROR_INVALIDDATA; } c->cblk_style = bytestream_get_byte(&s->buf); if (c->cblk_style != 0) { // cblk style avpriv_request_sample(s->avctx, "Support for extra cblk styles"); return AVERROR_PATCHWELCOME; } c->transform = bytestream_get_byte(&s->buf); // DWT transformation type /* set integer 9/7 DWT in case of BITEXACT flag */ if ((s->avctx->flags & CODEC_FLAG_BITEXACT) && (c->transform == FF_DWT97)) c->transform = FF_DWT97_INT; if (c->csty & JPEG2000_CSTY_PREC) { int i; for (i = 0; i < c->nreslevels; i++) { byte = bytestream_get_byte(&s->buf); c->log2_prec_widths[i] = byte & 0x0F; // precinct PPx c->log2_prec_heights[i] = (byte >> 4) & 0x0F; // precinct PPy } } return 0; }


void qemu_clock_warp(QEMUClockType type) { int64_t deadline; /* * There are too many global variables to make the "warp" behavior * applicable to other clocks. But a clock argument removes the * need for if statements all over the place. */ if (type != QEMU_CLOCK_VIRTUAL || !use_icount) { return; } /* * If the CPUs have been sleeping, advance QEMU_CLOCK_VIRTUAL timer now. * This ensures that the deadline for the timer is computed correctly below. * This also makes sure that the insn counter is synchronized before the * CPU starts running, in case the CPU is woken by an event other than * the earliest QEMU_CLOCK_VIRTUAL timer. */ icount_warp_rt(NULL); if (!all_cpu_threads_idle() || !qemu_clock_has_timers(QEMU_CLOCK_VIRTUAL)) { timer_del(icount_warp_timer); return; } if (qtest_enabled()) { /* When testing, qtest commands advance icount. */ return; } vm_clock_warp_start = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); /* We want to use the earliest deadline from ALL vm_clocks */ deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); /* Maintain prior (possibly buggy) behaviour where if no deadline * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than * INT32_MAX nanoseconds ahead, we still use INT32_MAX * nanoseconds. */ if ((deadline < 0) || (deadline > INT32_MAX)) { deadline = INT32_MAX; } if (deadline > 0) { /* * Ensure QEMU_CLOCK_VIRTUAL proceeds even when the virtual CPU goes to * sleep. Otherwise, the CPU might be waiting for a future timer * interrupt to wake it up, but the interrupt never comes because * the vCPU isn't running any insns and thus doesn't advance the * QEMU_CLOCK_VIRTUAL. * * An extreme solution for this problem would be to never let VCPUs * sleep in icount mode if there is a pending QEMU_CLOCK_VIRTUAL * timer; rather time could just advance to the next QEMU_CLOCK_VIRTUAL * event. Instead, we do stop VCPUs and only advance QEMU_CLOCK_VIRTUAL * after some e"real" time, (related to the time left until the next * event) has passed. The QEMU_CLOCK_REALTIME timer will do this. * This avoids that the warps are visible externally; for example, * you will not be sending network packets continuously instead of * every 100ms. */ timer_mod(icount_warp_timer, vm_clock_warp_start + deadline); } else if (deadline == 0) { qemu_clock_notify(QEMU_CLOCK_VIRTUAL); } }


void qpci_plug_device_test(const char *driver, const char *id, uint8_t slot, const char *opts) { QDict *response; char *cmd; cmd = g_strdup_printf("{'execute': 'device_add'," " 'arguments': {" " 'driver': '%s'," " 'addr': '%d'," " %s%s" " 'id': '%s'" "}}", driver, slot, opts ? opts : "", opts ? "," : "", id); response = qmp(cmd); g_free(cmd); g_assert(response); g_assert(!qdict_haskey(response, "error")); QDECREF(response); }


void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { bool ret; uint32_t fsr = 0; ARMMMUFaultInfo fi = {}; ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t syn, exc; unsigned int target_el; bool same_el; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } target_el = exception_target_el(env); if (fi.stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; } same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */ syn = fsr & ~(1 << 9); /* For insn and data aborts we assume there is no instruction syndrome * information; this is always true for exceptions reported to EL1. */ if (is_write == 2) { syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn); exc = EXCP_PREFETCH_ABORT; } else { syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn); if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { fsr |= (1 << 11); } exc = EXCP_DATA_ABORT; } env->exception.vaddress = addr; env->exception.fsr = fsr; raise_exception(env, exc, syn, target_el); } }


static int local_fstat(FsContext *fs_ctx, int fd, struct stat *stbuf) { int err; err = fstat(fd, stbuf); if (err) { return err; } if (fs_ctx->fs_sm == SM_MAPPED) { /* Actual credentials are part of extended attrs */ uid_t tmp_uid; gid_t tmp_gid; mode_t tmp_mode; dev_t tmp_dev; if (fgetxattr(fd, "user.virtfs.uid", &tmp_uid, sizeof(uid_t)) > 0) { stbuf->st_uid = tmp_uid; } if (fgetxattr(fd, "user.virtfs.gid", &tmp_gid, sizeof(gid_t)) > 0) { stbuf->st_gid = tmp_gid; } if (fgetxattr(fd, "user.virtfs.mode", &tmp_mode, sizeof(mode_t)) > 0) { stbuf->st_mode = tmp_mode; } if (fgetxattr(fd, "user.virtfs.rdev", &tmp_dev, sizeof(dev_t)) > 0) { stbuf->st_rdev = tmp_dev; } } return err; }


static void test_visitor_in_native_list_int8(TestInputVisitorData *data, const void *unused) { test_native_list_integer_helper(data, unused, USER_DEF_NATIVE_LIST_UNION_KIND_S8); }


static void xen_platform_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { PCIXenPlatformState *s = opaque; PCIDevice *pci_dev = PCI_DEVICE(s); switch (addr) { case 0: /* Platform flags */ platform_fixed_ioport_writeb(opaque, 0, (uint32_t)val); break; case 4: if (val == 1) { /* * SUSE unplug for Xenlinux * xen-kmp used this since xen-3.0.4, instead the official protocol * from xen-3.3+ It did an unconditional "outl(1, (ioaddr + 4));" * Pre VMDP 1.7 used 4 and 8 depending on how VMDP was configured. * If VMDP was to control both disk and LAN it would use 4. * If it controlled just disk or just LAN, it would use 8 below. */ pci_unplug_disks(pci_dev->bus); pci_unplug_nics(pci_dev->bus); } break; case 8: switch (val) { case 1: pci_unplug_disks(pci_dev->bus); break; case 2: pci_unplug_nics(pci_dev->bus); break; default: log_writeb(s, (uint32_t)val); break; } break; default: break; } }


void ff_thread_release_buffer(AVCodecContext *avctx, ThreadFrame *f) { PerThreadContext *p = avctx->internal->thread_ctx; FrameThreadContext *fctx; AVFrame *dst, *tmp; FF_DISABLE_DEPRECATION_WARNINGS int can_direct_free = !(avctx->active_thread_type & FF_THREAD_FRAME) || avctx->thread_safe_callbacks || ( #if FF_API_GET_BUFFER !avctx->get_buffer && #endif avctx->get_buffer2 == avcodec_default_get_buffer2); FF_ENABLE_DEPRECATION_WARNINGS if (!f->f->data[0]) return; if (avctx->debug & FF_DEBUG_BUFFERS) av_log(avctx, AV_LOG_DEBUG, "thread_release_buffer called on pic %p\n", f); av_buffer_unref(&f->progress); f->owner = NULL; if (can_direct_free) { av_frame_unref(f->f); return; } fctx = p->parent; pthread_mutex_lock(&fctx->buffer_mutex); if (p->num_released_buffers + 1 >= INT_MAX / sizeof(*p->released_buffers)) goto fail; tmp = av_fast_realloc(p->released_buffers, &p->released_buffers_allocated, (p->num_released_buffers + 1) * sizeof(*p->released_buffers)); if (!tmp) goto fail; p->released_buffers = tmp; dst = &p->released_buffers[p->num_released_buffers]; av_frame_move_ref(dst, f->f); p->num_released_buffers++; fail: pthread_mutex_unlock(&fctx->buffer_mutex); }


static int count_contiguous_clusters_by_type(int nb_clusters, uint64_t *l2_table, int wanted_type) { int i; for (i = 0; i < nb_clusters; i++) { int type = qcow2_get_cluster_type(be64_to_cpu(l2_table[i])); if (type != wanted_type) { break; } } return i; }


static void scsi_disk_emulate_mode_select(SCSIDiskReq *r, uint8_t *inbuf) { SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, r->req.dev); uint8_t *p = inbuf; int cmd = r->req.cmd.buf[0]; int len = r->req.cmd.xfer; int hdr_len = (cmd == MODE_SELECT ? 4 : 8); int bd_len; int pass; /* We only support PF=1, SP=0. */ if ((r->req.cmd.buf[1] & 0x11) != 0x10) { goto invalid_field; } if (len < hdr_len) { goto invalid_param_len; } bd_len = (cmd == MODE_SELECT ? p[3] : lduw_be_p(&p[6])); len -= hdr_len; p += hdr_len; if (len < bd_len) { goto invalid_param_len; } if (bd_len != 0 && bd_len != 8) { goto invalid_param; } len -= bd_len; p += bd_len; /* Ensure no change is made if there is an error! */ for (pass = 0; pass < 2; pass++) { if (mode_select_pages(r, p, len, pass == 1) < 0) { assert(pass == 0); return; } } if (!bdrv_enable_write_cache(s->qdev.conf.bs)) { /* The request is used as the AIO opaque value, so add a ref. */ scsi_req_ref(&r->req); block_acct_start(bdrv_get_stats(s->qdev.conf.bs), &r->acct, 0, BLOCK_ACCT_FLUSH); r->req.aiocb = bdrv_aio_flush(s->qdev.conf.bs, scsi_aio_complete, r); return; } scsi_req_complete(&r->req, GOOD); return; invalid_param: scsi_check_condition(r, SENSE_CODE(INVALID_PARAM)); return; invalid_param_len: scsi_check_condition(r, SENSE_CODE(INVALID_PARAM_LEN)); return; invalid_field: scsi_check_condition(r, SENSE_CODE(INVALID_FIELD)); }


int32 float32_to_int32_round_to_zero( float32 a STATUS_PARAM ) { flag aSign; int16 aExp, shiftCount; bits32 aSig; int32 z; aSig = extractFloat32Frac( a ); aExp = extractFloat32Exp( a ); aSign = extractFloat32Sign( a ); shiftCount = aExp - 0x9E; if ( 0 <= shiftCount ) { if ( a != 0xCF000000 ) { float_raise( float_flag_invalid STATUS_VAR); if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF; } return (sbits32) 0x80000000; } else if ( aExp <= 0x7E ) { if ( aExp | aSig ) STATUS(float_exception_flags) |= float_flag_inexact; return 0; } aSig = ( aSig | 0x00800000 )<<8; z = aSig>>( - shiftCount ); if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) { STATUS(float_exception_flags) |= float_flag_inexact; } if ( aSign ) z = - z; return z; }


QEMUFile *qemu_popen_cmd(const char *command, const char *mode) { FILE *stdio_file; QEMUFileStdio *s; stdio_file = popen(command, mode); if (stdio_file == NULL) { return NULL; } if (mode == NULL || (mode[0] != 'r' && mode[0] != 'w') || mode[1] != 0) { fprintf(stderr, "qemu_popen: Argument validity check failed\n"); return NULL; } s = g_malloc0(sizeof(QEMUFileStdio)); s->stdio_file = stdio_file; if(mode[0] == 'r') { s->file = qemu_fopen_ops(s, &stdio_pipe_read_ops); } else { s->file = qemu_fopen_ops(s, &stdio_pipe_write_ops); } return s->file; }


static int openpic_load(QEMUFile* f, void *opaque, int version_id) { OpenPICState *opp = (OpenPICState *)opaque; unsigned int i; if (version_id != 1) return -EINVAL; qemu_get_be32s(f, &opp->glbc); qemu_get_be32s(f, &opp->veni); qemu_get_be32s(f, &opp->pint); qemu_get_be32s(f, &opp->spve); qemu_get_be32s(f, &opp->tifr); for (i = 0; i < opp->max_irq; i++) { qemu_get_be32s(f, &opp->src[i].ipvp); qemu_get_be32s(f, &opp->src[i].ide); qemu_get_sbe32s(f, &opp->src[i].last_cpu); qemu_get_sbe32s(f, &opp->src[i].pending); } qemu_get_be32s(f, &opp->nb_cpus); for (i = 0; i < opp->nb_cpus; i++) { qemu_get_be32s(f, &opp->dst[i].pctp); qemu_get_be32s(f, &opp->dst[i].pcsr); openpic_load_IRQ_queue(f, &opp->dst[i].raised); openpic_load_IRQ_queue(f, &opp->dst[i].servicing); } for (i = 0; i < MAX_TMR; i++) { qemu_get_be32s(f, &opp->timers[i].ticc); qemu_get_be32s(f, &opp->timers[i].tibc); } return 0; }


uint64_t HELPER(abs_i64)(int64_t val) { HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val); if (val < 0) { return -val; } else { return val; } }


void blk_resume_after_migration(Error **errp) { BlockBackend *blk; Error *local_err = NULL; for (blk = blk_all_next(NULL); blk; blk = blk_all_next(blk)) { if (!blk->disable_perm) { continue; } blk->disable_perm = false; blk_set_perm(blk, blk->perm, blk->shared_perm, &local_err); if (local_err) { error_propagate(errp, local_err); blk->disable_perm = true; return; } } }


static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) { VFIOGroup *group; struct vfio_pci_hot_reset_info *info; struct vfio_pci_dependent_device *devices; struct vfio_pci_hot_reset *reset; int32_t *fds; int ret, i, count; bool multi = false; trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); vfio_pci_pre_reset(vdev); vdev->vbasedev.needs_reset = false; info = g_malloc0(sizeof(*info)); info->argsz = sizeof(*info); ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); if (ret && errno != ENOSPC) { ret = -errno; if (!vdev->has_pm_reset) { error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, " "no available reset mechanism.", vdev->host.domain, vdev->host.bus, vdev->host.slot, vdev->host.function); } goto out_single; } count = info->count; info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); info->argsz = sizeof(*info) + (count * sizeof(*devices)); devices = &info->devices[0]; ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); if (ret) { ret = -errno; error_report("vfio: hot reset info failed: %m"); goto out_single; } trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); /* Verify that we have all the groups required */ for (i = 0; i < info->count; i++) { PCIHostDeviceAddress host; VFIOPCIDevice *tmp; VFIODevice *vbasedev_iter; host.domain = devices[i].segment; host.bus = devices[i].bus; host.slot = PCI_SLOT(devices[i].devfn); host.function = PCI_FUNC(devices[i].devfn); trace_vfio_pci_hot_reset_dep_devices(host.domain, host.bus, host.slot, host.function, devices[i].group_id); if (vfio_pci_host_match(&host, &vdev->host)) { continue; } QLIST_FOREACH(group, &vfio_group_list, next) { if (group->groupid == devices[i].group_id) { break; } } if (!group) { if (!vdev->has_pm_reset) { error_report("vfio: Cannot reset device %s, " "depends on group %d which is not owned.", vdev->vbasedev.name, devices[i].group_id); } ret = -EPERM; goto out; } /* Prep dependent devices for reset and clear our marker. */ QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { continue; } tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); if (vfio_pci_host_match(&host, &tmp->host)) { if (single) { ret = -EINVAL; goto out_single; } vfio_pci_pre_reset(tmp); tmp->vbasedev.needs_reset = false; multi = true; break; } } } if (!single && !multi) { ret = -EINVAL; goto out_single; } /* Determine how many group fds need to be passed */ count = 0; QLIST_FOREACH(group, &vfio_group_list, next) { for (i = 0; i < info->count; i++) { if (group->groupid == devices[i].group_id) { count++; break; } } } reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); fds = &reset->group_fds[0]; /* Fill in group fds */ QLIST_FOREACH(group, &vfio_group_list, next) { for (i = 0; i < info->count; i++) { if (group->groupid == devices[i].group_id) { fds[reset->count++] = group->fd; break; } } } /* Bus reset! */ ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); g_free(reset); trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, ret ? "%m" : "Success"); out: /* Re-enable INTx on affected devices */ for (i = 0; i < info->count; i++) { PCIHostDeviceAddress host; VFIOPCIDevice *tmp; VFIODevice *vbasedev_iter; host.domain = devices[i].segment; host.bus = devices[i].bus; host.slot = PCI_SLOT(devices[i].devfn); host.function = PCI_FUNC(devices[i].devfn); if (vfio_pci_host_match(&host, &vdev->host)) { continue; } QLIST_FOREACH(group, &vfio_group_list, next) { if (group->groupid == devices[i].group_id) { break; } } if (!group) { break; } QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { continue; } tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); if (vfio_pci_host_match(&host, &tmp->host)) { vfio_pci_post_reset(tmp); break; } } } out_single: vfio_pci_post_reset(vdev); g_free(info); return ret; }


pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) { uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx); if (ready_ptr != mgr->consumed_ptr) { uint32_t next_ready_ptr = mgr->consumed_ptr++ & mgr->txr_len_mask; uint32_t next_ready_page = next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; uint32_t inpage_idx = next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; return mgr->req_ring_pages_pa[next_ready_page] + inpage_idx * sizeof(PVSCSIRingReqDesc); } else { return 0; } }


int nbd_receive_negotiate(QIOChannel *ioc, const char *name, uint32_t *flags, QCryptoTLSCreds *tlscreds, const char *hostname, QIOChannel **outioc, off_t *size, Error **errp) { char buf[256]; uint64_t magic, s; int rc; TRACE("Receiving negotiation tlscreds=%p hostname=%s.", tlscreds, hostname ? hostname : "<null>"); rc = -EINVAL; if (outioc) { *outioc = NULL; } if (tlscreds && !outioc) { error_setg(errp, "Output I/O channel required for TLS"); goto fail; } if (read_sync(ioc, buf, 8) != 8) { error_setg(errp, "Failed to read data"); goto fail; } buf[8] = '\0'; if (strlen(buf) == 0) { error_setg(errp, "Server connection closed unexpectedly"); goto fail; } TRACE("Magic is %c%c%c%c%c%c%c%c", qemu_isprint(buf[0]) ? buf[0] : '.', qemu_isprint(buf[1]) ? buf[1] : '.', qemu_isprint(buf[2]) ? buf[2] : '.', qemu_isprint(buf[3]) ? buf[3] : '.', qemu_isprint(buf[4]) ? buf[4] : '.', qemu_isprint(buf[5]) ? buf[5] : '.', qemu_isprint(buf[6]) ? buf[6] : '.', qemu_isprint(buf[7]) ? buf[7] : '.'); if (memcmp(buf, "NBDMAGIC", 8) != 0) { error_setg(errp, "Invalid magic received"); goto fail; } if (read_sync(ioc, &magic, sizeof(magic)) != sizeof(magic)) { error_setg(errp, "Failed to read magic"); goto fail; } magic = be64_to_cpu(magic); TRACE("Magic is 0x%" PRIx64, magic); if (magic == NBD_OPTS_MAGIC) { uint32_t clientflags = 0; uint32_t opt; uint32_t namesize; uint16_t globalflags; uint16_t exportflags; bool fixedNewStyle = false; if (read_sync(ioc, &globalflags, sizeof(globalflags)) != sizeof(globalflags)) { error_setg(errp, "Failed to read server flags"); goto fail; } globalflags = be16_to_cpu(globalflags); *flags = globalflags << 16; TRACE("Global flags are %" PRIx32, globalflags); if (globalflags & NBD_FLAG_FIXED_NEWSTYLE) { fixedNewStyle = true; TRACE("Server supports fixed new style"); clientflags |= NBD_FLAG_C_FIXED_NEWSTYLE; } /* client requested flags */ clientflags = cpu_to_be32(clientflags); if (write_sync(ioc, &clientflags, sizeof(clientflags)) != sizeof(clientflags)) { error_setg(errp, "Failed to send clientflags field"); goto fail; } if (tlscreds) { if (fixedNewStyle) { *outioc = nbd_receive_starttls(ioc, tlscreds, hostname, errp); if (!*outioc) { goto fail; } ioc = *outioc; } else { error_setg(errp, "Server does not support STARTTLS"); goto fail; } } if (!name) { TRACE("Using default NBD export name \"\""); name = ""; } if (fixedNewStyle) { /* Check our desired export is present in the * server export list. Since NBD_OPT_EXPORT_NAME * cannot return an error message, running this * query gives us good error reporting if the * server required TLS */ if (nbd_receive_query_exports(ioc, name, errp) < 0) { goto fail; } } /* write the export name */ magic = cpu_to_be64(magic); if (write_sync(ioc, &magic, sizeof(magic)) != sizeof(magic)) { error_setg(errp, "Failed to send export name magic"); goto fail; } opt = cpu_to_be32(NBD_OPT_EXPORT_NAME); if (write_sync(ioc, &opt, sizeof(opt)) != sizeof(opt)) { error_setg(errp, "Failed to send export name option number"); goto fail; } namesize = cpu_to_be32(strlen(name)); if (write_sync(ioc, &namesize, sizeof(namesize)) != sizeof(namesize)) { error_setg(errp, "Failed to send export name length"); goto fail; } if (write_sync(ioc, (char *)name, strlen(name)) != strlen(name)) { error_setg(errp, "Failed to send export name"); goto fail; } if (read_sync(ioc, &s, sizeof(s)) != sizeof(s)) { error_setg(errp, "Failed to read export length"); goto fail; } *size = be64_to_cpu(s); TRACE("Size is %" PRIu64, *size); if (read_sync(ioc, &exportflags, sizeof(exportflags)) != sizeof(exportflags)) { error_setg(errp, "Failed to read export flags"); goto fail; } exportflags = be16_to_cpu(exportflags); *flags |= exportflags; TRACE("Export flags are %" PRIx16, exportflags); } else if (magic == NBD_CLIENT_MAGIC) { if (name) { error_setg(errp, "Server does not support export names"); goto fail; } if (tlscreds) { error_setg(errp, "Server does not support STARTTLS"); goto fail; } if (read_sync(ioc, &s, sizeof(s)) != sizeof(s)) { error_setg(errp, "Failed to read export length"); goto fail; } *size = be64_to_cpu(s); TRACE("Size is %" PRIu64, *size); if (read_sync(ioc, flags, sizeof(*flags)) != sizeof(*flags)) { error_setg(errp, "Failed to read export flags"); goto fail; } *flags = be32_to_cpu(*flags); } else { error_setg(errp, "Bad magic received"); goto fail; } if (read_sync(ioc, &buf, 124) != 124) { error_setg(errp, "Failed to read reserved block"); goto fail; } rc = 0; fail: return rc; }


SCSIRequest *scsi_req_new(SCSIDevice *d, uint32_t tag, uint32_t lun, uint8_t *buf, void *hba_private) { SCSIRequest *req; req = d->info->alloc_req(d, tag, lun, hba_private); memcpy(req->cmd.buf, buf, 16); return req; }


int qemu_read_password(char *buf, int buf_size) { uint8_t ch; int i, ret; printf("password: "); fflush(stdout); term_init(); i = 0; for (;;) { ret = read(0, &ch, 1); if (ret == -1) { if (errno == EAGAIN || errno == EINTR) { continue; } else { break; } } else if (ret == 0) { ret = -1; break; } else { if (ch == '\r') { ret = 0; break; } if (i < (buf_size - 1)) { buf[i++] = ch; } } } term_exit(); buf[i] = '\0'; printf("\n"); return ret; }


static void qemu_account_warp_timer(void) { if (!use_icount || !icount_sleep) { return; } /* Nothing to do if the VM is stopped: QEMU_CLOCK_VIRTUAL timers * do not fire, so computing the deadline does not make sense. */ if (!runstate_is_running()) { return; } /* warp clock deterministically in record/replay mode */ if (!replay_checkpoint(CHECKPOINT_CLOCK_WARP_ACCOUNT)) { return; } timer_del(icount_warp_timer); icount_warp_rt(); }


int host_to_target_signal(int sig) { if (sig >= _NSIG) return sig; return host_to_target_signal_table[sig]; }


void process_pending_signals(CPUArchState *cpu_env) { CPUState *cpu = ENV_GET_CPU(cpu_env); int sig; abi_ulong handler; sigset_t set, old_set; target_sigset_t target_old_set; struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; TaskState *ts = cpu->opaque; if (!ts->signal_pending) return; /* FIXME: This is not threadsafe. */ k = ts->sigtab; for(sig = 1; sig <= TARGET_NSIG; sig++) { if (k->pending) goto handle_signal; k++; } /* if no signal is pending, just return */ ts->signal_pending = 0; return; handle_signal: #ifdef DEBUG_SIGNAL fprintf(stderr, "qemu: process signal %d\n", sig); #endif /* dequeue signal */ q = k->first; k->first = q->next; if (!k->first) k->pending = 0; sig = gdb_handlesig(cpu, sig); if (!sig) { sa = NULL; handler = TARGET_SIG_IGN; } else { sa = &sigact_table[sig - 1]; handler = sa->_sa_handler; } if (handler == TARGET_SIG_DFL) { /* default handler : ignore some signal. The other are job control or fatal */ if (sig == TARGET_SIGTSTP || sig == TARGET_SIGTTIN || sig == TARGET_SIGTTOU) { kill(getpid(),SIGSTOP); } else if (sig != TARGET_SIGCHLD && sig != TARGET_SIGURG && sig != TARGET_SIGWINCH && sig != TARGET_SIGCONT) { force_sig(sig); } } else if (handler == TARGET_SIG_IGN) { /* ignore sig */ } else if (handler == TARGET_SIG_ERR) { force_sig(sig); } else { /* compute the blocked signals during the handler execution */ target_to_host_sigset(&set, &sa->sa_mask); /* SA_NODEFER indicates that the current signal should not be blocked during the handler */ if (!(sa->sa_flags & TARGET_SA_NODEFER)) sigaddset(&set, target_to_host_signal(sig)); /* block signals in the handler using Linux */ sigprocmask(SIG_BLOCK, &set, &old_set); /* save the previous blocked signal state to restore it at the end of the signal execution (see do_sigreturn) */ host_to_target_sigset_internal(&target_old_set, &old_set); /* if the CPU is in VM86 mode, we restore the 32 bit values */ #if defined(TARGET_I386) && !defined(TARGET_X86_64) { CPUX86State *env = cpu_env; if (env->eflags & VM_MASK) save_v86_state(env); } #endif /* prepare the stack frame of the virtual CPU */ #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) /* These targets do not have traditional signals. */ setup_rt_frame(sig, sa, &q->info, &target_old_set, cpu_env); #else if (sa->sa_flags & TARGET_SA_SIGINFO) setup_rt_frame(sig, sa, &q->info, &target_old_set, cpu_env); else setup_frame(sig, sa, &target_old_set, cpu_env); #endif if (sa->sa_flags & TARGET_SA_RESETHAND) sa->_sa_handler = TARGET_SIG_DFL; } if (q != &k->info) free_sigqueue(cpu_env, q); }


static void handle_stream_probing(AVStream *st) { if (st->codec->codec_id == AV_CODEC_ID_PCM_S16LE) { st->request_probe = AVPROBE_SCORE_EXTENSION; st->probe_packets = FFMIN(st->probe_packets, 14); } }


int avcodec_close(AVCodecContext *avctx) { /* If there is a user-supplied mutex locking routine, call it. */ if (ff_lockmgr_cb) { if ((*ff_lockmgr_cb)(&codec_mutex, AV_LOCK_OBTAIN)) return -1; } entangled_thread_counter++; if(entangled_thread_counter != 1){ av_log(avctx, AV_LOG_ERROR, "insufficient thread locking around avcodec_open/close()\n"); entangled_thread_counter--; return -1; } if (HAVE_THREADS && avctx->thread_opaque) avcodec_thread_free(avctx); if (avctx->codec->close) avctx->codec->close(avctx); avcodec_default_free_buffers(avctx); av_freep(&avctx->priv_data); avctx->codec = NULL; entangled_thread_counter--; /* Release any user-supplied mutex. */ if (ff_lockmgr_cb) { (*ff_lockmgr_cb)(&codec_mutex, AV_LOCK_RELEASE); } return 0; }


static int a52_decode_frame(AVCodecContext *avctx, void *data, int *data_size, uint8_t *buf, int buf_size) { AC3DecodeState *s = avctx->priv_data; uint8_t *buf_ptr; int flags, i, len; int sample_rate, bit_rate; short *out_samples = data; float level; static const int ac3_channels[8] = { 2, 1, 2, 3, 3, 4, 4, 5 }; *data_size= 0; buf_ptr = buf; while (buf_size > 0) { len = s->inbuf_ptr - s->inbuf; if (s->frame_size == 0) { /* no header seen : find one. We need at least 7 bytes to parse it */ len = HEADER_SIZE - len; if (len > buf_size) len = buf_size; memcpy(s->inbuf_ptr, buf_ptr, len); buf_ptr += len; s->inbuf_ptr += len; buf_size -= len; if ((s->inbuf_ptr - s->inbuf) == HEADER_SIZE) { len = s->a52_syncinfo(s->inbuf, &s->flags, &sample_rate, &bit_rate); if (len == 0) { /* no sync found : move by one byte (inefficient, but simple!) */ memcpy(s->inbuf, s->inbuf + 1, HEADER_SIZE - 1); s->inbuf_ptr--; } else { s->frame_size = len; /* update codec info */ avctx->sample_rate = sample_rate; s->channels = ac3_channels[s->flags & 7]; if (s->flags & A52_LFE) s->channels++; avctx->channels = s->channels; if (avctx->request_channels > 0 && avctx->request_channels <= 2 && avctx->request_channels < s->channels) { avctx->channels = avctx->request_channels; } avctx->bit_rate = bit_rate; } } } else if (len < s->frame_size) { len = s->frame_size - len; if (len > buf_size) len = buf_size; memcpy(s->inbuf_ptr, buf_ptr, len); buf_ptr += len; s->inbuf_ptr += len; buf_size -= len; } else { flags = s->flags; if (avctx->channels == 1) flags = A52_MONO; else if (avctx->channels == 2) flags = A52_STEREO; else flags |= A52_ADJUST_LEVEL; level = 1; if (s->a52_frame(s->state, s->inbuf, &flags, &level, 384)) { fail: av_log(avctx, AV_LOG_ERROR, "Error decoding frame\n"); s->inbuf_ptr = s->inbuf; s->frame_size = 0; continue; } for (i = 0; i < 6; i++) { if (s->a52_block(s->state)) goto fail; float_to_int(s->samples, out_samples + i * 256 * avctx->channels, avctx->channels); } s->inbuf_ptr = s->inbuf; s->frame_size = 0; *data_size = 6 * avctx->channels * 256 * sizeof(int16_t); break; } } return buf_ptr - buf; }


static int get_packetheader(NUTContext *nut, ByteIOContext *bc, int calculate_checksum) { int64_t start, size; start= url_ftell(bc) - 8; init_checksum(bc, calculate_checksum ? update_adler32 : NULL, 0); size= get_v(bc); nut->packet_start[2] = start; nut->written_packet_size= size; return size; }


static void rtsp_close_streams(RTSPState *rt) { int i; RTSPStream *rtsp_st; for(i=0;i<rt->nb_rtsp_streams;i++) { rtsp_st = rt->rtsp_streams[i]; if (rtsp_st) { if (rtsp_st->transport_priv) { if (rt->transport == RTSP_TRANSPORT_RDT) ff_rdt_parse_close(rtsp_st->transport_priv); else rtp_parse_close(rtsp_st->transport_priv); } if (rtsp_st->rtp_handle) url_close(rtsp_st->rtp_handle); if (rtsp_st->dynamic_handler && rtsp_st->dynamic_protocol_context) rtsp_st->dynamic_handler->close(rtsp_st->dynamic_protocol_context); } } av_free(rt->rtsp_streams); if (rt->asf_ctx) { av_close_input_stream (rt->asf_ctx); rt->asf_ctx = NULL; } av_freep(&rt->auth_b64); }


static uint32_t drc_isolate_logical(sPAPRDRConnector *drc) { /* if the guest is configuring a device attached to this DRC, we * should reset the configuration state at this point since it may * no longer be reliable (guest released device and needs to start * over, or unplug occurred so the FDT is no longer valid) */ g_free(drc->ccs); drc->ccs = NULL; /* * Fail any requests to ISOLATE the LMB DRC if this LMB doesn't * belong to a DIMM device that is marked for removal. * * Currently the guest userspace tool drmgr that drives the memory * hotplug/unplug will just try to remove a set of 'removable' LMBs * in response to a hot unplug request that is based on drc-count. * If the LMB being removed doesn't belong to a DIMM device that is * actually being unplugged, fail the isolation request here. */ if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB && !drc->unplug_requested) { return RTAS_OUT_HW_ERROR; } drc->isolation_state = SPAPR_DR_ISOLATION_STATE_ISOLATED; /* if we're awaiting release, but still in an unconfigured state, * it's likely the guest is still in the process of configuring * the device and is transitioning the devices to an ISOLATED * state as a part of that process. so we only complete the * removal when this transition happens for a device in a * configured state, as suggested by the state diagram from PAPR+ * 2.7, 13.4 */ if (drc->unplug_requested) { uint32_t drc_index = spapr_drc_index(drc); if (drc->configured) { trace_spapr_drc_set_isolation_state_finalizing(drc_index); spapr_drc_detach(drc); } else { trace_spapr_drc_set_isolation_state_deferring(drc_index); } } drc->configured = false; return RTAS_OUT_SUCCESS; }


static void compat_free_buffer(void *opaque, uint8_t *data) { CompatReleaseBufPriv *priv = opaque; priv->avctx.release_buffer(&priv->avctx, &priv->frame); av_freep(&priv); }


static int aio_write_f(BlockBackend *blk, int argc, char **argv) { int nr_iov, c; int pattern = 0xcd; struct aio_ctx *ctx = g_new0(struct aio_ctx, 1); int flags = 0; ctx->blk = blk; while ((c = getopt(argc, argv, "CfqP:uz")) != -1) { switch (c) { case 'C': ctx->Cflag = true; break; case 'f': flags |= BDRV_REQ_FUA; break; case 'q': ctx->qflag = true; break; case 'u': flags |= BDRV_REQ_MAY_UNMAP; break; case 'P': pattern = parse_pattern(optarg); if (pattern < 0) { g_free(ctx); return 0; } break; case 'z': ctx->zflag = true; break; default: g_free(ctx); return qemuio_command_usage(&aio_write_cmd); } } if (optind > argc - 2) { g_free(ctx); return qemuio_command_usage(&aio_write_cmd); } if (ctx->zflag && optind != argc - 2) { printf("-z supports only a single length parameter\n"); g_free(ctx); return 0; } if ((flags & BDRV_REQ_MAY_UNMAP) && !ctx->zflag) { printf("-u requires -z to be specified\n"); g_free(ctx); return 0; } if (ctx->zflag && ctx->Pflag) { printf("-z and -P cannot be specified at the same time\n"); g_free(ctx); return 0; } ctx->offset = cvtnum(argv[optind]); if (ctx->offset < 0) { print_cvtnum_err(ctx->offset, argv[optind]); g_free(ctx); return 0; } optind++; if (ctx->zflag) { int64_t count = cvtnum(argv[optind]); if (count < 0) { print_cvtnum_err(count, argv[optind]); g_free(ctx); return 0; } ctx->qiov.size = count; blk_aio_write_zeroes(blk, ctx->offset, count, flags, aio_write_done, ctx); } else { nr_iov = argc - optind; ctx->buf = create_iovec(blk, &ctx->qiov, &argv[optind], nr_iov, pattern); if (ctx->buf == NULL) { block_acct_invalid(blk_get_stats(blk), BLOCK_ACCT_WRITE); g_free(ctx); return 0; } gettimeofday(&ctx->t1, NULL); block_acct_start(blk_get_stats(blk), &ctx->acct, ctx->qiov.size, BLOCK_ACCT_WRITE); blk_aio_pwritev(blk, ctx->offset, &ctx->qiov, flags, aio_write_done, ctx); } return 0; }


void *g_malloc_n(size_t nmemb, size_t size) { size_t sz; void *ptr; __coverity_negative_sink__(nmemb); __coverity_negative_sink__(size); sz = nmemb * size; ptr = __coverity_alloc__(size); __coverity_mark_as_uninitialized_buffer__(ptr); __coverity_mark_as_afm_allocated__(ptr, AFM_free); return ptr; }


int i2c_recv(I2CBus *bus) { I2CSlaveClass *sc; if ((QLIST_EMPTY(&bus->current_devs)) || (bus->broadcast)) { return -1; } sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt); if (sc->recv) { return sc->recv(QLIST_FIRST(&bus->current_devs)->elt); } return -1; }


static int spapr_vga_init(PCIBus *pci_bus) { switch (vga_interface_type) { case VGA_STD: pci_std_vga_init(pci_bus); return 1; case VGA_NONE: return 0; default: fprintf(stderr, "This vga model is not supported," "currently it only supports -vga std\n"); exit(0); break; } }


static void thread_pool_init_one(ThreadPool *pool, AioContext *ctx) { if (!ctx) { ctx = qemu_get_aio_context(); } memset(pool, 0, sizeof(*pool)); event_notifier_init(&pool->notifier, false); pool->ctx = ctx; qemu_mutex_init(&pool->lock); qemu_cond_init(&pool->check_cancel); qemu_cond_init(&pool->worker_stopped); qemu_sem_init(&pool->sem, 0); pool->max_threads = 64; pool->new_thread_bh = aio_bh_new(ctx, spawn_thread_bh_fn, pool); QLIST_INIT(&pool->head); QTAILQ_INIT(&pool->request_list); aio_set_event_notifier(ctx, &pool->notifier, event_notifier_ready); }


static always_inline void gen_cmov (TCGCond inv_cond, int ra, int rb, int rc, int islit, uint8_t lit, int mask) { int l1; if (unlikely(rc == 31)) return; l1 = gen_new_label(); if (ra != 31) { if (mask) { TCGv tmp = tcg_temp_new(TCG_TYPE_I64); tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); tcg_temp_free(tmp); } else tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1); } else { /* Very uncommon case - Do not bother to optimize. */ TCGv tmp = tcg_const_i64(0); tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); tcg_temp_free(tmp); } if (islit) tcg_gen_movi_i64(cpu_ir[rc], lit); else tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); gen_set_label(l1); }


static int process_tns_coeffs(TemporalNoiseShaping *tns, float *tns_coefs_raw, int order, int w, int filt) { int i, j; int *idx = tns->coef_idx[w][filt]; float *lpc = tns->coef[w][filt]; const int iqfac_p = ((1 << (MAX_LPC_PRECISION-1)) - 0.5)/(M_PI/2.0); const int iqfac_m = ((1 << (MAX_LPC_PRECISION-1)) + 0.5)/(M_PI/2.0); float temp[TNS_MAX_ORDER] = {0.0f}, out[TNS_MAX_ORDER] = {0.0f}; /* Quantization */ for (i = 0; i < order; i++) { idx[i] = ceilf(asin(tns_coefs_raw[i])*((tns_coefs_raw[i] >= 0) ? iqfac_p : iqfac_m)); lpc[i] = 2*sin(idx[i]/((idx[i] >= 0) ? iqfac_p : iqfac_m)); } /* Trim any coeff less than 0.1f from the end */ for (i = order; i > -1; i--) { lpc[i] = (fabs(lpc[i]) > 0.1f) ? lpc[i] : 0.0f; if (lpc[i] != 0.0 ) { order = i; break; } } if (!order) return 0; /* Step up procedure, convert to LPC coeffs */ out[0] = 1.0f; for (i = 1; i <= order; i++) { for (j = 1; j < i; j++) { temp[j] = out[j] + lpc[i]*out[i-j]; } for (j = 1; j <= i; j++) { out[j] = temp[j]; } out[i] = lpc[i-1]; } memcpy(lpc, out, TNS_MAX_ORDER*sizeof(float)); return order; }


static inline void downmix_3f_to_stereo(float *samples) { int i; for (i = 0; i < 256; i++) { samples[i] += samples[i + 256]; samples[i + 256] = samples[i + 512]; samples[i + 512] = 0; } }


static int vfio_set_resample_eventfd(VFIOINTp *intp) { VFIODevice *vbasedev = &intp->vdev->vbasedev; struct vfio_irq_set *irq_set; int argsz, ret; int32_t *pfd; argsz = sizeof(*irq_set) + sizeof(*pfd); irq_set = g_malloc0(argsz); irq_set->argsz = argsz; irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; irq_set->index = intp->pin; irq_set->start = 0; irq_set->count = 1; pfd = (int32_t *)&irq_set->data; *pfd = event_notifier_get_fd(&intp->unmask); qemu_set_fd_handler(*pfd, NULL, NULL, NULL); ret = ioctl(vbasedev->fd, VFIO_DEVICE_SET_IRQS, irq_set); g_free(irq_set); if (ret < 0) { error_report("vfio: Failed to set resample eventfd: %m"); } return ret; }


static void test_io_channel_unix_fd_pass(void) { SocketAddress *listen_addr = g_new0(SocketAddress, 1); SocketAddress *connect_addr = g_new0(SocketAddress, 1); QIOChannel *src, *dst; int testfd; int fdsend[3]; int *fdrecv = NULL; size_t nfdrecv = 0; size_t i; char bufsend[12], bufrecv[12]; struct iovec iosend[1], iorecv[1]; #define TEST_SOCKET "test-io-channel-socket.sock" #define TEST_FILE "test-io-channel-socket.txt" testfd = open(TEST_FILE, O_RDWR|O_TRUNC|O_CREAT, 0700); g_assert(testfd != -1); fdsend[0] = testfd; fdsend[1] = testfd; fdsend[2] = testfd; listen_addr->type = SOCKET_ADDRESS_KIND_UNIX; listen_addr->u.q_unix.data = g_new0(UnixSocketAddress, 1); listen_addr->u.q_unix.data->path = g_strdup(TEST_SOCKET); connect_addr->type = SOCKET_ADDRESS_KIND_UNIX; connect_addr->u.q_unix.data = g_new0(UnixSocketAddress, 1); connect_addr->u.q_unix.data->path = g_strdup(TEST_SOCKET); test_io_channel_setup_sync(listen_addr, connect_addr, &src, &dst); memcpy(bufsend, "Hello World", G_N_ELEMENTS(bufsend)); iosend[0].iov_base = bufsend; iosend[0].iov_len = G_N_ELEMENTS(bufsend); iorecv[0].iov_base = bufrecv; iorecv[0].iov_len = G_N_ELEMENTS(bufrecv); g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS)); g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS)); qio_channel_writev_full(src, iosend, G_N_ELEMENTS(iosend), fdsend, G_N_ELEMENTS(fdsend), &error_abort); qio_channel_readv_full(dst, iorecv, G_N_ELEMENTS(iorecv), &fdrecv, &nfdrecv, &error_abort); g_assert(nfdrecv == G_N_ELEMENTS(fdsend)); /* Each recvd FD should be different from sent FD */ for (i = 0; i < nfdrecv; i++) { g_assert_cmpint(fdrecv[i], !=, testfd); } /* Each recvd FD should be different from each other */ g_assert_cmpint(fdrecv[0], !=, fdrecv[1]); g_assert_cmpint(fdrecv[0], !=, fdrecv[2]); g_assert_cmpint(fdrecv[1], !=, fdrecv[2]); /* Check the I/O buf we sent at the same time matches */ g_assert(memcmp(bufsend, bufrecv, G_N_ELEMENTS(bufsend)) == 0); /* Write some data into the FD we received */ g_assert(write(fdrecv[0], bufsend, G_N_ELEMENTS(bufsend)) == G_N_ELEMENTS(bufsend)); /* Read data from the original FD and make sure it matches */ memset(bufrecv, 0, G_N_ELEMENTS(bufrecv)); g_assert(lseek(testfd, 0, SEEK_SET) == 0); g_assert(read(testfd, bufrecv, G_N_ELEMENTS(bufrecv)) == G_N_ELEMENTS(bufrecv)); g_assert(memcmp(bufsend, bufrecv, G_N_ELEMENTS(bufsend)) == 0); object_unref(OBJECT(src)); object_unref(OBJECT(dst)); qapi_free_SocketAddress(listen_addr); qapi_free_SocketAddress(connect_addr); unlink(TEST_SOCKET); unlink(TEST_FILE); close(testfd); for (i = 0; i < nfdrecv; i++) { close(fdrecv[i]); } g_free(fdrecv); }


static int raw_open_common(BlockDriverState *bs, const char *filename, int bdrv_flags, int open_flags) { BDRVRawState *s = bs->opaque; int fd, ret; ret = raw_normalize_devicepath(&filename); if (ret != 0) { return ret; } s->open_flags = open_flags | O_BINARY; s->open_flags &= ~O_ACCMODE; if (bdrv_flags & BDRV_O_RDWR) { s->open_flags |= O_RDWR; } else { s->open_flags |= O_RDONLY; } /* Use O_DSYNC for write-through caching, no flags for write-back caching, * and O_DIRECT for no caching. */ if ((bdrv_flags & BDRV_O_NOCACHE)) s->open_flags |= O_DIRECT; if (!(bdrv_flags & BDRV_O_CACHE_WB)) s->open_flags |= O_DSYNC; s->fd = -1; fd = qemu_open(filename, s->open_flags, 0644); if (fd < 0) { ret = -errno; if (ret == -EROFS) ret = -EACCES; return ret; } s->fd = fd; s->aligned_buf = NULL; if ((bdrv_flags & BDRV_O_NOCACHE)) { /* * Allocate a buffer for read/modify/write cycles. Chose the size * pessimistically as we don't know the block size yet. */ s->aligned_buf_size = 32 * MAX_BLOCKSIZE; s->aligned_buf = qemu_memalign(MAX_BLOCKSIZE, s->aligned_buf_size); if (s->aligned_buf == NULL) { goto out_close; } } /* We're falling back to POSIX AIO in some cases so init always */ if (paio_init() < 0) { goto out_free_buf; } #ifdef CONFIG_LINUX_AIO /* * Currently Linux do AIO only for files opened with O_DIRECT * specified so check NOCACHE flag too */ if ((bdrv_flags & (BDRV_O_NOCACHE|BDRV_O_NATIVE_AIO)) == (BDRV_O_NOCACHE|BDRV_O_NATIVE_AIO)) { s->aio_ctx = laio_init(); if (!s->aio_ctx) { goto out_free_buf; } s->use_aio = 1; } else #endif { #ifdef CONFIG_LINUX_AIO s->use_aio = 0; #endif } #ifdef CONFIG_XFS if (platform_test_xfs_fd(s->fd)) { s->is_xfs = 1; } #endif return 0; out_free_buf: qemu_vfree(s->aligned_buf); out_close: qemu_close(fd); return -errno; }


static int proxy_close(FsContext *ctx, V9fsFidOpenState *fs) { return close(fs->fd); }


uint64_t ldq_be_phys(target_phys_addr_t addr) { return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); }


static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) { hwaddr addr; addr = ((uint64_t)ubase << 32) | lbase; return addr; }


static int nbd_send_rep(int csock, uint32_t type, uint32_t opt) { uint64_t magic; uint32_t len; magic = cpu_to_be64(NBD_REP_MAGIC); if (write_sync(csock, &magic, sizeof(magic)) != sizeof(magic)) { LOG("write failed (rep magic)"); return -EINVAL; } opt = cpu_to_be32(opt); if (write_sync(csock, &opt, sizeof(opt)) != sizeof(opt)) { LOG("write failed (rep opt)"); return -EINVAL; } type = cpu_to_be32(type); if (write_sync(csock, &type, sizeof(type)) != sizeof(type)) { LOG("write failed (rep type)"); return -EINVAL; } len = cpu_to_be32(0); if (write_sync(csock, &len, sizeof(len)) != sizeof(len)) { LOG("write failed (rep data length)"); return -EINVAL; } return 0; }


void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp) { VirtIOBlockDataPlane *s; Error *local_err = NULL; BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev))); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); *dataplane = NULL; if (!conf->data_plane && !conf->iothread) { return; } /* Don't try if transport does not support notifiers. */ if (!k->set_guest_notifiers || !k->set_host_notifier) { error_setg(errp, "device is incompatible with x-data-plane " "(transport does not support notifiers)"); return; } /* If dataplane is (re-)enabled while the guest is running there could be * block jobs that can conflict. */ if (bdrv_op_is_blocked(conf->conf.bs, BLOCK_OP_TYPE_DATAPLANE, &local_err)) { error_setg(errp, "cannot start dataplane thread: %s", error_get_pretty(local_err)); error_free(local_err); return; } s = g_new0(VirtIOBlockDataPlane, 1); s->vdev = vdev; s->conf = conf; if (conf->iothread) { s->iothread = conf->iothread; object_ref(OBJECT(s->iothread)); } else { /* Create per-device IOThread if none specified. This is for * x-data-plane option compatibility. If x-data-plane is removed we * can drop this. */ object_initialize(&s->internal_iothread_obj, sizeof(s->internal_iothread_obj), TYPE_IOTHREAD); user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort); s->iothread = &s->internal_iothread_obj; } s->ctx = iothread_get_aio_context(s->iothread); s->bh = aio_bh_new(s->ctx, notify_guest_bh, s); error_setg(&s->blocker, "block device is in use by data plane"); bdrv_op_block_all(conf->conf.bs, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_RESIZE, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker); *dataplane = s; }


uint32_t HELPER(servc)(uint32_t r1, uint64_t r2) { if (sclp_service_call(env, r1, r2)) { return 3; } return 0; }


void ff_acelp_interpolate( int16_t* out, const int16_t* in, const int16_t* filter_coeffs, int precision, int frac_pos, int filter_length, int length) { int n, i; assert(pitch_delay_frac >= 0 && pitch_delay_frac < precision); for(n=0; n<length; n++) { int idx = 0; int v = 0x4000; for(i=0; i<filter_length;) { /* The reference G.729 and AMR fixed point code performs clipping after each of the two following accumulations. Since clipping affects only the synthetic OVERFLOW test without causing an int type overflow, it was moved outside the loop. */ /* R(x):=ac_v[-k+x] v += R(n-i)*ff_acelp_interp_filter(t+6i) v += R(n+i+1)*ff_acelp_interp_filter(6-t+6i) */ v += in[n + i] * filter_coeffs[idx + frac_pos]; idx += precision; i++; v += in[n - i] * filter_coeffs[idx - frac_pos]; } out[n] = av_clip_int16(v >> 15); } }


static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) { env->reserve = -1; /* Default MMU definitions */ env->nb_BATs = -1; env->nb_tlb = 0; env->nb_ways = 0; /* XXX: missing: * 32 bits PowerPC: * - MPC5xx(x) * - MPC8xx(x) * - RCPU (same as MPC5xx ?) */ spr_register(env, SPR_PVR, "PVR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, def->pvr); printf("%s: PVR %08x mask %08x => %08x\n", __func__, def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); switch (def->pvr) { /* Embedded PowerPC from IBM */ case CPU_PPC_401A1: /* 401 A1 family */ case CPU_PPC_401B2: /* 401 B2 family */ case CPU_PPC_401C2: /* 401 C2 family */ case CPU_PPC_401D2: /* 401 D2 family */ case CPU_PPC_401E2: /* 401 E2 family */ case CPU_PPC_401F2: /* 401 F2 family */ case CPU_PPC_401G2: /* 401 G2 family */ case CPU_PPC_IOP480: /* IOP 480 family */ case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); #if defined (TODO) /* XXX: optional ? */ gen_spr_compress(env); #endif env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_403GA: /* 403 GA family */ case CPU_PPC_403GB: /* 403 GB family */ case CPU_PPC_403GC: /* 403 GC family */ case CPU_PPC_403GCX: /* 403 GCX family */ gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); gen_spr_403(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_405CR: /* 405 GP/CR family */ case CPU_PPC_405EP: /* 405 EP family */ case CPU_PPC_405GPR: /* 405 GPR family */ case CPU_PPC_405D2: /* 405 D2 family */ case CPU_PPC_405D4: /* 405 D4 family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; case CPU_PPC_NPE405H: /* NPe405 H family */ case CPU_PPC_NPE405H2: case CPU_PPC_NPE405L: /* Npe405 L family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; #if defined (TODO) case CPU_PPC_STB01000: #endif #if defined (TODO) case CPU_PPC_STB01010: #endif #if defined (TODO) case CPU_PPC_STB0210: #endif case CPU_PPC_STB03: /* STB03 family */ #if defined (TODO) case CPU_PPC_STB043: /* STB043 family */ #endif #if defined (TODO) case CPU_PPC_STB045: /* STB045 family */ #endif case CPU_PPC_STB25: /* STB25 family */ #if defined (TODO) case CPU_PPC_STB130: /* STB130 family */ #endif gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; case CPU_PPC_440EP: /* 440 EP family */ case CPU_PPC_440GP: /* 440 GP family */ case CPU_PPC_440GX: /* 440 GX family */ case CPU_PPC_440GXc: /* 440 GXc family */ case CPU_PPC_440GXf: /* 440 GXf family */ case CPU_PPC_440SP: /* 440 SP family */ case CPU_PPC_440SP2: case CPU_PPC_440SPE: /* 440 SPE family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_BookE(env); gen_spr_440(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; /* Embedded PowerPC from Freescale */ #if defined (TODO) case CPU_PPC_5xx: break; #endif #if defined (TODO) case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ break; #endif #if defined (TODO) case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ break; #endif #if defined (TODO) case CPU_PPC_827x: /* MPC 827x / 828x */ break; #endif /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */ case CPU_PPC_e500v110: case CPU_PPC_e500v120: case CPU_PPC_e500v210: case CPU_PPC_e500v220: gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_BookE(env); gen_spr_BookE_FSL(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; #if defined (TODO) case CPU_PPC_e600: break; #endif /* 32 bits PowerPC */ case CPU_PPC_601: /* PowerPC 601 */ gen_spr_generic(env); gen_spr_ne_601(env); gen_spr_601(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_601_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_601_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ #if 0 /* ? */ spr_register(env, SPR_601_HID15, "HID15", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #endif env->nb_tlb = 64; env->nb_ways = 2; env->id_tlbs = 0; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_602: /* PowerPC 602 */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_602(env); /* hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_603: /* PowerPC 603 */ case CPU_PPC_603E: /* PowerPC 603e */ case CPU_PPC_603E7v: case CPU_PPC_603E7v2: case CPU_PPC_603P: /* PowerPC 603p */ case CPU_PPC_603R: /* PowerPC 603r */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_603(env); /* hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_G2: /* PowerPC G2 family */ case CPU_PPC_G2H4: case CPU_PPC_G2gp: case CPU_PPC_G2ls: case CPU_PPC_G2LE: /* PowerPC G2LE family */ case CPU_PPC_G2LEgp: case CPU_PPC_G2LEls: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); /* Memory management */ gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); gen_spr_G2(env); /* Hardware implementation register */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_604: /* PowerPC 604 */ case CPU_PPC_604E: /* PowerPC 604e */ case CPU_PPC_604R: /* PowerPC 604r */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_604(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_74x: /* PowerPC 740 / 750 */ case CPU_PPC_740E: case CPU_PPC_750E: case CPU_PPC_74xP: /* PowerPC 740P / 750P */ case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ case CPU_PPC_750CXE22: case CPU_PPC_750CXE23: case CPU_PPC_750CXE24: case CPU_PPC_750CXE24b: case CPU_PPC_750CXE31: case CPU_PPC_750CXE31b: case CPU_PPC_750CXR: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ case CPU_PPC_750FX20: case CPU_PPC_750FX21: case CPU_PPC_750FX22: case CPU_PPC_750FX23: case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ case CPU_PPC_750GX11: case CPU_PPC_750GX12: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ gen_high_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_755_10: /* PowerPC 755 */ case CPU_PPC_755_11: case CPU_PPC_755_20: case CPU_PPC_755D: case CPU_PPC_755E: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); /* Memory management */ gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); /* L2 cache control */ /* XXX : not implemented */ spr_register(env, SPR_ICTC, "ICTC", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_L2PM, "L2PM", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; #if defined (TODO) /* G4 family */ case CPU_PPC_7400: /* PowerPC 7400 */ case CPU_PPC_7410C: /* PowerPC 7410 */ case CPU_PPC_7410D: case CPU_PPC_7410E: case CPU_PPC_7441: /* PowerPC 7441 */ case CPU_PPC_7445: /* PowerPC 7445 */ case CPU_PPC_7447: /* PowerPC 7447 */ case CPU_PPC_7447A: /* PowerPC 7447A */ case CPU_PPC_7448: /* PowerPC 7448 */ case CPU_PPC_7450: /* PowerPC 7450 */ case CPU_PPC_7450b: case CPU_PPC_7451: /* PowerPC 7451 */ case CPU_PPC_7451G: case CPU_PPC_7455: /* PowerPC 7455 */ case CPU_PPC_7455F: case CPU_PPC_7455G: case CPU_PPC_7457: /* PowerPC 7457 */ case CPU_PPC_7457C: case CPU_PPC_7457A: /* PowerPC 7457A */ break; #endif /* 64 bits PowerPC */ #if defined (TARGET_PPC64) #if defined (TODO) case CPU_PPC_620: /* PowerPC 620 */ case CPU_PPC_630: /* PowerPC 630 (Power 3) */ case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ case CPU_PPC_POWER4: /* Power 4 */ case CPU_PPC_POWER4P: /* Power 4+ */ case CPU_PPC_POWER5: /* Power 5 */ case CPU_PPC_POWER5P: /* Power 5+ */ #endif break; case CPU_PPC_970: /* PowerPC 970 */ case CPU_PPC_970FX10: /* PowerPC 970 FX */ case CPU_PPC_970FX20: case CPU_PPC_970FX21: case CPU_PPC_970FX30: case CPU_PPC_970FX31: case CPU_PPC_970MP10: /* PowerPC 970 MP */ case CPU_PPC_970MP11: gen_spr_generic(env); gen_spr_ne_601(env); /* XXX: not correct */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc970_irq_init(env); break; #if defined (TODO) case CPU_PPC_CELL10: /* Cell family */ case CPU_PPC_CELL20: case CPU_PPC_CELL30: case CPU_PPC_CELL31: #endif break; #if defined (TODO) case CPU_PPC_RS64: /* Apache (RS64/A35) */ case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ #endif break; #endif /* defined (TARGET_PPC64) */ #if defined (TODO) /* POWER */ case CPU_POWER: /* POWER */ case CPU_POWER2: /* POWER2 */ break; #endif default: gen_spr_generic(env); /* XXX: TODO: allocate internal IRQ controller */ break; } if (env->nb_BATs == -1) env->nb_BATs = 4; /* Allocate TLBs buffer when needed */ if (env->nb_tlb != 0) { int nb_tlb = env->nb_tlb; if (env->id_tlbs != 0) nb_tlb *= 2; env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); /* Pre-compute some useful values */ env->tlb_per_way = env->nb_tlb / env->nb_ways; } }


static void nop(DBDMA_channel *ch) { dbdma_cmd *current = &ch->current; if (conditional_wait(ch)) goto wait; current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); dbdma_cmdptr_save(ch); conditional_interrupt(ch); conditional_branch(ch); wait: qemu_bh_schedule(dbdma_bh); }


static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle) { unsigned opc = get_Opcode_Y1(bundle); unsigned ext = get_RRROpcodeExtension_Y1(bundle); unsigned dest = get_Dest_Y1(bundle); unsigned srca = get_SrcA_Y1(bundle); unsigned srcb; int imm; switch (get_Opcode_Y1(bundle)) { case RRR_1_OPCODE_Y1: if (ext == UNARY_RRR_1_OPCODE_Y0) { ext = get_UnaryOpcodeExtension_Y1(bundle); return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca); } /* fallthru */ case RRR_0_OPCODE_Y1: case RRR_2_OPCODE_Y1: case RRR_3_OPCODE_Y1: case RRR_4_OPCODE_Y1: case RRR_5_OPCODE_Y1: case RRR_6_OPCODE_Y1: case RRR_7_OPCODE_Y1: srcb = get_SrcB_Y1(bundle); return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb); case SHIFT_OPCODE_Y1: ext = get_ShiftOpcodeExtension_Y1(bundle); imm = get_ShAmt_Y1(bundle); return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm); case ADDI_OPCODE_Y1: case ADDXI_OPCODE_Y1: case ANDI_OPCODE_Y1: case CMPEQI_OPCODE_Y1: case CMPLTSI_OPCODE_Y1: imm = (int8_t)get_Imm8_Y1(bundle); return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm); default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; } }


static void versatile_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, int board_id) { CPUState *env; ram_addr_t ram_offset; qemu_irq *cpu_pic; qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev; PCIBus *pci_bus; NICInfo *nd; int n; int done_smc = 0; if (!cpu_model) cpu_model = "arm926"; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } ram_offset = qemu_ram_alloc(ram_size); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); arm_sysctl_init(0x10000000, 0x41007004); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); for (n = 0; n < 32; n++) { pic[n] = qdev_get_gpio_in(dev, n); } dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); for (n = 0; n < 32; n++) { sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]); sic[n] = qdev_get_gpio_in(dev, n); } sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); dev = sysbus_create_varargs("versatile_pci", 0x40000000, sic[27], sic[28], sic[29], sic[30], NULL); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); /* The Versatile PCI bridge does not provide access to PCI IO space, so many of the qemu PCI devices are not useable. */ for(n = 0; n < nb_nics; n++) { nd = &nd_table[n]; if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { smc91c111_init(nd, 0x10010000, sic[25]); done_smc = 1; } else { pci_nic_init_nofail(nd, "rtl8139", NULL); } } if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } n = drive_get_max_bus(IF_SCSI); while (n >= 0) { pci_create_simple(pci_bus, -1, "lsi53c895a"); n--; } sysbus_create_simple("pl011", 0x101f1000, pic[12]); sysbus_create_simple("pl011", 0x101f2000, pic[13]); sysbus_create_simple("pl011", 0x101f3000, pic[14]); sysbus_create_simple("pl011", 0x10009000, sic[6]); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); sysbus_create_simple("sp804", 0x101e3000, pic[5]); /* The versatile/PB actually has a modified Color LCD controller that includes hardware cursor support from the PL111. */ sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); /* Add PL031 Real Time Clock. */ sysbus_create_simple("pl031", 0x101e8000, pic[10]); /* Memory map for Versatile/PB: */ /* 0x10000000 System registers. */ /* 0x10001000 PCI controller config registers. */ /* 0x10002000 Serial bus interface. */ /* 0x10003000 Secondary interrupt controller. */ /* 0x10004000 AACI (audio). */ /* 0x10005000 MMCI0. */ /* 0x10006000 KMI0 (keyboard). */ /* 0x10007000 KMI1 (mouse). */ /* 0x10008000 Character LCD Interface. */ /* 0x10009000 UART3. */ /* 0x1000a000 Smart card 1. */ /* 0x1000b000 MMCI1. */ /* 0x10010000 Ethernet. */ /* 0x10020000 USB. */ /* 0x10100000 SSMC. */ /* 0x10110000 MPMC. */ /* 0x10120000 CLCD Controller. */ /* 0x10130000 DMA Controller. */ /* 0x10140000 Vectored interrupt controller. */ /* 0x101d0000 AHB Monitor Interface. */ /* 0x101e0000 System Controller. */ /* 0x101e1000 Watchdog Interface. */ /* 0x101e2000 Timer 0/1. */ /* 0x101e3000 Timer 2/3. */ /* 0x101e4000 GPIO port 0. */ /* 0x101e5000 GPIO port 1. */ /* 0x101e6000 GPIO port 2. */ /* 0x101e7000 GPIO port 3. */ /* 0x101e8000 RTC. */ /* 0x101f0000 Smart card 0. */ /* 0x101f1000 UART0. */ /* 0x101f2000 UART1. */ /* 0x101f3000 UART2. */ /* 0x101f4000 SSPI. */ versatile_binfo.ram_size = ram_size; versatile_binfo.kernel_filename = kernel_filename; versatile_binfo.kernel_cmdline = kernel_cmdline; versatile_binfo.initrd_filename = initrd_filename; versatile_binfo.board_id = board_id; arm_load_kernel(env, &versatile_binfo); }


static void tftp_send_next_block(struct tftp_session *spt, struct tftp_t *recv_tp) { struct sockaddr_in saddr, daddr; struct mbuf *m; struct tftp_t *tp; int nobytes; m = m_get(spt->slirp); if (!m) { return; } memset(m->m_data, 0, m->m_size); m->m_data += IF_MAXLINKHDR; tp = (void *)m->m_data; m->m_data += sizeof(struct udpiphdr); tp->tp_op = htons(TFTP_DATA); tp->x.tp_data.tp_block_nr = htons((spt->block_nr + 1) & 0xffff); saddr.sin_addr = recv_tp->ip.ip_dst; saddr.sin_port = recv_tp->udp.uh_dport; daddr.sin_addr = spt->client_ip; daddr.sin_port = spt->client_port; nobytes = tftp_read_data(spt, spt->block_nr, tp->x.tp_data.tp_buf, 512); if (nobytes < 0) { m_free(m); /* send "file not found" error back */ tftp_send_error(spt, 1, "File not found", tp); return; } m->m_len = sizeof(struct tftp_t) - (512 - nobytes) - sizeof(struct ip) - sizeof(struct udphdr); udp_output2(NULL, m, &saddr, &daddr, IPTOS_LOWDELAY); if (nobytes == 512) { tftp_session_update(spt); } else { tftp_session_terminate(spt); } spt->block_nr++; }


static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, unsigned max_lvl, unsigned *compat_lvl, unsigned *cpu_version) { unsigned lvl = get_compat_level(pvr); bool is205, is206; if (!lvl) { return; } /* If it is a logical PVR, try to determine the highest level */ is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) && (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) && ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); if (is205 || is206) { if (!max_lvl) { /* User did not set the level, choose the highest */ if (*compat_lvl <= lvl) { *compat_lvl = lvl; *cpu_version = pvr; } } else if (max_lvl >= lvl) { /* User chose the level, don't set higher than this */ *compat_lvl = lvl; *cpu_version = pvr; } } }


static void qobject_input_type_str(Visitor *v, const char *name, char **obj, Error **errp) { QObjectInputVisitor *qiv = to_qiv(v); QObject *qobj = qobject_input_get_object(qiv, name, true, errp); QString *qstr; *obj = NULL; if (!qobj) { return; } qstr = qobject_to_qstring(qobj); if (!qstr) { error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null", "string"); return; } *obj = g_strdup(qstring_get_str(qstr)); }


static void gen_or(DisasContext *ctx) { int rs, ra, rb; rs = rS(ctx->opcode); ra = rA(ctx->opcode); rb = rB(ctx->opcode); /* Optimisation for mr. ri case */ if (rs != ra || rs != rb) { if (rs != rb) tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); else tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[ra]); } else if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_Rc0(ctx, cpu_gpr[rs]); #if defined(TARGET_PPC64) } else { int prio = 0; switch (rs) { case 1: /* Set process priority to low */ prio = 2; break; case 6: /* Set process priority to medium-low */ prio = 3; break; case 2: /* Set process priority to normal */ prio = 4; break; #if !defined(CONFIG_USER_ONLY) case 31: if (!ctx->pr) { /* Set process priority to very low */ prio = 1; } break; case 5: if (!ctx->pr) { /* Set process priority to medium-hight */ prio = 5; } break; case 3: if (!ctx->pr) { /* Set process priority to high */ prio = 6; } break; case 7: if (ctx->hv) { /* Set process priority to very high */ prio = 7; } break; #endif default: /* nop */ break; } if (prio) { TCGv t0 = tcg_temp_new(); gen_load_spr(t0, SPR_PPR); tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); gen_store_spr(SPR_PPR, t0); tcg_temp_free(t0); } #endif } }


target_ulong helper_dvpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; do { /* Turn off all VPEs except the one executing the dvpe. */ if (other_cpu != env) { other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } other_cpu = other_cpu->next_cpu; } while (other_cpu); return prev; }


static int sbr_make_f_master(AACContext *ac, SpectralBandReplication *sbr, SpectrumParameters *spectrum) { unsigned int temp, max_qmf_subbands; unsigned int start_min, stop_min; int k; const int8_t *sbr_offset_ptr; int16_t stop_dk[13]; if (sbr->sample_rate < 32000) { temp = 3000; } else if (sbr->sample_rate < 64000) { temp = 4000; } else temp = 5000; switch (sbr->sample_rate) { case 16000: sbr_offset_ptr = sbr_offset[0]; break; case 22050: sbr_offset_ptr = sbr_offset[1]; break; case 24000: sbr_offset_ptr = sbr_offset[2]; break; case 32000: sbr_offset_ptr = sbr_offset[3]; break; case 44100: case 48000: case 64000: sbr_offset_ptr = sbr_offset[4]; break; case 88200: case 96000: case 128000: case 176400: case 192000: sbr_offset_ptr = sbr_offset[5]; break; default: av_log(ac->avctx, AV_LOG_ERROR, "Unsupported sample rate for SBR: %d\n", sbr->sample_rate); return -1; } start_min = ((temp << 7) + (sbr->sample_rate >> 1)) / sbr->sample_rate; stop_min = ((temp << 8) + (sbr->sample_rate >> 1)) / sbr->sample_rate; sbr->k[0] = start_min + sbr_offset_ptr[spectrum->bs_start_freq]; if (spectrum->bs_stop_freq < 14) { sbr->k[2] = stop_min; make_bands(stop_dk, stop_min, 64, 13); qsort(stop_dk, 13, sizeof(stop_dk[0]), qsort_comparison_function_int16); for (k = 0; k < spectrum->bs_stop_freq; k++) sbr->k[2] += stop_dk[k]; } else if (spectrum->bs_stop_freq == 14) { sbr->k[2] = 2*sbr->k[0]; } else if (spectrum->bs_stop_freq == 15) { sbr->k[2] = 3*sbr->k[0]; } else { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bs_stop_freq: %d\n", spectrum->bs_stop_freq); return -1; } sbr->k[2] = FFMIN(64, sbr->k[2]); // Requirements (14496-3 sp04 p205) if (sbr->sample_rate <= 32000) { max_qmf_subbands = 48; } else if (sbr->sample_rate == 44100) { max_qmf_subbands = 35; } else if (sbr->sample_rate >= 48000) max_qmf_subbands = 32; if (sbr->k[2] - sbr->k[0] > max_qmf_subbands) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bitstream, too many QMF subbands: %d\n", sbr->k[2] - sbr->k[0]); return -1; } if (!spectrum->bs_freq_scale) { int dk, k2diff; dk = spectrum->bs_alter_scale + 1; sbr->n_master = ((sbr->k[2] - sbr->k[0] + (dk&2)) >> dk) << 1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] = dk; k2diff = sbr->k[2] - sbr->k[0] - sbr->n_master * dk; if (k2diff < 0) { sbr->f_master[1]--; sbr->f_master[2]-= (k2diff < -1); } else if (k2diff) { sbr->f_master[sbr->n_master]++; } sbr->f_master[0] = sbr->k[0]; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] += sbr->f_master[k - 1]; } else { int half_bands = 7 - spectrum->bs_freq_scale; // bs_freq_scale = {1,2,3} int two_regions, num_bands_0; int vdk0_max, vdk1_min; int16_t vk0[49]; if (49 * sbr->k[2] > 110 * sbr->k[0]) { two_regions = 1; sbr->k[1] = 2 * sbr->k[0]; } else { two_regions = 0; sbr->k[1] = sbr->k[2]; } num_bands_0 = lrintf(half_bands * log2f(sbr->k[1] / (float)sbr->k[0])) * 2; if (num_bands_0 <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid num_bands_0: %d\n", num_bands_0); return -1; } vk0[0] = 0; make_bands(vk0+1, sbr->k[0], sbr->k[1], num_bands_0); qsort(vk0 + 1, num_bands_0, sizeof(vk0[1]), qsort_comparison_function_int16); vdk0_max = vk0[num_bands_0]; vk0[0] = sbr->k[0]; for (k = 1; k <= num_bands_0; k++) { if (vk0[k] <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk0[%d]: %d\n", k, vk0[k]); return -1; } vk0[k] += vk0[k-1]; } if (two_regions) { int16_t vk1[49]; float invwarp = spectrum->bs_alter_scale ? 0.76923076923076923077f : 1.0f; // bs_alter_scale = {0,1} int num_bands_1 = lrintf(half_bands * invwarp * log2f(sbr->k[2] / (float)sbr->k[1])) * 2; make_bands(vk1+1, sbr->k[1], sbr->k[2], num_bands_1); vdk1_min = array_min_int16(vk1 + 1, num_bands_1); if (vdk1_min < vdk0_max) { int change; qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); change = FFMIN(vdk0_max - vk1[1], (vk1[num_bands_1] - vk1[1]) >> 1); vk1[1] += change; vk1[num_bands_1] -= change; } qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); vk1[0] = sbr->k[1]; for (k = 1; k <= num_bands_1; k++) { if (vk1[k] <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk1[%d]: %d\n", k, vk1[k]); return -1; } vk1[k] += vk1[k-1]; } sbr->n_master = num_bands_0 + num_bands_1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(&sbr->f_master[0], vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); memcpy(&sbr->f_master[num_bands_0 + 1], vk1 + 1, num_bands_1 * sizeof(sbr->f_master[0])); } else { sbr->n_master = num_bands_0; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(sbr->f_master, vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); } } return 0; }


static void event_loop(VideoState *cur_stream) { SDL_Event event; double incr, pos, frac; for (;;) { double x; refresh_loop_wait_event(cur_stream, &event); switch (event.type) { case SDL_KEYDOWN: if (exit_on_keydown) { do_exit(cur_stream); break; } switch (event.key.keysym.sym) { case SDLK_ESCAPE: case SDLK_q: do_exit(cur_stream); break; case SDLK_f: toggle_full_screen(cur_stream); cur_stream->force_refresh = 1; break; case SDLK_p: case SDLK_SPACE: toggle_pause(cur_stream); break; case SDLK_s: // S: Step to next frame step_to_next_frame(cur_stream); break; case SDLK_a: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_AUDIO); break; case SDLK_v: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_VIDEO); break; case SDLK_t: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_SUBTITLE); break; case SDLK_w: toggle_audio_display(cur_stream); break; case SDLK_PAGEUP: incr = 600.0; goto do_seek; case SDLK_PAGEDOWN: incr = -600.0; goto do_seek; case SDLK_LEFT: incr = -10.0; goto do_seek; case SDLK_RIGHT: incr = 10.0; goto do_seek; case SDLK_UP: incr = 60.0; goto do_seek; case SDLK_DOWN: incr = -60.0; do_seek: if (seek_by_bytes) { if (cur_stream->video_stream >= 0 && cur_stream->video_current_pos >= 0) { pos = cur_stream->video_current_pos; } else if (cur_stream->audio_stream >= 0 && cur_stream->audio_pkt.pos >= 0) { pos = cur_stream->audio_pkt.pos; } else pos = avio_tell(cur_stream->ic->pb); if (cur_stream->ic->bit_rate) incr *= cur_stream->ic->bit_rate / 8.0; else incr *= 180000.0; pos += incr; stream_seek(cur_stream, pos, incr, 1); } else { pos = get_master_clock(cur_stream); if (isnan(pos)) pos = (double)cur_stream->seek_pos / AV_TIME_BASE; pos += incr; if (cur_stream->ic->start_time != AV_NOPTS_VALUE && pos < cur_stream->ic->start_time / (double)AV_TIME_BASE) pos = cur_stream->ic->start_time / (double)AV_TIME_BASE; stream_seek(cur_stream, (int64_t)(pos * AV_TIME_BASE), (int64_t)(incr * AV_TIME_BASE), 0); } break; default: break; } break; case SDL_VIDEOEXPOSE: cur_stream->force_refresh = 1; break; case SDL_MOUSEBUTTONDOWN: if (exit_on_mousedown) { do_exit(cur_stream); break; } case SDL_MOUSEMOTION: if (cursor_hidden) { SDL_ShowCursor(1); cursor_hidden = 0; } cursor_last_shown = av_gettime(); if (event.type == SDL_MOUSEBUTTONDOWN) { x = event.button.x; } else { if (event.motion.state != SDL_PRESSED) break; x = event.motion.x; } if (seek_by_bytes || cur_stream->ic->duration <= 0) { uint64_t size = avio_size(cur_stream->ic->pb); stream_seek(cur_stream, size*x/cur_stream->width, 0, 1); } else { int64_t ts; int ns, hh, mm, ss; int tns, thh, tmm, tss; tns = cur_stream->ic->duration / 1000000LL; thh = tns / 3600; tmm = (tns % 3600) / 60; tss = (tns % 60); frac = x / cur_stream->width; ns = frac * tns; hh = ns / 3600; mm = (ns % 3600) / 60; ss = (ns % 60); fprintf(stderr, "Seek to %2.0f%% (%2d:%02d:%02d) of total duration (%2d:%02d:%02d) \n", frac*100, hh, mm, ss, thh, tmm, tss); ts = frac * cur_stream->ic->duration; if (cur_stream->ic->start_time != AV_NOPTS_VALUE) ts += cur_stream->ic->start_time; stream_seek(cur_stream, ts, 0, 0); } break; case SDL_VIDEORESIZE: screen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0, SDL_HWSURFACE|SDL_RESIZABLE|SDL_ASYNCBLIT|SDL_HWACCEL); screen_width = cur_stream->width = event.resize.w; screen_height = cur_stream->height = event.resize.h; cur_stream->force_refresh = 1; break; case SDL_QUIT: case FF_QUIT_EVENT: do_exit(cur_stream); break; case FF_ALLOC_EVENT: alloc_picture(event.user.data1); break; default: break; } } }