static int qdm2_parse_packet(AVFormatContext *s, PayloadContext *qdm, AVStream *st, AVPacket *pkt, uint32_t *timestamp, const uint8_t *buf, int len, int flags) { int res = AVERROR_INVALIDDATA, n; const uint8_t *end = buf + len, *p = buf; if (len > 0) { if (len < 2) return AVERROR_INVALIDDATA; /* configuration block */ if (*p == 0xff) { if (qdm->n_pkts > 0) { av_log(s, AV_LOG_WARNING, "Out of sequence config - dropping queue\n"); qdm->n_pkts = 0; memset(qdm->len, 0, sizeof(qdm->len)); } if ((res = qdm2_parse_config(qdm, st, ++p, end)) < 0) return res; p += res; /* We set codec_id to CODEC_ID_NONE initially to * delay decoder initialization since extradata is * carried within the RTP stream, not SDP. Here, * by setting codec_id to CODEC_ID_QDM2, we are signalling * to the decoder that it is OK to initialize. */ st->codec->codec_id = CODEC_ID_QDM2; } /* subpackets */ while (end - p >= 4) { if ((res = qdm2_parse_subpacket(qdm, st, p, end)) < 0) return res; p += res; } qdm->timestamp = *timestamp; if (++qdm->n_pkts < qdm->subpkts_per_block) qdm->cache = 0; for (n = 0; n < 0x80; n++) if (qdm->len[n] > 0) qdm->cache++; } /* output the subpackets into freshly created superblock structures */ if (!qdm->cache || (res = qdm2_restore_block(qdm, st, pkt)) < 0) return res; if (--qdm->cache == 0) qdm->n_pkts = 0; *timestamp = qdm->timestamp; qdm->timestamp = RTP_NOTS_VALUE; return (qdm->cache > 0) ? 1 : 0; }


av_cold void ff_ac3dsp_init_x86(AC3DSPContext *c, int bit_exact) { int mm_flags = av_get_cpu_flags(); if (EXTERNAL_MMX(mm_flags)) { c->ac3_exponent_min = ff_ac3_exponent_min_mmx; c->ac3_max_msb_abs_int16 = ff_ac3_max_msb_abs_int16_mmx; c->ac3_lshift_int16 = ff_ac3_lshift_int16_mmx; c->ac3_rshift_int32 = ff_ac3_rshift_int32_mmx; } if (EXTERNAL_AMD3DNOW(mm_flags)) { c->extract_exponents = ff_ac3_extract_exponents_3dnow; if (!bit_exact) { c->float_to_fixed24 = ff_float_to_fixed24_3dnow; } } if (EXTERNAL_MMXEXT(mm_flags)) { c->ac3_exponent_min = ff_ac3_exponent_min_mmxext; c->ac3_max_msb_abs_int16 = ff_ac3_max_msb_abs_int16_mmxext; } if (EXTERNAL_SSE(mm_flags)) { c->float_to_fixed24 = ff_float_to_fixed24_sse; } if (EXTERNAL_SSE2(mm_flags)) { c->ac3_exponent_min = ff_ac3_exponent_min_sse2; c->ac3_max_msb_abs_int16 = ff_ac3_max_msb_abs_int16_sse2; c->float_to_fixed24 = ff_float_to_fixed24_sse2; c->compute_mantissa_size = ff_ac3_compute_mantissa_size_sse2; c->extract_exponents = ff_ac3_extract_exponents_sse2; if (!(mm_flags & AV_CPU_FLAG_SSE2SLOW)) { c->ac3_lshift_int16 = ff_ac3_lshift_int16_sse2; c->ac3_rshift_int32 = ff_ac3_rshift_int32_sse2; } } if (EXTERNAL_SSSE3(mm_flags)) { c->ac3_max_msb_abs_int16 = ff_ac3_max_msb_abs_int16_ssse3; if (!(mm_flags & AV_CPU_FLAG_ATOM)) { c->extract_exponents = ff_ac3_extract_exponents_ssse3; } } #if HAVE_SSE_INLINE && HAVE_7REGS if (INLINE_SSE(mm_flags)) { c->downmix = ac3_downmix_sse; } #endif }


void tcg_context_init(TCGContext *s) { int op, total_args, n; TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; memset(s, 0, sizeof(*s)); s->nb_globals = 0; /* Count total number of arguments and allocate the corresponding space */ total_args = 0; for(op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; n = def->nb_iargs + def->nb_oargs; total_args += n; } args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); sorted_args = g_malloc(sizeof(int) * total_args); for(op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; def->args_ct = args_ct; def->sorted_args = sorted_args; n = def->nb_iargs + def->nb_oargs; sorted_args += n; args_ct += n; } /* Register helpers. */ #define GEN_HELPER 2 #include "helper.h" tcg_target_init(s); }


void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar, target_phys_addr_t mem_base) { memory_region_add_subregion(bar, mem_base, &s->mem); }


int qemu_input_key_value_to_scancode(const KeyValue *value, bool down, int *codes) { int keycode = qemu_input_key_value_to_number(value); int count = 0; if (value->type == KEY_VALUE_KIND_QCODE && value->u.qcode == Q_KEY_CODE_PAUSE) { /* specific case */ int v = down ? 0 : 0x80; codes[count++] = 0xe1; codes[count++] = 0x1d | v; codes[count++] = 0x45 | v; return count; } if (keycode & SCANCODE_GREY) { codes[count++] = SCANCODE_EMUL0; keycode &= ~SCANCODE_GREY; } if (!down) { keycode |= SCANCODE_UP; } codes[count++] = keycode; return count; }


static void coroutine_fn verify_self(void *opaque) { g_assert(qemu_coroutine_self() == opaque); }


void net_set_boot_mask(int net_boot_mask) { int i; /* Only the first four NICs may be bootable */ net_boot_mask = net_boot_mask & 0xF; for (i = 0; i < nb_nics; i++) { if (net_boot_mask & (1 << i)) { net_boot_mask &= ~(1 << i); } } if (net_boot_mask) { fprintf(stderr, "Cannot boot from non-existent NIC\n"); exit(1); } }


void msix_reset(PCIDevice *dev) { if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) return; msix_free_irq_entries(dev); dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); msix_mask_all(dev, dev->msix_entries_nr); }


static void pl110_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { pl110_state *s = (pl110_state *)opaque; int n; /* For simplicity invalidate the display whenever a control register is written to. */ s->invalidate = 1; if (offset >= 0x200 && offset < 0x400) { /* Palette. */ n = (offset - 0x200) >> 2; s->raw_palette[(offset - 0x200) >> 2] = val; pl110_update_palette(s, n); return; } switch (offset >> 2) { case 0: /* LCDTiming0 */ s->timing[0] = val; n = ((val & 0xfc) + 4) * 4; pl110_resize(s, n, s->rows); break; case 1: /* LCDTiming1 */ s->timing[1] = val; n = (val & 0x3ff) + 1; pl110_resize(s, s->cols, n); break; case 2: /* LCDTiming2 */ s->timing[2] = val; break; case 3: /* LCDTiming3 */ s->timing[3] = val; break; case 4: /* LCDUPBASE */ s->upbase = val; break; case 5: /* LCDLPBASE */ s->lpbase = val; break; case 6: /* LCDIMSC */ if (s->version != PL110) { goto control; } imsc: s->int_mask = val; pl110_update(s); break; case 7: /* LCDControl */ if (s->version != PL110) { goto imsc; } control: s->cr = val; s->bpp = (val >> 1) & 7; if (pl110_enabled(s)) { qemu_console_resize(s->ds, s->cols, s->rows); } break; case 10: /* LCDICR */ s->int_status &= ~val; pl110_update(s); break; default: hw_error("pl110_write: Bad offset %x\n", (int)offset); } }


static int process_input(void) { InputFile *ifile; AVFormatContext *is; InputStream *ist; AVPacket pkt; int ret, i, j; int file_index; /* select the stream that we must read now */ file_index = select_input_file(); /* if none, if is finished */ if (file_index == -2) { poll_filters() ; return AVERROR(EAGAIN); } if (file_index < 0) { if (got_eagain()) { reset_eagain(); av_usleep(10000); return AVERROR(EAGAIN); } av_log(NULL, AV_LOG_VERBOSE, "No more inputs to read from, finishing.\n"); return AVERROR_EOF; } ifile = input_files[file_index]; is = ifile->ctx; ret = get_input_packet(ifile, &pkt); if (ret == AVERROR(EAGAIN)) { ifile->eagain = 1; return ret; } if (ret < 0) { if (ret != AVERROR_EOF) { print_error(is->filename, ret); if (exit_on_error) exit_program(1); } ifile->eof_reached = 1; for (i = 0; i < ifile->nb_streams; i++) { ist = input_streams[ifile->ist_index + i]; if (ist->decoding_needed) output_packet(ist, NULL); poll_filters(); } if (opt_shortest) return AVERROR_EOF; else return AVERROR(EAGAIN); } reset_eagain(); if (do_pkt_dump) { av_pkt_dump_log2(NULL, AV_LOG_DEBUG, &pkt, do_hex_dump, is->streams[pkt.stream_index]); } /* the following test is needed in case new streams appear dynamically in stream : we ignore them */ if (pkt.stream_index >= ifile->nb_streams) { report_new_stream(file_index, &pkt); goto discard_packet; } ist = input_streams[ifile->ist_index + pkt.stream_index]; if (ist->discard) goto discard_packet; if(!ist->wrap_correction_done && input_files[file_index]->ctx->start_time != AV_NOPTS_VALUE && ist->st->pts_wrap_bits < 64){ uint64_t stime = av_rescale_q(input_files[file_index]->ctx->start_time, AV_TIME_BASE_Q, ist->st->time_base); uint64_t stime2= stime + (1LL<<ist->st->pts_wrap_bits); ist->wrap_correction_done = 1; if(pkt.dts != AV_NOPTS_VALUE && pkt.dts > stime && pkt.dts - stime > stime2 - pkt.dts) { pkt.dts -= 1LL<<ist->st->pts_wrap_bits; ist->wrap_correction_done = 0; } if(pkt.pts != AV_NOPTS_VALUE && pkt.pts > stime && pkt.pts - stime > stime2 - pkt.pts) { pkt.pts -= 1LL<<ist->st->pts_wrap_bits; ist->wrap_correction_done = 0; } } if (pkt.dts != AV_NOPTS_VALUE) pkt.dts += av_rescale_q(ifile->ts_offset, AV_TIME_BASE_Q, ist->st->time_base); if (pkt.pts != AV_NOPTS_VALUE) pkt.pts += av_rescale_q(ifile->ts_offset, AV_TIME_BASE_Q, ist->st->time_base); if (pkt.pts != AV_NOPTS_VALUE) pkt.pts *= ist->ts_scale; if (pkt.dts != AV_NOPTS_VALUE) pkt.dts *= ist->ts_scale; if (debug_ts) { av_log(NULL, AV_LOG_INFO, "demuxer -> ist_index:%d type:%s " "next_dts:%s next_dts_time:%s next_pts:%s next_pts_time:%s pkt_pts:%s pkt_pts_time:%s pkt_dts:%s pkt_dts_time:%s off:%"PRId64"\n", ifile->ist_index + pkt.stream_index, av_get_media_type_string(ist->st->codec->codec_type), av_ts2str(ist->next_dts), av_ts2timestr(ist->next_dts, &AV_TIME_BASE_Q), av_ts2str(ist->next_pts), av_ts2timestr(ist->next_pts, &AV_TIME_BASE_Q), av_ts2str(pkt.pts), av_ts2timestr(pkt.pts, &ist->st->time_base), av_ts2str(pkt.dts), av_ts2timestr(pkt.dts, &ist->st->time_base), input_files[ist->file_index]->ts_offset); } if (pkt.dts != AV_NOPTS_VALUE && ist->next_dts != AV_NOPTS_VALUE && !copy_ts) { int64_t pkt_dts = av_rescale_q(pkt.dts, ist->st->time_base, AV_TIME_BASE_Q); int64_t delta = pkt_dts - ist->next_dts; if (is->iformat->flags & AVFMT_TS_DISCONT) { if(delta < -1LL*dts_delta_threshold*AV_TIME_BASE || (delta > 1LL*dts_delta_threshold*AV_TIME_BASE && ist->st->codec->codec_type != AVMEDIA_TYPE_SUBTITLE) || pkt_dts+1<ist->pts){ ifile->ts_offset -= delta; av_log(NULL, AV_LOG_DEBUG, "timestamp discontinuity %"PRId64", new offset= %"PRId64"\n", delta, ifile->ts_offset); pkt.dts -= av_rescale_q(delta, AV_TIME_BASE_Q, ist->st->time_base); if (pkt.pts != AV_NOPTS_VALUE) pkt.pts -= av_rescale_q(delta, AV_TIME_BASE_Q, ist->st->time_base); } } else { if ( delta < -1LL*dts_error_threshold*AV_TIME_BASE || (delta > 1LL*dts_error_threshold*AV_TIME_BASE && ist->st->codec->codec_type != AVMEDIA_TYPE_SUBTITLE) || pkt_dts+1<ist->pts){ av_log(NULL, AV_LOG_WARNING, "DTS %"PRId64", next:%"PRId64" st:%d invalid dropping\n", pkt.dts, ist->next_dts, pkt.stream_index); pkt.dts = AV_NOPTS_VALUE; } if (pkt.pts != AV_NOPTS_VALUE){ int64_t pkt_pts = av_rescale_q(pkt.pts, ist->st->time_base, AV_TIME_BASE_Q); delta = pkt_pts - ist->next_dts; if ( delta < -1LL*dts_error_threshold*AV_TIME_BASE || (delta > 1LL*dts_error_threshold*AV_TIME_BASE && ist->st->codec->codec_type != AVMEDIA_TYPE_SUBTITLE) || pkt_pts+1<ist->pts) { av_log(NULL, AV_LOG_WARNING, "PTS %"PRId64", next:%"PRId64" invalid dropping st:%d\n", pkt.pts, ist->next_dts, pkt.stream_index); pkt.pts = AV_NOPTS_VALUE; } } } } sub2video_heartbeat(ist, pkt.pts); if ((ret = output_packet(ist, &pkt)) < 0 || ((ret = poll_filters()) < 0 && ret != AVERROR_EOF)) { char buf[128]; av_strerror(ret, buf, sizeof(buf)); av_log(NULL, AV_LOG_ERROR, "Error while decoding stream #%d:%d: %s\n", ist->file_index, ist->st->index, buf); if (exit_on_error) exit_program(1); av_free_packet(&pkt); return AVERROR(EAGAIN); } discard_packet: av_free_packet(&pkt); return 0; }


static inline void gen_intermediate_code_internal(AlphaCPU *cpu, TranslationBlock *tb, bool search_pc) { CPUState *cs = CPU(cpu); CPUAlphaState *env = &cpu->env; DisasContext ctx, *ctxp = &ctx; target_ulong pc_start; target_ulong pc_mask; uint32_t insn; uint16_t *gen_opc_end; CPUBreakpoint *bp; int j, lj = -1; ExitStatus ret; int num_insns; int max_insns; pc_start = tb->pc; gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; ctx.tb = tb; ctx.pc = pc_start; ctx.mem_idx = cpu_mmu_index(env); ctx.implver = env->implver; ctx.singlestep_enabled = cs->singlestep_enabled; /* ??? Every TB begins with unset rounding mode, to be initialized on the first fp insn of the TB. Alternately we could define a proper default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure to reset the FP_STATUS to that default at the end of any TB that changes the default. We could even (gasp) dynamiclly figure out what default would be most efficient given the running program. */ ctx.tb_rm = -1; /* Similarly for flush-to-zero. */ ctx.tb_ftz = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } if (in_superpage(&ctx, pc_start)) { pc_mask = (1ULL << 41) - 1; } else { pc_mask = ~TARGET_PAGE_MASK; } gen_tb_start(); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { gen_excp(&ctx, EXCP_DEBUG, 0); break; } } } if (search_pc) { j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; if (lj < j) { lj++; while (lj < j) tcg_ctx.gen_opc_instr_start[lj++] = 0; } tcg_ctx.gen_opc_pc[lj] = ctx.pc; tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } insn = cpu_ldl_code(env, ctx.pc); num_insns++; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(ctx.pc); } TCGV_UNUSED_I64(ctx.zero); TCGV_UNUSED_I64(ctx.sink); TCGV_UNUSED_I64(ctx.lit); ctx.pc += 4; ret = translate_one(ctxp, insn); if (!TCGV_IS_UNUSED_I64(ctx.sink)) { tcg_gen_discard_i64(ctx.sink); tcg_temp_free(ctx.sink); } if (!TCGV_IS_UNUSED_I64(ctx.zero)) { tcg_temp_free(ctx.zero); } if (!TCGV_IS_UNUSED_I64(ctx.lit)) { tcg_temp_free(ctx.lit); } /* If we reach a page boundary, are single stepping, or exhaust instruction count, stop generation. */ if (ret == NO_EXIT && ((ctx.pc & pc_mask) == 0 || tcg_ctx.gen_opc_ptr >= gen_opc_end || num_insns >= max_insns || singlestep || ctx.singlestep_enabled)) { ret = EXIT_PC_STALE; } } while (ret == NO_EXIT); if (tb->cflags & CF_LAST_IO) { gen_io_end(); } switch (ret) { case EXIT_GOTO_TB: case EXIT_NORETURN: break; case EXIT_PC_STALE: tcg_gen_movi_i64(cpu_pc, ctx.pc); /* FALLTHRU */ case EXIT_PC_UPDATED: if (ctx.singlestep_enabled) { gen_excp_1(EXCP_DEBUG, 0); } else { tcg_gen_exit_tb(0); } break; default: abort(); } gen_tb_end(tb, num_insns); *tcg_ctx.gen_opc_ptr = INDEX_op_end; if (search_pc) { j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = ctx.pc - pc_start; tb->icount = num_insns; } #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(env, pc_start, ctx.pc - pc_start, 1); qemu_log("\n"); } #endif }


uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg) { CPU_DoubleU farg; farg.ll = arg; if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN conversion */ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); } else if (unlikely(float64_is_quiet_nan(farg.d) || float64_is_infinity(farg.d))) { /* qNan / infinity conversion */ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI); } else { farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status); /* XXX: higher bits are not supposed to be significant. * to make tests easier, return the same as a real PowerPC 750 */ farg.ll |= 0xFFF80000ULL << 32; } return farg.ll; }


POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER8"; dc->desc = "POWER8E"; dc->props = powerpc_servercpu_properties; pcc->pvr_match = ppc_pvr_match_power8; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | (1ull << MSR_ME) | (1ull << MSR_FE0) | (1ull << MSR_SE) | (1ull << MSR_DE) | (1ull << MSR_FE1) | (1ull << MSR_IR) | (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif pcc->excp_model = POWERPC_EXCP_POWER7; pcc->bus_model = PPC_FLAGS_INPUT_POWER7; pcc->bfd_mach = bfd_mach_ppc64; pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | POWERPC_FLAG_VSX; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; }


static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip) { target_phys_addr_t paddr; VAPICHandlers *handlers; uint8_t opcode[2]; uint32_t imm32; if (smp_cpus == 1) { handlers = &s->rom_state.up; } else { handlers = &s->rom_state.mp; } pause_all_vcpus(); cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0); switch (opcode[0]) { case 0x89: /* mov r32 to r/m32 */ patch_byte(env, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */ patch_call(s, env, ip + 1, handlers->set_tpr); break; case 0x8b: /* mov r/m32 to r32 */ patch_byte(env, ip, 0x90); patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]); break; case 0xa1: /* mov abs to eax */ patch_call(s, env, ip, handlers->get_tpr[0]); break; case 0xa3: /* mov eax to abs */ patch_call(s, env, ip, handlers->set_tpr_eax); break; case 0xc7: /* mov imm32, r/m32 (c7/0) */ patch_byte(env, ip, 0x68); /* push imm32 */ cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0); cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1); patch_call(s, env, ip + 5, handlers->set_tpr); break; case 0xff: /* push r/m32 */ patch_byte(env, ip, 0x50); /* push eax */ patch_call(s, env, ip + 1, handlers->get_tpr_stack); break; default: abort(); } resume_all_vcpus(); paddr = cpu_get_phys_page_debug(env, ip); paddr += ip & ~TARGET_PAGE_MASK; tb_invalidate_phys_page_range(paddr, paddr + 1, 1); }


void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr) { TranslationBlock *tb; CPUState *saved_env; unsigned long pc; int ret; /* XXX: hack to restore env in all cases, even if not called from generated code */ saved_env = env; env = cpu_single_env; { unsigned long tlb_addrr, tlb_addrw; int index; index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); tlb_addrr = env->tlb_read[is_user][index].address; tlb_addrw = env->tlb_write[is_user][index].address; #if 0 if (loglevel) { fprintf(logfile, "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx " "(0x%08lx 0x%08lx)\n", __func__, env, &env->tlb_read[is_user][index], index, addr, tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK, tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); } #endif } ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1); if (ret) { if (retaddr) { /* now we have a real cpu fault */ pc = (unsigned long)retaddr; tb = tb_find_pc(pc); if (tb) { /* the PC is inside the translated code. It means that we have a virtual CPU fault */ cpu_restore_state(tb, env, pc, NULL); } } do_raise_exception_err(env->exception_index, env->error_code); } { unsigned long tlb_addrr, tlb_addrw; int index; index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); tlb_addrr = env->tlb_read[is_user][index].address; tlb_addrw = env->tlb_write[is_user][index].address; #if 0 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx " "(0x%08lx 0x%08lx)\n", __func__, env, &env->tlb_read[is_user][index], index, addr, tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK, tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); #endif } env = saved_env; }


static inline int get_cabac_cbf_ctx( H264Context *h, int cat, int idx ) { int nza, nzb; int ctx = 0; if( cat == 0 ) { nza = h->left_cbp&0x100; nzb = h-> top_cbp&0x100; } else if( cat == 1 || cat == 2 ) { nza = h->non_zero_count_cache[scan8[idx] - 1]; nzb = h->non_zero_count_cache[scan8[idx] - 8]; } else if( cat == 3 ) { nza = (h->left_cbp>>(6+idx))&0x01; nzb = (h-> top_cbp>>(6+idx))&0x01; } else { assert(cat == 4); nza = h->non_zero_count_cache[scan8[16+idx] - 1]; nzb = h->non_zero_count_cache[scan8[16+idx] - 8]; } if( nza > 0 ) ctx++; if( nzb > 0 ) ctx += 2; return ctx + 4 * cat; }


static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, uint32_t *ext_features, uint32_t *ext2_features, uint32_t *ext3_features, uint32_t *kvm_features) { int i; int found = 0; for ( i = 0 ; i < 32 ; i++ ) if (feature_name[i] && !strcmp (flagname, feature_name[i])) { *features |= 1 << i; found = 1; } for ( i = 0 ; i < 32 ; i++ ) if (ext_feature_name[i] && !strcmp (flagname, ext_feature_name[i])) { *ext_features |= 1 << i; found = 1; } for ( i = 0 ; i < 32 ; i++ ) if (ext2_feature_name[i] && !strcmp (flagname, ext2_feature_name[i])) { *ext2_features |= 1 << i; found = 1; } for ( i = 0 ; i < 32 ; i++ ) if (ext3_feature_name[i] && !strcmp (flagname, ext3_feature_name[i])) { *ext3_features |= 1 << i; found = 1; } for ( i = 0 ; i < 32 ; i++ ) if (kvm_feature_name[i] && !strcmp (flagname, kvm_feature_name[i])) { *kvm_features |= 1 << i; found = 1; } if (!found) { fprintf(stderr, "CPU feature %s not found\n", flagname); } }


CPUPPCState *cpu_ppc_init(void) { CPUPPCState *env; cpu_exec_init(); env = qemu_mallocz(sizeof(CPUPPCState)); if (!env) return NULL; #if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE) setup_machine(env, 0); #else // env->spr[PVR] = 0; /* Basic PPC */ env->spr[PVR] = 0x00080100; /* G3 CPU */ // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */ // env->spr[PVR] = 0x00070100; /* IBM 750FX */ #endif tlb_flush(env, 1); #if defined (DO_SINGLE_STEP) /* Single step trace mode */ msr_se = 1; #endif msr_fp = 1; /* Allow floating point exceptions */ msr_me = 1; /* Allow machine check exceptions */ #if defined(CONFIG_USER_ONLY) msr_pr = 1; cpu_ppc_register(env, 0x00080000); #else env->nip = 0xFFFFFFFC; #endif env->access_type = ACCESS_INT; cpu_single_env = env; return env; }


static void vmxnet3_net_init(VMXNET3State *s) { DeviceState *d = DEVICE(s); VMW_CBPRN("vmxnet3_net_init called..."); qemu_macaddr_default_if_unset(&s->conf.macaddr); /* Windows guest will query the address that was set on init */ memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); s->mcast_list = NULL; s->mcast_list_len = 0; s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, object_get_typename(OBJECT(s)), d->id, s); s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); s->tx_sop = true; s->skip_current_tx_pkt = false; s->tx_pkt = NULL; s->rx_pkt = NULL; s->rx_vlan_stripping = false; s->lro_supported = false; if (s->peer_has_vhdr) { qemu_peer_set_vnet_hdr_len(qemu_get_queue(s->nic), sizeof(struct virtio_net_hdr)); qemu_peer_using_vnet_hdr(qemu_get_queue(s->nic), 1); } qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); }


static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, target_ulong sr, target_ulong eaddr, ppc_hash_pte32_t *pte) { CPUPPCState *env = &cpu->env; hwaddr pteg_off, pte_offset; hwaddr hash; uint32_t vsid, pgidx, ptem; vsid = sr & SR32_VSID; pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS; hash = vsid ^ pgidx; ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); /* Primary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " ptem=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, hash); pteg_off = get_pteg_offset32(cpu, hash); pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte); if (pte_offset == -1) { /* Secondary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " api=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, ~hash); pteg_off = get_pteg_offset32(cpu, ~hash); pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte); } return pte_offset; }


int av_expr_parse(AVExpr **expr, const char *s, const char * const *const_names, const char * const *func1_names, double (* const *funcs1)(void *, double), const char * const *func2_names, double (* const *funcs2)(void *, double, double), int log_offset, void *log_ctx) { Parser p = { 0 }; AVExpr *e = NULL; char *w = av_malloc(strlen(s) + 1); char *wp = w; const char *s0 = s; int ret = 0; if (!w) return AVERROR(ENOMEM); while (*s) if (!av_isspace(*s++)) *wp++ = s[-1]; *wp++ = 0; p.class = &eval_class; p.stack_index=100; p.s= w; p.const_names = const_names; p.funcs1 = funcs1; p.func1_names = func1_names; p.funcs2 = funcs2; p.func2_names = func2_names; p.log_offset = log_offset; p.log_ctx = log_ctx; if ((ret = parse_expr(&e, &p)) < 0) if (*p.s) { av_log(&p, AV_LOG_ERROR, "Invalid chars '%s' at the end of expression '%s'\n", p.s, s0); ret = AVERROR(EINVAL); if (!verify_expr(e)) { ret = AVERROR(EINVAL); e->var= av_mallocz(sizeof(double) *VARS); *expr = e; e = NULL; end: av_expr_free(e); av_free(w); return ret;


void spapr_create_phb(sPAPREnvironment *spapr, const char *busname, uint64_t buid, uint64_t mem_win_addr, uint64_t mem_win_size, uint64_t io_win_addr, uint64_t msi_win_addr) { DeviceState *dev; dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); if (busname) { qdev_prop_set_string(dev, "busname", g_strdup(busname)); } qdev_prop_set_uint64(dev, "buid", buid); qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr); qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size); qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr); qdev_prop_set_uint64(dev, "msi_win_addr", msi_win_addr); qdev_init_nofail(dev); }


static int expand_zero_clusters_in_l1(BlockDriverState *bs, uint64_t *l1_table, int l1_size, uint8_t **expanded_clusters, uint64_t *nb_clusters) { BDRVQcowState *s = bs->opaque; bool is_active_l1 = (l1_table == s->l1_table); uint64_t *l2_table = NULL; int ret; int i, j; if (!is_active_l1) { /* inactive L2 tables require a buffer to be stored in when loading * them from disk */ l2_table = qemu_blockalign(bs, s->cluster_size); } for (i = 0; i < l1_size; i++) { uint64_t l2_offset = l1_table[i] & L1E_OFFSET_MASK; bool l2_dirty = false; if (!l2_offset) { /* unallocated */ continue; } if (is_active_l1) { /* get active L2 tables from cache */ ret = qcow2_cache_get(bs, s->l2_table_cache, l2_offset, (void **)&l2_table); } else { /* load inactive L2 tables from disk */ ret = bdrv_read(bs->file, l2_offset / BDRV_SECTOR_SIZE, (void *)l2_table, s->cluster_sectors); } if (ret < 0) { goto fail; } for (j = 0; j < s->l2_size; j++) { uint64_t l2_entry = be64_to_cpu(l2_table[j]); int64_t offset = l2_entry & L2E_OFFSET_MASK, cluster_index; int cluster_type = qcow2_get_cluster_type(l2_entry); bool preallocated = offset != 0; if (cluster_type == QCOW2_CLUSTER_NORMAL) { cluster_index = offset >> s->cluster_bits; assert((cluster_index >= 0) && (cluster_index < *nb_clusters)); if ((*expanded_clusters)[cluster_index / 8] & (1 << (cluster_index % 8))) { /* Probably a shared L2 table; this cluster was a zero * cluster which has been expanded, its refcount * therefore most likely requires an update. */ ret = qcow2_update_cluster_refcount(bs, cluster_index, 1, QCOW2_DISCARD_NEVER); if (ret < 0) { goto fail; } /* Since we just increased the refcount, the COPIED flag may * no longer be set. */ l2_table[j] = cpu_to_be64(l2_entry & ~QCOW_OFLAG_COPIED); l2_dirty = true; } continue; } else if (qcow2_get_cluster_type(l2_entry) != QCOW2_CLUSTER_ZERO) { continue; } if (!preallocated) { if (!bs->backing_hd) { /* not backed; therefore we can simply deallocate the * cluster */ l2_table[j] = 0; l2_dirty = true; continue; } offset = qcow2_alloc_clusters(bs, s->cluster_size); if (offset < 0) { ret = offset; goto fail; } } ret = qcow2_pre_write_overlap_check(bs, QCOW2_OL_DEFAULT, offset, s->cluster_size); if (ret < 0) { if (!preallocated) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_ALWAYS); } goto fail; } ret = bdrv_write_zeroes(bs->file, offset / BDRV_SECTOR_SIZE, s->cluster_sectors); if (ret < 0) { if (!preallocated) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_ALWAYS); } goto fail; } l2_table[j] = cpu_to_be64(offset | QCOW_OFLAG_COPIED); l2_dirty = true; cluster_index = offset >> s->cluster_bits; if (cluster_index >= *nb_clusters) { uint64_t old_bitmap_size = (*nb_clusters + 7) / 8; uint64_t new_bitmap_size; /* The offset may lie beyond the old end of the underlying image * file for growable files only */ assert(bs->file->growable); *nb_clusters = size_to_clusters(s, bs->file->total_sectors * BDRV_SECTOR_SIZE); new_bitmap_size = (*nb_clusters + 7) / 8; *expanded_clusters = g_realloc(*expanded_clusters, new_bitmap_size); /* clear the newly allocated space */ memset(&(*expanded_clusters)[old_bitmap_size], 0, new_bitmap_size - old_bitmap_size); } assert((cluster_index >= 0) && (cluster_index < *nb_clusters)); (*expanded_clusters)[cluster_index / 8] |= 1 << (cluster_index % 8); } if (is_active_l1) { if (l2_dirty) { qcow2_cache_entry_mark_dirty(s->l2_table_cache, l2_table); qcow2_cache_depends_on_flush(s->l2_table_cache); } ret = qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); if (ret < 0) { l2_table = NULL; goto fail; } } else { if (l2_dirty) { ret = qcow2_pre_write_overlap_check(bs, QCOW2_OL_DEFAULT & ~(QCOW2_OL_INACTIVE_L2 | QCOW2_OL_ACTIVE_L2), l2_offset, s->cluster_size); if (ret < 0) { goto fail; } ret = bdrv_write(bs->file, l2_offset / BDRV_SECTOR_SIZE, (void *)l2_table, s->cluster_sectors); if (ret < 0) { goto fail; } } } } ret = 0; fail: if (l2_table) { if (!is_active_l1) { qemu_vfree(l2_table); } else { if (ret < 0) { qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); } else { ret = qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); } } } return ret; }


static void virtio_scsi_bad_req(void) { error_report("wrong size for virtio-scsi headers"); exit(1); }


static int h261_decode_mb(H261Context *h, DCTELEM block[6][64]) { MpegEncContext * const s = &h->s; int i, cbp, xy, old_mtype; cbp = 63; // Read mba do{ h->mba_diff = get_vlc2(&s->gb, h261_mba_vlc.table, H261_MBA_VLC_BITS, 2)+1; } while( h->mba_diff == MAX_MBA + 1 ); // stuffing if ( h->mba_diff < 0 ) return -1; h->current_mba += h->mba_diff; if ( h->current_mba > MAX_MBA ) return -1; s->mb_x= ((h->gob_number-1) % 2) * 11 + ((h->current_mba-1) % 11); s->mb_y= ((h->gob_number-1) / 2) * 3 + ((h->current_mba-1) / 11); xy = s->mb_x + s->mb_y * s->mb_stride; ff_init_block_index(s); ff_update_block_index(s); s->dsp.clear_blocks(s->block[0]); // Read mtype old_mtype = h->mtype; h->mtype = get_vlc2(&s->gb, h261_mtype_vlc.table, H261_MTYPE_VLC_BITS, 2); h->mtype = h261_mtype_map[h->mtype]; if (IS_FIL (h->mtype)) h->loop_filter = 1; // Read mquant if ( IS_QUANT ( h->mtype ) ){ ff_set_qscale(s, get_bits(&s->gb, 5)); } s->mb_intra = IS_INTRA4x4(h->mtype); // Read mv if ( IS_16X16 ( h->mtype ) ){ // Motion vector data is included for all MC macroblocks. MVD is obtained from the macroblock vector by subtracting the // vector of the preceding macroblock. For this calculation the vector of the preceding macroblock is regarded as zero in the // following three situations: // 1) evaluating MVD for macroblocks 1, 12 and 23; // 2) evaluating MVD for macroblocks in which MBA does not represent a difference of 1; // 3) MTYPE of the previous macroblock was not MC. if ( ( h->current_mba == 1 ) || ( h->current_mba == 12 ) || ( h->current_mba == 23 ) || ( h->mba_diff != 1) || ( !IS_16X16 ( old_mtype ) )) { h->current_mv_x = 0; h->current_mv_y = 0; } h->current_mv_x= decode_mv_component(&s->gb, h->current_mv_x); h->current_mv_y= decode_mv_component(&s->gb, h->current_mv_y); } // Read cbp if ( HAS_CBP( h->mtype ) ){ cbp = get_vlc2(&s->gb, h261_cbp_vlc.table, H261_CBP_VLC_BITS, 2) + 1; } if(s->mb_intra){ s->current_picture.mb_type[xy]= MB_TYPE_INTRA; goto intra; } //set motion vectors s->mv_dir = MV_DIR_FORWARD; s->mv_type = MV_TYPE_16X16; s->current_picture.mb_type[xy]= MB_TYPE_16x16 | MB_TYPE_L0; if(IS_16X16 ( h->mtype )){ s->mv[0][0][0] = h->current_mv_x * 2;//gets divided by 2 in motion compensation s->mv[0][0][1] = h->current_mv_y * 2; } else{ h->current_mv_x = s->mv[0][0][0] = 0; h->current_mv_x = s->mv[0][0][1] = 0; } intra: /* decode each block */ if(s->mb_intra || HAS_CBP(h->mtype)){ for (i = 0; i < 6; i++) { if (h261_decode_block(h, block[i], i, cbp&32) < 0){ return -1; } cbp+=cbp; } } /* per-MB end of slice check */ { int v= show_bits(&s->gb, 15); if(get_bits_count(&s->gb) + 15 > s->gb.size_in_bits){ v>>= get_bits_count(&s->gb) + 15 - s->gb.size_in_bits; } if(v==0){ return SLICE_END; } } return SLICE_OK; }


static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q) { int next, i; int priority; next = -1; priority = -1; if (!q->pending) { /* IRQ bitmap is empty */ goto out; } for (i = 0; i < opp->max_irq; i++) { if (IRQ_testbit(q, i)) { DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n", i, IPVP_PRIORITY(opp->src[i].ipvp), priority); if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) { next = i; priority = IPVP_PRIORITY(opp->src[i].ipvp); } } } out: q->next = next; q->priority = priority; }


static void test_visitor_out_alternate(TestOutputVisitorData *data, const void *unused) { QObject *arg; UserDefAlternate *tmp; QDict *qdict; tmp = g_new0(UserDefAlternate, 1); tmp->type = QTYPE_QINT; tmp->u.i = 42; visit_type_UserDefAlternate(data->ov, NULL, &tmp, &error_abort); arg = qmp_output_get_qobject(data->qov); g_assert(qobject_type(arg) == QTYPE_QINT); g_assert_cmpint(qint_get_int(qobject_to_qint(arg)), ==, 42); qapi_free_UserDefAlternate(tmp); qobject_decref(arg); tmp = g_new0(UserDefAlternate, 1); tmp->type = QTYPE_QSTRING; tmp->u.s = g_strdup("hello"); visit_type_UserDefAlternate(data->ov, NULL, &tmp, &error_abort); arg = qmp_output_get_qobject(data->qov); g_assert(qobject_type(arg) == QTYPE_QSTRING); g_assert_cmpstr(qstring_get_str(qobject_to_qstring(arg)), ==, "hello"); qapi_free_UserDefAlternate(tmp); qobject_decref(arg); tmp = g_new0(UserDefAlternate, 1); tmp->type = QTYPE_QDICT; tmp->u.udfu.integer = 1; tmp->u.udfu.string = g_strdup("str"); tmp->u.udfu.enum1 = ENUM_ONE_VALUE1; tmp->u.udfu.u.value1 = g_new0(UserDefA, 1); tmp->u.udfu.u.value1->boolean = true; visit_type_UserDefAlternate(data->ov, NULL, &tmp, &error_abort); arg = qmp_output_get_qobject(data->qov); g_assert_cmpint(qobject_type(arg), ==, QTYPE_QDICT); qdict = qobject_to_qdict(arg); g_assert_cmpint(qdict_size(qdict), ==, 4); g_assert_cmpint(qdict_get_int(qdict, "integer"), ==, 1); g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, "str"); g_assert_cmpstr(qdict_get_str(qdict, "enum1"), ==, "value1"); g_assert_cmpint(qdict_get_bool(qdict, "boolean"), ==, true); qapi_free_UserDefAlternate(tmp); qobject_decref(arg); }


static double get_volume(CompandContext *s, double in_lin) { CompandSegment *cs; double in_log, out_log; int i; if (in_lin < s->in_min_lin) return s->out_min_lin; in_log = log(in_lin); for (i = 1;; i++) if (in_log <= s->segments[i + 1].x) break; cs = &s->segments[i]; in_log -= cs->x; out_log = cs->y + in_log * (cs->a * in_log + cs->b); return exp(out_log); }


static void qemu_co_queue_next_bh(void *opaque) { struct unlock_bh *unlock_bh = opaque; Coroutine *next; trace_qemu_co_queue_next_bh(); while ((next = QTAILQ_FIRST(&unlock_bh_queue))) { QTAILQ_REMOVE(&unlock_bh_queue, next, co_queue_next); qemu_coroutine_enter(next, NULL); } qemu_bh_delete(unlock_bh->bh); qemu_free(unlock_bh); }


static void store_reg(DisasContext *s, int reg, TCGv var) { if (reg == 15) { tcg_gen_andi_i32(var, var, ~1); s->is_jmp = DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); dead_tmp(var); }


static int vnc_display_get_addresses(QemuOpts *opts, bool reverse, SocketAddress ***retsaddr, size_t *retnsaddr, SocketAddress ***retwsaddr, size_t *retnwsaddr, Error **errp) { SocketAddress *saddr = NULL; SocketAddress *wsaddr = NULL; QemuOptsIter addriter; const char *addr; int to = qemu_opt_get_number(opts, "to", 0); bool has_ipv4 = qemu_opt_get(opts, "ipv4"); bool has_ipv6 = qemu_opt_get(opts, "ipv6"); bool ipv4 = qemu_opt_get_bool(opts, "ipv4", false); bool ipv6 = qemu_opt_get_bool(opts, "ipv6", false); size_t i; int displaynum = -1; int ret = -1; *retsaddr = NULL; *retnsaddr = 0; *retwsaddr = NULL; *retnwsaddr = 0; addr = qemu_opt_get(opts, "vnc"); if (addr == NULL || g_str_equal(addr, "none")) { ret = 0; goto cleanup; } if (qemu_opt_get(opts, "websocket") && !qcrypto_hash_supports(QCRYPTO_HASH_ALG_SHA1)) { error_setg(errp, "SHA1 hash support is required for websockets"); goto cleanup; } qemu_opt_iter_init(&addriter, opts, "vnc"); while ((addr = qemu_opt_iter_next(&addriter)) != NULL) { int rv; rv = vnc_display_get_address(addr, false, reverse, 0, to, has_ipv4, has_ipv6, ipv4, ipv6, &saddr, errp); if (rv < 0) { goto cleanup; } /* Historical compat - first listen address can be used * to set the default websocket port */ if (displaynum == -1) { displaynum = rv; } *retsaddr = g_renew(SocketAddress *, *retsaddr, *retnsaddr + 1); (*retsaddr)[(*retnsaddr)++] = saddr; } /* If we had multiple primary displays, we don't do defaults * for websocket, and require explicit config instead. */ if (*retnsaddr > 1) { displaynum = -1; } qemu_opt_iter_init(&addriter, opts, "websocket"); while ((addr = qemu_opt_iter_next(&addriter)) != NULL) { if (vnc_display_get_address(addr, true, reverse, displaynum, to, has_ipv4, has_ipv6, ipv4, ipv6, &wsaddr, errp) < 0) { goto cleanup; } /* Historical compat - if only a single listen address was * provided, then this is used to set the default listen * address for websocket too */ if (*retnsaddr == 1 && (*retsaddr)[0]->type == SOCKET_ADDRESS_TYPE_INET && wsaddr->type == SOCKET_ADDRESS_TYPE_INET && g_str_equal(wsaddr->u.inet.host, "") && !g_str_equal((*retsaddr)[0]->u.inet.host, "")) { g_free(wsaddr->u.inet.host); wsaddr->u.inet.host = g_strdup((*retsaddr)[0]->u.inet.host); } *retwsaddr = g_renew(SocketAddress *, *retwsaddr, *retnwsaddr + 1); (*retwsaddr)[(*retnwsaddr)++] = wsaddr; } ret = 0; cleanup: if (ret < 0) { for (i = 0; i < *retnsaddr; i++) { qapi_free_SocketAddress((*retsaddr)[i]); } g_free(*retsaddr); for (i = 0; i < *retnwsaddr; i++) { qapi_free_SocketAddress((*retwsaddr)[i]); } g_free(*retwsaddr); *retsaddr = *retwsaddr = NULL; *retnsaddr = *retnwsaddr = 0; } return ret; }


uint64_t HELPER(neon_abdl_u64)(uint32_t a, uint32_t b) { uint64_t result; DO_ABD(result, a, b, uint32_t); return result; }


static void virtio_net_handle_tx(VirtIODevice *vdev, VirtQueue *vq) { VirtIONet *n = to_virtio_net(vdev); if (n->tx_waiting) { virtio_queue_set_notification(vq, 1); qemu_del_timer(n->tx_timer); n->tx_waiting = 0; virtio_net_flush_tx(n, vq); } else { qemu_mod_timer(n->tx_timer, qemu_get_clock(vm_clock) + n->tx_timeout); n->tx_waiting = 1; virtio_queue_set_notification(vq, 0); } }


static void encode_picture(MpegEncContext *s, int picture_number) { int mb_x, mb_y, last_gob, pdif = 0; int i; int bits; MpegEncContext best_s, backup_s; UINT8 bit_buf[7][3000]; //FIXME check that this is ALLWAYS large enogh for a MB s->picture_number = picture_number; s->block_wrap[0]= s->block_wrap[1]= s->block_wrap[2]= s->block_wrap[3]= s->mb_width*2 + 2; s->block_wrap[4]= s->block_wrap[5]= s->mb_width + 2; /* Reset the average MB variance */ s->avg_mb_var = 0; s->mc_mb_var = 0; /* we need to initialize some time vars before we can encode b-frames */ if (s->h263_pred && !s->h263_msmpeg4) ff_set_mpeg4_time(s, s->picture_number); /* Estimate motion for every MB */ if(s->pict_type != I_TYPE){ // int16_t (*tmp)[2]= s->p_mv_table; // s->p_mv_table= s->last_mv_table; // s->last_mv_table= s->mv_table; for(mb_y=0; mb_y < s->mb_height; mb_y++) { s->block_index[0]= s->block_wrap[0]*(mb_y*2 + 1) - 1; s->block_index[1]= s->block_wrap[0]*(mb_y*2 + 1); s->block_index[2]= s->block_wrap[0]*(mb_y*2 + 2) - 1; s->block_index[3]= s->block_wrap[0]*(mb_y*2 + 2); for(mb_x=0; mb_x < s->mb_width; mb_x++) { s->mb_x = mb_x; s->mb_y = mb_y; s->block_index[0]+=2; s->block_index[1]+=2; s->block_index[2]+=2; s->block_index[3]+=2; /* compute motion vector & mb_type and store in context */ if(s->pict_type==B_TYPE) ff_estimate_b_frame_motion(s, mb_x, mb_y); else ff_estimate_p_frame_motion(s, mb_x, mb_y); // s->mb_type[mb_y*s->mb_width + mb_x]=MB_TYPE_INTER; } } emms_c(); }else if(s->pict_type == I_TYPE){ /* I-Frame */ //FIXME do we need to zero them? memset(s->motion_val[0], 0, sizeof(INT16)*(s->mb_width*2 + 2)*(s->mb_height*2 + 2)*2); memset(s->p_mv_table , 0, sizeof(INT16)*(s->mb_width+2)*(s->mb_height+2)*2); memset(s->mb_type , MB_TYPE_INTRA, sizeof(UINT8)*s->mb_width*s->mb_height); } if(s->avg_mb_var < s->mc_mb_var && s->pict_type == P_TYPE){ //FIXME subtract MV bits s->pict_type= I_TYPE; memset(s->mb_type , MB_TYPE_INTRA, sizeof(UINT8)*s->mb_width*s->mb_height); if(s->max_b_frames==0){ s->input_pict_type= I_TYPE; s->input_picture_in_gop_number=0; } //printf("Scene change detected, encoding as I Frame\n"); } if(s->pict_type==P_TYPE || s->pict_type==S_TYPE) s->f_code= ff_get_best_fcode(s, s->p_mv_table, MB_TYPE_INTER); ff_fix_long_p_mvs(s); if(s->pict_type==B_TYPE){ s->f_code= ff_get_best_fcode(s, s->b_forw_mv_table, MB_TYPE_FORWARD); s->b_code= ff_get_best_fcode(s, s->b_back_mv_table, MB_TYPE_BACKWARD); ff_fix_long_b_mvs(s, s->b_forw_mv_table, s->f_code, MB_TYPE_FORWARD); ff_fix_long_b_mvs(s, s->b_back_mv_table, s->b_code, MB_TYPE_BACKWARD); ff_fix_long_b_mvs(s, s->b_bidir_forw_mv_table, s->f_code, MB_TYPE_BIDIR); ff_fix_long_b_mvs(s, s->b_bidir_back_mv_table, s->b_code, MB_TYPE_BIDIR); } //printf("f_code %d ///\n", s->f_code); // printf("%d %d\n", s->avg_mb_var, s->mc_mb_var); if(s->flags&CODEC_FLAG_PASS2) s->qscale = ff_rate_estimate_qscale_pass2(s); else if (!s->fixed_qscale) s->qscale = ff_rate_estimate_qscale(s); /* precompute matrix */ if (s->out_format == FMT_MJPEG) { /* for mjpeg, we do include qscale in the matrix */ s->intra_matrix[0] = default_intra_matrix[0]; for(i=1;i<64;i++) s->intra_matrix[i] = (default_intra_matrix[i] * s->qscale) >> 3; convert_matrix(s->q_intra_matrix, s->q_intra_matrix16, s->intra_matrix, 8); } else { convert_matrix(s->q_intra_matrix, s->q_intra_matrix16, s->intra_matrix, s->qscale); convert_matrix(s->q_non_intra_matrix, s->q_non_intra_matrix16, s->non_intra_matrix, s->qscale); } s->last_bits= get_bit_count(&s->pb); switch(s->out_format) { case FMT_MJPEG: mjpeg_picture_header(s); break; case FMT_H263: if (s->h263_msmpeg4) msmpeg4_encode_picture_header(s, picture_number); else if (s->h263_pred) mpeg4_encode_picture_header(s, picture_number); else if (s->h263_rv10) rv10_encode_picture_header(s, picture_number); else h263_encode_picture_header(s, picture_number); break; case FMT_MPEG1: mpeg1_encode_picture_header(s, picture_number); break; } bits= get_bit_count(&s->pb); s->header_bits= bits - s->last_bits; s->last_bits= bits; s->mv_bits=0; s->misc_bits=0; s->i_tex_bits=0; s->p_tex_bits=0; s->i_count=0; s->p_count=0; s->skip_count=0; /* init last dc values */ /* note: quant matrix value (8) is implied here */ s->last_dc[0] = 128; s->last_dc[1] = 128; s->last_dc[2] = 128; s->mb_incr = 1; s->last_mv[0][0][0] = 0; s->last_mv[0][0][1] = 0; /* Get the GOB height based on picture height */ if (s->out_format == FMT_H263 && !s->h263_pred && !s->h263_msmpeg4) { if (s->height <= 400) s->gob_index = 1; else if (s->height <= 800) s->gob_index = 2; else s->gob_index = 4; } s->avg_mb_var = s->avg_mb_var / s->mb_num; for(mb_y=0; mb_y < s->mb_height; mb_y++) { /* Put GOB header based on RTP MTU */ /* TODO: Put all this stuff in a separate generic function */ if (s->rtp_mode) { if (!mb_y) { s->ptr_lastgob = s->pb.buf; s->ptr_last_mb_line = s->pb.buf; } else if (s->out_format == FMT_H263 && !s->h263_pred && !s->h263_msmpeg4 && !(mb_y % s->gob_index)) { last_gob = h263_encode_gob_header(s, mb_y); if (last_gob) { s->first_gob_line = 1; } } } s->block_index[0]= s->block_wrap[0]*(mb_y*2 + 1) - 1; s->block_index[1]= s->block_wrap[0]*(mb_y*2 + 1); s->block_index[2]= s->block_wrap[0]*(mb_y*2 + 2) - 1; s->block_index[3]= s->block_wrap[0]*(mb_y*2 + 2); s->block_index[4]= s->block_wrap[4]*(mb_y + 1) + s->block_wrap[0]*(s->mb_height*2 + 2); s->block_index[5]= s->block_wrap[4]*(mb_y + 1 + s->mb_height + 2) + s->block_wrap[0]*(s->mb_height*2 + 2); for(mb_x=0; mb_x < s->mb_width; mb_x++) { const int mb_type= s->mb_type[mb_y * s->mb_width + mb_x]; const int xy= (mb_y+1) * (s->mb_width+2) + mb_x + 1; PutBitContext pb; int d; int dmin=10000000; int best=0; s->mb_x = mb_x; s->mb_y = mb_y; s->block_index[0]+=2; s->block_index[1]+=2; s->block_index[2]+=2; s->block_index[3]+=2; s->block_index[4]++; s->block_index[5]++; if(mb_type & (mb_type-1)){ // more than 1 MB type possible int next_block=0; pb= s->pb; copy_context_before_encode(&backup_s, s, -1); if(mb_type&MB_TYPE_INTER){ s->mv_dir = MV_DIR_FORWARD; s->mv_type = MV_TYPE_16X16; s->mb_intra= 0; s->mv[0][0][0] = s->p_mv_table[xy][0]; s->mv[0][0][1] = s->p_mv_table[xy][1]; init_put_bits(&s->pb, bit_buf[1], 3000, NULL, NULL); s->block= s->blocks[next_block]; s->last_bits= 0; //done in copy_context_before_encode but we skip that here encode_mb(s, s->mv[0][0][0], s->mv[0][0][1]); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_INTER); best=1; next_block^=1; } } if(mb_type&MB_TYPE_INTER4V){ copy_context_before_encode(s, &backup_s, MB_TYPE_INTER4V); s->mv_dir = MV_DIR_FORWARD; s->mv_type = MV_TYPE_8X8; s->mb_intra= 0; for(i=0; i<4; i++){ s->mv[0][i][0] = s->motion_val[s->block_index[i]][0]; s->mv[0][i][1] = s->motion_val[s->block_index[i]][1]; } init_put_bits(&s->pb, bit_buf[2], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, 0, 0); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_INTER4V); best=2; next_block^=1; } } if(mb_type&MB_TYPE_FORWARD){ copy_context_before_encode(s, &backup_s, MB_TYPE_FORWARD); s->mv_dir = MV_DIR_FORWARD; s->mv_type = MV_TYPE_16X16; s->mb_intra= 0; s->mv[0][0][0] = s->b_forw_mv_table[xy][0]; s->mv[0][0][1] = s->b_forw_mv_table[xy][1]; init_put_bits(&s->pb, bit_buf[3], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, s->mv[0][0][0], s->mv[0][0][1]); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_FORWARD); best=3; next_block^=1; } } if(mb_type&MB_TYPE_BACKWARD){ copy_context_before_encode(s, &backup_s, MB_TYPE_BACKWARD); s->mv_dir = MV_DIR_BACKWARD; s->mv_type = MV_TYPE_16X16; s->mb_intra= 0; s->mv[1][0][0] = s->b_back_mv_table[xy][0]; s->mv[1][0][1] = s->b_back_mv_table[xy][1]; init_put_bits(&s->pb, bit_buf[4], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, s->mv[1][0][0], s->mv[1][0][1]); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_BACKWARD); best=4; next_block^=1; } } if(mb_type&MB_TYPE_BIDIR){ copy_context_before_encode(s, &backup_s, MB_TYPE_BIDIR); s->mv_dir = MV_DIR_FORWARD | MV_DIR_BACKWARD; s->mv_type = MV_TYPE_16X16; s->mb_intra= 0; s->mv[0][0][0] = s->b_bidir_forw_mv_table[xy][0]; s->mv[0][0][1] = s->b_bidir_forw_mv_table[xy][1]; s->mv[1][0][0] = s->b_bidir_back_mv_table[xy][0]; s->mv[1][0][1] = s->b_bidir_back_mv_table[xy][1]; init_put_bits(&s->pb, bit_buf[5], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, 0, 0); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_BIDIR); best=5; next_block^=1; } } if(mb_type&MB_TYPE_DIRECT){ copy_context_before_encode(s, &backup_s, MB_TYPE_DIRECT); s->mv_dir = MV_DIR_FORWARD | MV_DIR_BACKWARD | MV_DIRECT; s->mv_type = MV_TYPE_16X16; //FIXME s->mb_intra= 0; s->mv[0][0][0] = s->b_direct_forw_mv_table[xy][0]; s->mv[0][0][1] = s->b_direct_forw_mv_table[xy][1]; s->mv[1][0][0] = s->b_direct_back_mv_table[xy][0]; s->mv[1][0][1] = s->b_direct_back_mv_table[xy][1]; init_put_bits(&s->pb, bit_buf[6], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, s->b_direct_mv_table[xy][0], s->b_direct_mv_table[xy][1]); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_DIRECT); best=6; next_block^=1; } } if(mb_type&MB_TYPE_INTRA){ copy_context_before_encode(s, &backup_s, MB_TYPE_INTRA); s->mv_dir = MV_DIR_FORWARD; s->mv_type = MV_TYPE_16X16; s->mb_intra= 1; s->mv[0][0][0] = 0; s->mv[0][0][1] = 0; init_put_bits(&s->pb, bit_buf[0], 3000, NULL, NULL); s->block= s->blocks[next_block]; encode_mb(s, 0, 0); d= get_bit_count(&s->pb); if(d<dmin){ flush_put_bits(&s->pb); dmin=d; copy_context_after_encode(&best_s, s, MB_TYPE_INTRA); best=0; next_block^=1; } /* force cleaning of ac/dc pred stuff if needed ... */ if(s->h263_pred || s->h263_aic) s->mbintra_table[mb_x + mb_y*s->mb_width]=1; } copy_context_after_encode(s, &best_s, -1); copy_bits(&pb, bit_buf[best], dmin); s->pb= pb; s->last_bits= get_bit_count(&s->pb); } else { int motion_x, motion_y; s->mv_type=MV_TYPE_16X16; // only one MB-Type possible switch(mb_type){ case MB_TYPE_INTRA: s->mv_dir = MV_DIR_FORWARD; s->mb_intra= 1; motion_x= s->mv[0][0][0] = 0; motion_y= s->mv[0][0][1] = 0; break; case MB_TYPE_INTER: s->mv_dir = MV_DIR_FORWARD; s->mb_intra= 0; motion_x= s->mv[0][0][0] = s->p_mv_table[xy][0]; motion_y= s->mv[0][0][1] = s->p_mv_table[xy][1]; break; case MB_TYPE_DIRECT: s->mv_dir = MV_DIR_FORWARD | MV_DIR_BACKWARD | MV_DIRECT; s->mb_intra= 0; motion_x=s->b_direct_mv_table[xy][0]; motion_y=s->b_direct_mv_table[xy][1]; s->mv[0][0][0] = s->b_direct_forw_mv_table[xy][0]; s->mv[0][0][1] = s->b_direct_forw_mv_table[xy][1]; s->mv[1][0][0] = s->b_direct_back_mv_table[xy][0]; s->mv[1][0][1] = s->b_direct_back_mv_table[xy][1]; break; case MB_TYPE_BIDIR: s->mv_dir = MV_DIR_FORWARD | MV_DIR_BACKWARD; s->mb_intra= 0; motion_x=0; motion_y=0; s->mv[0][0][0] = s->b_bidir_forw_mv_table[xy][0]; s->mv[0][0][1] = s->b_bidir_forw_mv_table[xy][1]; s->mv[1][0][0] = s->b_bidir_back_mv_table[xy][0]; s->mv[1][0][1] = s->b_bidir_back_mv_table[xy][1]; break; case MB_TYPE_BACKWARD: s->mv_dir = MV_DIR_BACKWARD; s->mb_intra= 0; motion_x= s->mv[1][0][0] = s->b_back_mv_table[xy][0]; motion_y= s->mv[1][0][1] = s->b_back_mv_table[xy][1]; break; case MB_TYPE_FORWARD: s->mv_dir = MV_DIR_FORWARD; s->mb_intra= 0; motion_x= s->mv[0][0][0] = s->b_forw_mv_table[xy][0]; motion_y= s->mv[0][0][1] = s->b_forw_mv_table[xy][1]; // printf(" %d %d ", motion_x, motion_y); break; default: motion_x=motion_y=0; //gcc warning fix printf("illegal MB type\n"); } encode_mb(s, motion_x, motion_y); } /* clean the MV table in IPS frames for direct mode in B frames */ if(s->mb_intra /* && I,P,S_TYPE */){ s->p_mv_table[xy][0]=0; s->p_mv_table[xy][1]=0; } MPV_decode_mb(s, s->block); } /* Obtain average GOB size for RTP */ if (s->rtp_mode) { if (!mb_y) s->mb_line_avgsize = pbBufPtr(&s->pb) - s->ptr_last_mb_line; else if (!(mb_y % s->gob_index)) { s->mb_line_avgsize = (s->mb_line_avgsize + pbBufPtr(&s->pb) - s->ptr_last_mb_line) >> 1; s->ptr_last_mb_line = pbBufPtr(&s->pb); } //fprintf(stderr, "\nMB line: %d\tSize: %u\tAvg. Size: %u", s->mb_y, // (s->pb.buf_ptr - s->ptr_last_mb_line), s->mb_line_avgsize); s->first_gob_line = 0; } } emms_c(); if (s->h263_msmpeg4 && s->msmpeg4_version<4 && s->pict_type == I_TYPE) msmpeg4_encode_ext_header(s); //if (s->gob_number) // fprintf(stderr,"\nNumber of GOB: %d", s->gob_number); /* Send the last GOB if RTP */ if (s->rtp_mode) { flush_put_bits(&s->pb); pdif = pbBufPtr(&s->pb) - s->ptr_lastgob; /* Call the RTP callback to send the last GOB */ if (s->rtp_callback) s->rtp_callback(s->ptr_lastgob, pdif, s->gob_number); s->ptr_lastgob = pbBufPtr(&s->pb); //fprintf(stderr,"\nGOB: %2d size: %d (last)", s->gob_number, pdif); } }


static void store_word(DBDMA_channel *ch, int key, uint32_t addr, uint16_t len) { dbdma_cmd *current = &ch->current; uint32_t val; DBDMA_DPRINTF("store_word\n"); /* only implements KEY_SYSTEM */ if (key != KEY_SYSTEM) { printf("DBDMA: STORE_WORD, unimplemented key %x\n", key); kill_channel(ch); return; } val = current->cmd_dep; if (len == 2) val >>= 16; else if (len == 1) val >>= 24; cpu_physical_memory_write(addr, (uint8_t*)&val, len); if (conditional_wait(ch)) goto wait; current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); dbdma_cmdptr_save(ch); ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH); conditional_interrupt(ch); next(ch); wait: qemu_bh_schedule(dbdma_bh); }


static int decode_cabac_mb_ref( H264Context *h, int list, int n ) { int refa = h->ref_cache[list][scan8[n] - 1]; int refb = h->ref_cache[list][scan8[n] - 8]; int ref = 0; int ctx = 0; if( h->slice_type_nos == FF_B_TYPE) { if( refa > 0 && !h->direct_cache[scan8[n] - 1] ) ctx++; if( refb > 0 && !h->direct_cache[scan8[n] - 8] ) ctx += 2; } else { if( refa > 0 ) ctx++; if( refb > 0 ) ctx += 2; } while( get_cabac( &h->cabac, &h->cabac_state[54+ctx] ) ) { ref++; if( ctx < 4 ) ctx = 4; else ctx = 5; if(ref >= 32 /*h->ref_list[list]*/){ av_log(h->s.avctx, AV_LOG_ERROR, "overflow in decode_cabac_mb_ref\n"); return 0; //FIXME we should return -1 and check the return everywhere } } return ref; }


static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) check_insn(ctx, ISA_MIPS32); if (use_icount) gen_io_start(); switch (reg) { case 0: switch (sel) { case 0: gen_helper_mtc0_index(cpu_env, arg); rn = "Index"; break; case 1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); rn = "MVPControl"; break; case 2: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ rn = "MVPConf0"; break; case 3: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ rn = "MVPConf1"; break; default: goto cp0_unimplemented; } break; case 1: switch (sel) { case 0: /* ignored */ rn = "Random"; break; case 1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpecontrol(cpu_env, arg); rn = "VPEControl"; break; case 2: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf0(cpu_env, arg); rn = "VPEConf0"; break; case 3: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf1(cpu_env, arg); rn = "VPEConf1"; break; case 4: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_yqmask(cpu_env, arg); rn = "YQMask"; break; case 5: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeopt(cpu_env, arg); rn = "VPEOpt"; break; default: goto cp0_unimplemented; } break; case 2: switch (sel) { case 0: gen_helper_mtc0_entrylo0(cpu_env, arg); rn = "EntryLo0"; break; case 1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); rn = "TCStatus"; break; case 2: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); rn = "TCBind"; break; case 3: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); rn = "TCRestart"; break; case 4: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); rn = "TCHalt"; break; case 5: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); rn = "TCContext"; break; case 6: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); rn = "TCSchedule"; break; case 7: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); rn = "TCScheFBack"; break; default: goto cp0_unimplemented; } break; case 3: switch (sel) { case 0: gen_helper_mtc0_entrylo1(cpu_env, arg); rn = "EntryLo1"; break; default: goto cp0_unimplemented; } break; case 4: switch (sel) { case 0: gen_helper_mtc0_context(cpu_env, arg); rn = "Context"; break; case 1: // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; goto cp0_unimplemented; // break; case 2: CP0_CHECK(ctx->ulri); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); rn = "UserLocal"; break; default: goto cp0_unimplemented; } break; case 5: switch (sel) { case 0: gen_helper_mtc0_pagemask(cpu_env, arg); rn = "PageMask"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); rn = "PageGrain"; break; default: goto cp0_unimplemented; } break; case 6: switch (sel) { case 0: gen_helper_mtc0_wired(cpu_env, arg); rn = "Wired"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); rn = "SRSConf0"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); rn = "SRSConf1"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); rn = "SRSConf2"; break; case 4: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); rn = "SRSConf3"; break; case 5: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); rn = "SRSConf4"; break; default: goto cp0_unimplemented; } break; case 7: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->bstate = BS_STOP; rn = "HWREna"; break; default: goto cp0_unimplemented; } break; case 8: switch (sel) { case 0: /* ignored */ rn = "BadVAddr"; break; case 1: /* ignored */ rn = "BadInstr"; break; case 2: /* ignored */ rn = "BadInstrP"; break; default: goto cp0_unimplemented; } break; case 9: switch (sel) { case 0: gen_helper_mtc0_count(cpu_env, arg); rn = "Count"; break; /* 6,7 are implementation dependent */ default: goto cp0_unimplemented; } break; case 10: switch (sel) { case 0: gen_helper_mtc0_entryhi(cpu_env, arg); rn = "EntryHi"; break; default: goto cp0_unimplemented; } break; case 11: switch (sel) { case 0: gen_helper_mtc0_compare(cpu_env, arg); rn = "Compare"; break; /* 6,7 are implementation dependent */ default: goto cp0_unimplemented; } break; case 12: switch (sel) { case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Status"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSMap"; break; default: goto cp0_unimplemented; } break; case 13: switch (sel) { case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_cause(cpu_env, arg); rn = "Cause"; break; default: goto cp0_unimplemented; } break; case 14: switch (sel) { case 0: gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC)); rn = "EPC"; break; default: goto cp0_unimplemented; } break; case 15: switch (sel) { case 0: /* ignored */ rn = "PRid"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); rn = "EBase"; break; default: goto cp0_unimplemented; } break; case 16: switch (sel) { case 0: gen_helper_mtc0_config0(cpu_env, arg); rn = "Config"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; case 1: /* ignored, read only */ rn = "Config1"; break; case 2: gen_helper_mtc0_config2(cpu_env, arg); rn = "Config2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; case 3: gen_helper_mtc0_config3(cpu_env, arg); rn = "Config3"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; case 4: gen_helper_mtc0_config4(cpu_env, arg); rn = "Config4"; ctx->bstate = BS_STOP; break; case 5: gen_helper_mtc0_config5(cpu_env, arg); rn = "Config5"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; /* 6,7 are implementation dependent */ case 6: /* ignored */ rn = "Config6"; break; case 7: /* ignored */ rn = "Config7"; break; default: rn = "Invalid config selector"; goto cp0_unimplemented; } break; case 17: switch (sel) { case 0: gen_helper_mtc0_lladdr(cpu_env, arg); rn = "LLAddr"; break; default: goto cp0_unimplemented; } break; case 18: switch (sel) { case 0 ... 7: gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; default: goto cp0_unimplemented; } break; case 19: switch (sel) { case 0 ... 7: gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; default: goto cp0_unimplemented; } break; case 20: switch (sel) { case 0: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); rn = "XContext"; break; #endif default: goto cp0_unimplemented; } break; case 21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); rn = "Framemask"; break; default: goto cp0_unimplemented; } break; case 22: /* ignored */ rn = "Diagnostic"; /* implementation dependent */ break; case 23: switch (sel) { case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */ rn = "TraceControl"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 2: // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */ rn = "TraceControl2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 3: /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */ rn = "UserTraceData"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 4: // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceBPC"; // break; default: goto cp0_unimplemented; } break; case 24: switch (sel) { case 0: /* EJTAG support */ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC)); rn = "DEPC"; break; default: goto cp0_unimplemented; } break; case 25: switch (sel) { case 0: gen_helper_mtc0_performance0(cpu_env, arg); rn = "Performance0"; break; case 1: // gen_helper_mtc0_performance1(arg); rn = "Performance1"; // break; case 2: // gen_helper_mtc0_performance2(arg); rn = "Performance2"; // break; case 3: // gen_helper_mtc0_performance3(arg); rn = "Performance3"; // break; case 4: // gen_helper_mtc0_performance4(arg); rn = "Performance4"; // break; case 5: // gen_helper_mtc0_performance5(arg); rn = "Performance5"; // break; case 6: // gen_helper_mtc0_performance6(arg); rn = "Performance6"; // break; case 7: // gen_helper_mtc0_performance7(arg); rn = "Performance7"; // break; default: goto cp0_unimplemented; } break; case 26: /* ignored */ rn = "ECC"; break; case 27: switch (sel) { case 0 ... 3: /* ignored */ rn = "CacheErr"; break; default: goto cp0_unimplemented; } break; case 28: switch (sel) { case 0: case 2: case 4: case 6: gen_helper_mtc0_taglo(cpu_env, arg); rn = "TagLo"; break; case 1: case 3: case 5: case 7: gen_helper_mtc0_datalo(cpu_env, arg); rn = "DataLo"; break; default: goto cp0_unimplemented; } break; case 29: switch (sel) { case 0: case 2: case 4: case 6: gen_helper_mtc0_taghi(cpu_env, arg); rn = "TagHi"; break; case 1: case 3: case 5: case 7: gen_helper_mtc0_datahi(cpu_env, arg); rn = "DataHi"; break; default: rn = "invalid sel"; goto cp0_unimplemented; } break; case 30: switch (sel) { case 0: gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC)); rn = "ErrorEPC"; break; default: goto cp0_unimplemented; } break; case 31: switch (sel) { case 0: /* EJTAG support */ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; case 2 ... 7: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); rn = "KScratch"; break; default: goto cp0_unimplemented; } /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; default: goto cp0_unimplemented; } (void)rn; /* avoid a compiler warning */ LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ if (use_icount) { gen_io_end(); ctx->bstate = BS_STOP; } return; cp0_unimplemented: LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); }


void module_call_init(module_init_type type) { ModuleTypeList *l; ModuleEntry *e; l = find_type(type); TAILQ_FOREACH(e, l, node) { e->init(); } }


static void qmp_output_free(Visitor *v) { QmpOutputVisitor *qov = to_qov(v); QStackEntry *e; while (!QSLIST_EMPTY(&qov->stack)) { e = QSLIST_FIRST(&qov->stack); QSLIST_REMOVE_HEAD(&qov->stack, node); g_free(e); } qobject_decref(qov->root); g_free(qov); }


static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) { CPUX86State *env = &cpu->env; x86_def_t def1, *def = &def1; memset(def, 0, sizeof(*def)); if (cpu_x86_find_by_name(cpu, def, name) < 0) { error_setg(errp, "Unable to find CPU definition: %s", name); return; } object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp); object_property_set_int(OBJECT(cpu), def->level, "level", errp); object_property_set_int(OBJECT(cpu), def->family, "family", errp); object_property_set_int(OBJECT(cpu), def->model, "model", errp); object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp); env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX]; env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX]; env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX]; env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX]; object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp); env->features[FEAT_KVM] = def->features[FEAT_KVM]; env->features[FEAT_SVM] = def->features[FEAT_SVM]; env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX]; env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX]; env->cpuid_xlevel2 = def->xlevel2; cpu->cache_info_passthrough = def->cache_info_passthrough; object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); /* Special cases not set in the x86_def_t structs: */ if (kvm_enabled()) { env->features[FEAT_KVM] |= kvm_default_features; } env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; }


static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "cadence_gem"); dev = qdev_create(NULL, "cadence_gem"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }


static void monitor_json_emitter(Monitor *mon, const QObject *data) { QString *json; json = qobject_to_json(data); assert(json != NULL); mon->mc->print_enabled = 1; monitor_printf(mon, "%s\n", qstring_get_str(json)); mon->mc->print_enabled = 0; QDECREF(json); }


void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) { int i; X86CPU *cpu = NULL; Error *error = NULL; unsigned long apic_id_limit; /* init CPUs */ if (cpu_model == NULL) { #ifdef TARGET_X86_64 cpu_model = "qemu64"; #else cpu_model = "qemu32"; #endif } current_cpu_model = cpu_model; apic_id_limit = pc_apic_id_limit(max_cpus); if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { error_report("max_cpus is too large. APIC ID of last CPU is %lu", apic_id_limit - 1); exit(1); } for (i = 0; i < smp_cpus; i++) { cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), icc_bridge, &error); if (error) { error_report_err(error); exit(1); } object_unref(OBJECT(cpu)); } /* tell smbios about cpuid version and features */ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); }


static void cpu_exit_tb_from_sighandler(CPUState *cpu, void *puc) { #ifdef __linux__ struct ucontext *uc = puc; #elif defined(__OpenBSD__) struct sigcontext *uc = puc; #endif /* XXX: use siglongjmp ? */ #ifdef __linux__ #ifdef __ia64 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL); #else sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); #endif #elif defined(__OpenBSD__) sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); #endif cpu_resume_from_signal(cpu, NULL); }


static int ioreq_runio_qemu_aio(struct ioreq *ioreq) { struct XenBlkDev *blkdev = ioreq->blkdev; if (ioreq->req.nr_segments && ioreq_map(ioreq) == -1) { goto err_no_map; } ioreq->aio_inflight++; if (ioreq->presync) { bdrv_aio_flush(ioreq->blkdev->bs, qemu_aio_complete, ioreq); return 0; } switch (ioreq->req.operation) { case BLKIF_OP_READ: block_acct_start(bdrv_get_stats(blkdev->bs), &ioreq->acct, ioreq->v.size, BLOCK_ACCT_READ); ioreq->aio_inflight++; bdrv_aio_readv(blkdev->bs, ioreq->start / BLOCK_SIZE, &ioreq->v, ioreq->v.size / BLOCK_SIZE, qemu_aio_complete, ioreq); break; case BLKIF_OP_WRITE: case BLKIF_OP_FLUSH_DISKCACHE: if (!ioreq->req.nr_segments) { break; } block_acct_start(bdrv_get_stats(blkdev->bs), &ioreq->acct, ioreq->v.size, BLOCK_ACCT_WRITE); ioreq->aio_inflight++; bdrv_aio_writev(blkdev->bs, ioreq->start / BLOCK_SIZE, &ioreq->v, ioreq->v.size / BLOCK_SIZE, qemu_aio_complete, ioreq); break; case BLKIF_OP_DISCARD: { struct blkif_request_discard *discard_req = (void *)&ioreq->req; ioreq->aio_inflight++; bdrv_aio_discard(blkdev->bs, discard_req->sector_number, discard_req->nr_sectors, qemu_aio_complete, ioreq); break; } default: /* unknown operation (shouldn't happen -- parse catches this) */ goto err; } qemu_aio_complete(ioreq, 0); return 0; err: ioreq_unmap(ioreq); err_no_map: ioreq_finish(ioreq); ioreq->status = BLKIF_RSP_ERROR; return -1; }


static int decode_subframe_lpc(ShortenContext *s, int command, int channel, int residual_size, int32_t coffset) { int pred_order, sum, qshift, init_sum, i, j; const int *coeffs; if (command == FN_QLPC) { /* read/validate prediction order */ pred_order = get_ur_golomb_shorten(&s->gb, LPCQSIZE); if (pred_order > s->nwrap) { av_log(s->avctx, AV_LOG_ERROR, "invalid pred_order %d\n", pred_order); return AVERROR(EINVAL); } /* read LPC coefficients */ for (i = 0; i < pred_order; i++) s->coeffs[i] = get_sr_golomb_shorten(&s->gb, LPCQUANT); coeffs = s->coeffs; qshift = LPCQUANT; } else { /* fixed LPC coeffs */ pred_order = command; if (pred_order >= FF_ARRAY_ELEMS(fixed_coeffs)) { av_log(s->avctx, AV_LOG_ERROR, "invalid pred_order %d\n", pred_order); return AVERROR_INVALIDDATA; } coeffs = fixed_coeffs[pred_order]; qshift = 0; } /* subtract offset from previous samples to use in prediction */ if (command == FN_QLPC && coffset) for (i = -pred_order; i < 0; i++) s->decoded[channel][i] -= coffset; /* decode residual and do LPC prediction */ init_sum = pred_order ? (command == FN_QLPC ? s->lpcqoffset : 0) : coffset; for (i = 0; i < s->blocksize; i++) { sum = init_sum; for (j = 0; j < pred_order; j++) sum += coeffs[j] * s->decoded[channel][i - j - 1]; s->decoded[channel][i] = get_sr_golomb_shorten(&s->gb, residual_size) + (sum >> qshift); } /* add offset to current samples */ if (command == FN_QLPC && coffset) for (i = 0; i < s->blocksize; i++) s->decoded[channel][i] += coffset; return 0; }


static int coroutine_fn blkreplay_co_pwritev(BlockDriverState *bs, uint64_t offset, uint64_t bytes, QEMUIOVector *qiov, int flags) { uint64_t reqid = request_id++; int ret = bdrv_co_pwritev(bs->file->bs, offset, bytes, qiov, flags); block_request_create(reqid, bs, qemu_coroutine_self()); qemu_coroutine_yield(); return ret; }


static void hmp_handle_error(Monitor *mon, Error **errp) { if (error_is_set(errp)) { monitor_printf(mon, "%s\n", error_get_pretty(*errp)); error_free(*errp); } }


void mips_r4k_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { char *filename; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); int bios_size; CPUState *env; ResetData *reset_info; int i; qemu_irq *i8259; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *dinfo; int be; /* init CPUs */ if (cpu_model == NULL) { #ifdef TARGET_MIPS64 cpu_model = "R4000"; #else cpu_model = "24Kf"; #endif } env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } reset_info = g_malloc0(sizeof(ResetData)); reset_info->env = env; reset_info->vector = env->active_tc.PC; qemu_register_reset(main_cpu_reset, reset_info); /* allocate RAM */ if (ram_size > (256 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } memory_region_init_ram(ram, NULL, "mips_r4k.ram", ram_size); memory_region_add_subregion(address_space_mem, 0, ram); memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000); memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem); /* Try to load a BIOS image. If this fails, we continue regardless, but initialize the hardware ourselves. When a kernel gets preloaded we also initialize the hardware, since the BIOS wasn't run. */ if (bios_name == NULL) bios_name = BIOS_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { bios_size = get_image_size(filename); } else { bios_size = -1; } #ifdef TARGET_WORDS_BIGENDIAN be = 1; #else be = 0; #endif if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { bios = g_new(MemoryRegion, 1); memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { uint32_t mips_rom = 0x00400000; if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom, dinfo->bdrv, sector_len, mips_rom / sector_len, 4, 0, 0, 0, 0, be)) { fprintf(stderr, "qemu: Error registering flash memory.\n"); } } else { /* not fatal */ fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", bios_name); } if (filename) { g_free(filename); } if (kernel_filename) { loaderparams.ram_size = ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; reset_info->vector = load_kernel(); } /* Init CPU internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); /* The PIC is attached to the MIPS CPU INT0 pin */ i8259 = i8259_init(env->irq[2]); isa_bus_new(NULL, get_system_io()); isa_bus_irqs(i8259); rtc_init(2000, NULL); /* Register 64 KB of ISA IO space at 0x14000000 */ isa_mmio_init(0x14000000, 0x00010000); isa_mem_base = 0x10000000; pit = pit_init(0x40, 0); for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { serial_isa_init(i, serial_hds[i]); } } isa_vga_init(); if (nd_table[0].vlan) isa_ne2000_init(0x300, 9, &nd_table[0]); ide_drive_get(hd, MAX_IDE_BUS); for(i = 0; i < MAX_IDE_BUS; i++) isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); isa_create_simple("i8042"); }


static int dmg_open(BlockDriverState *bs, QDict *options, int flags, Error **errp) { BDRVDMGState *s = bs->opaque; DmgHeaderState ds; uint64_t rsrc_fork_offset, rsrc_fork_length; uint64_t plist_xml_offset, plist_xml_length; int64_t offset; int ret; bs->file = bdrv_open_child(NULL, options, "file", bs, &child_file, false, errp); if (!bs->file) { return -EINVAL; } block_module_load_one("dmg-bz2"); bs->read_only = true; s->n_chunks = 0; s->offsets = s->lengths = s->sectors = s->sectorcounts = NULL; /* used by dmg_read_mish_block to keep track of the current I/O position */ ds.data_fork_offset = 0; ds.max_compressed_size = 1; ds.max_sectors_per_chunk = 1; /* locate the UDIF trailer */ offset = dmg_find_koly_offset(bs->file, errp); if (offset < 0) { ret = offset; goto fail; } /* offset of data fork (DataForkOffset) */ ret = read_uint64(bs, offset + 0x18, &ds.data_fork_offset); if (ret < 0) { goto fail; } else if (ds.data_fork_offset > offset) { ret = -EINVAL; goto fail; } /* offset of resource fork (RsrcForkOffset) */ ret = read_uint64(bs, offset + 0x28, &rsrc_fork_offset); if (ret < 0) { goto fail; } ret = read_uint64(bs, offset + 0x30, &rsrc_fork_length); if (ret < 0) { goto fail; } if (rsrc_fork_offset >= offset || rsrc_fork_length > offset - rsrc_fork_offset) { ret = -EINVAL; goto fail; } /* offset of property list (XMLOffset) */ ret = read_uint64(bs, offset + 0xd8, &plist_xml_offset); if (ret < 0) { goto fail; } ret = read_uint64(bs, offset + 0xe0, &plist_xml_length); if (ret < 0) { goto fail; } if (plist_xml_offset >= offset || plist_xml_length > offset - plist_xml_offset) { ret = -EINVAL; goto fail; } ret = read_uint64(bs, offset + 0x1ec, (uint64_t *)&bs->total_sectors); if (ret < 0) { goto fail; } if (bs->total_sectors < 0) { ret = -EINVAL; goto fail; } if (rsrc_fork_length != 0) { ret = dmg_read_resource_fork(bs, &ds, rsrc_fork_offset, rsrc_fork_length); if (ret < 0) { goto fail; } } else if (plist_xml_length != 0) { ret = dmg_read_plist_xml(bs, &ds, plist_xml_offset, plist_xml_length); if (ret < 0) { goto fail; } } else { ret = -EINVAL; goto fail; } /* initialize zlib engine */ s->compressed_chunk = qemu_try_blockalign(bs->file->bs, ds.max_compressed_size + 1); s->uncompressed_chunk = qemu_try_blockalign(bs->file->bs, 512 * ds.max_sectors_per_chunk); if (s->compressed_chunk == NULL || s->uncompressed_chunk == NULL) { ret = -ENOMEM; goto fail; } if (inflateInit(&s->zstream) != Z_OK) { ret = -EINVAL; goto fail; } s->current_chunk = s->n_chunks; qemu_co_mutex_init(&s->lock); return 0; fail: g_free(s->types); g_free(s->offsets); g_free(s->lengths); g_free(s->sectors); g_free(s->sectorcounts); qemu_vfree(s->compressed_chunk); qemu_vfree(s->uncompressed_chunk); return ret; }


void bdrv_detach_aio_context(BlockDriverState *bs) { BdrvAioNotifier *baf; if (!bs->drv) { return; } QLIST_FOREACH(baf, &bs->aio_notifiers, list) { baf->detach_aio_context(baf->opaque); } if (bs->io_limits_enabled) { throttle_timers_detach_aio_context(&bs->throttle_timers); } if (bs->drv->bdrv_detach_aio_context) { bs->drv->bdrv_detach_aio_context(bs); } if (bs->file) { bdrv_detach_aio_context(bs->file->bs); } if (bs->backing) { bdrv_detach_aio_context(bs->backing->bs); } bs->aio_context = NULL; }


static int virtio_rng_load(QEMUFile *f, void *opaque, int version_id) { VirtIORNG *vrng = opaque; VirtIODevice *vdev = VIRTIO_DEVICE(vrng); if (version_id != 1) { return -EINVAL; } virtio_load(vdev, f, version_id); /* We may have an element ready but couldn't process it due to a quota * limit. Make sure to try again after live migration when the quota may * have been reset. */ virtio_rng_process(vrng); return 0; }


static av_cold int roq_dpcm_encode_init(AVCodecContext *avctx) { ROQDPCMContext *context = avctx->priv_data; if (avctx->channels > 2) { av_log(avctx, AV_LOG_ERROR, "Audio must be mono or stereo\n"); return -1; } if (avctx->sample_rate != 22050) { av_log(avctx, AV_LOG_ERROR, "Audio must be 22050 Hz\n"); return -1; } if (avctx->sample_fmt != AV_SAMPLE_FMT_S16) { av_log(avctx, AV_LOG_ERROR, "Audio must be signed 16-bit\n"); return -1; } avctx->frame_size = ROQ_FIRST_FRAME_SIZE; context->lastSample[0] = context->lastSample[1] = 0; avctx->coded_frame= avcodec_alloc_frame(); if (!avctx->coded_frame) return AVERROR(ENOMEM); return 0; }


static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr) { struct kvm_x86_mce mce = { .bank = 9, .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | MCI_STATUS_AR | 0x134, .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, .addr = paddr, .misc = (MCM_ADDR_PHYS << 6) | 0xc, }; int r; r = kvm_set_mce(env, &mce); if (r < 0) { fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); abort(); } kvm_mce_broadcast_rest(env); }


int qemu_global_option(const char *str) { char driver[64], property[64]; QemuOpts *opts; int rc, offset; rc = sscanf(str, "%63[^.].%63[^=]%n", driver, property, &offset); if (rc < 2 || str[offset] != '=') { error_report("can't parse: \"%s\"", str); return -1; } opts = qemu_opts_create(&qemu_global_opts, NULL, 0, &error_abort); qemu_opt_set(opts, "driver", driver, &error_abort); qemu_opt_set(opts, "property", property, &error_abort); qemu_opt_set(opts, "value", str + offset + 1, &error_abort); return 0; }


static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { UHCIState *s = opaque; addr &= 0x1f; DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val); switch(addr) { case 0x00: if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { /* start frame processing */ s->expire_time = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / FRAME_TIMER_FREQ); qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); s->status &= ~UHCI_STS_HCHALTED; } else if (!(val & UHCI_CMD_RS)) { s->status |= UHCI_STS_HCHALTED; } if (val & UHCI_CMD_GRESET) { UHCIPort *port; USBDevice *dev; int i; /* send reset on the USB bus */ for(i = 0; i < NB_PORTS; i++) { port = &s->ports[i]; dev = port->port.dev; if (dev) { usb_send_msg(dev, USB_MSG_RESET); } } uhci_reset(s); return; } if (val & UHCI_CMD_HCRESET) { uhci_reset(s); return; } s->cmd = val; break; case 0x02: s->status &= ~val; /* XXX: the chip spec is not coherent, so we add a hidden register to distinguish between IOC and SPD */ if (val & UHCI_STS_USBINT) s->status2 = 0; uhci_update_irq(s); break; case 0x04: s->intr = val; uhci_update_irq(s); break; case 0x06: if (s->status & UHCI_STS_HCHALTED) s->frnum = val & 0x7ff; break; case 0x10 ... 0x1f: { UHCIPort *port; USBDevice *dev; int n; n = (addr >> 1) & 7; if (n >= NB_PORTS) return; port = &s->ports[n]; dev = port->port.dev; if (dev) { /* port reset */ if ( (val & UHCI_PORT_RESET) && !(port->ctrl & UHCI_PORT_RESET) ) { usb_send_msg(dev, USB_MSG_RESET); } } port->ctrl &= UHCI_PORT_READ_ONLY; port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); /* some bits are reset when a '1' is written to them */ port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); } break; } }


static void tlb_info_pae32(Monitor *mon, CPUState *env) { int l1, l2, l3; uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; pdp_addr = env->cr[3] & ~0x1f; for (l1 = 0; l1 < 4; l1++) { cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8); pde = le64_to_cpu(pde); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { /* 2M pages with PAE, CR4.PSE is ignored */ print_pte(mon, (l1 << 30 ) + (l2 << 21), pde, ~((target_phys_addr_t)(1 << 20) - 1)); } else { pt_addr = pde & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8); pte = le64_to_cpu(pte); if (pte & PG_PRESENT_MASK) { print_pte(mon, (l1 << 30 ) + (l2 << 21) + (l3 << 12), pte & ~PG_PSE_MASK, ~(target_phys_addr_t)0xfff); } } } } } } } }


void *paio_init(void) { struct sigaction act; PosixAioState *s; int fds[2]; int ret; if (posix_aio_state) return posix_aio_state; s = qemu_malloc(sizeof(PosixAioState)); sigfillset(&act.sa_mask); act.sa_flags = 0; /* do not restart syscalls to interrupt select() */ act.sa_handler = aio_signal_handler; sigaction(SIGUSR2, &act, NULL); s->first_aio = NULL; if (pipe(fds) == -1) { fprintf(stderr, "failed to create pipe\n"); return NULL; } s->rfd = fds[0]; s->wfd = fds[1]; fcntl(s->rfd, F_SETFL, O_NONBLOCK); fcntl(s->wfd, F_SETFL, O_NONBLOCK); qemu_aio_set_fd_handler(s->rfd, posix_aio_read, NULL, posix_aio_flush, s); ret = pthread_attr_init(&attr); if (ret) die2(ret, "pthread_attr_init"); ret = pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); if (ret) die2(ret, "pthread_attr_setdetachstate"); TAILQ_INIT(&request_list); posix_aio_state = s; return posix_aio_state; }


static void close_slaves(AVFormatContext *avf) { TeeContext *tee = avf->priv_data; AVFormatContext *avf2; unsigned i, j; for (i = 0; i < tee->nb_slaves; i++) { avf2 = tee->slaves[i].avf; for (j = 0; j < avf2->nb_streams; j++) { AVBitStreamFilterContext *bsf_next, *bsf = tee->slaves[i].bsfs[j]; while (bsf) { bsf_next = bsf->next; av_bitstream_filter_close(bsf); bsf = bsf_next; } } av_freep(&tee->slaves[i].stream_map); avio_close(avf2->pb); avf2->pb = NULL; avformat_free_context(avf2); tee->slaves[i].avf = NULL; } }


static int update_context_from_thread(AVCodecContext *dst, AVCodecContext *src, int for_user) { int err = 0; if (dst != src) { dst->sub_id = src->sub_id; dst->time_base = src->time_base; dst->width = src->width; dst->height = src->height; dst->pix_fmt = src->pix_fmt; dst->coded_width = src->coded_width; dst->coded_height = src->coded_height; dst->has_b_frames = src->has_b_frames; dst->idct_algo = src->idct_algo; dst->slice_count = src->slice_count; dst->bits_per_coded_sample = src->bits_per_coded_sample; dst->sample_aspect_ratio = src->sample_aspect_ratio; dst->dtg_active_format = src->dtg_active_format; dst->profile = src->profile; dst->level = src->level; dst->bits_per_raw_sample = src->bits_per_raw_sample; dst->ticks_per_frame = src->ticks_per_frame; dst->color_primaries = src->color_primaries; dst->color_trc = src->color_trc; dst->colorspace = src->colorspace; dst->color_range = src->color_range; dst->chroma_sample_location = src->chroma_sample_location; } if (for_user) { dst->coded_frame = src->coded_frame; dst->has_b_frames += src->thread_count - 1; } else { if (dst->codec->update_thread_context) err = dst->codec->update_thread_context(dst, src); } return err; }


static int v4l2_set_parameters(AVFormatContext *s1) { struct video_data *s = s1->priv_data; struct v4l2_standard standard = { 0 }; struct v4l2_streamparm streamparm = { 0 }; struct v4l2_fract *tpf; AVRational framerate_q = { 0 }; int i, ret; if (s->framerate && (ret = av_parse_video_rate(&framerate_q, s->framerate)) < 0) { av_log(s1, AV_LOG_ERROR, "Could not parse framerate '%s'.\n", s->framerate); return ret; } if (s->standard) { if (s->std_id) { ret = 0; av_log(s1, AV_LOG_DEBUG, "Setting standard: %s\n", s->standard); /* set tv standard */ for (i = 0; ; i++) { standard.index = i; if (v4l2_ioctl(s->fd, VIDIOC_ENUMSTD, &standard) < 0) { ret = AVERROR(errno); break; } if (!av_strcasecmp(standard.name, s->standard)) break; } if (ret < 0) { av_log(s1, AV_LOG_ERROR, "Unknown or unsupported standard '%s'\n", s->standard); return ret; } if (v4l2_ioctl(s->fd, VIDIOC_S_STD, &standard.id) < 0) { ret = AVERROR(errno); av_log(s1, AV_LOG_ERROR, "ioctl(VIDIOC_S_STD): %s\n", av_err2str(ret)); return ret; } } else { av_log(s1, AV_LOG_WARNING, "This device does not support any standard\n"); } } /* get standard */ if (v4l2_ioctl(s->fd, VIDIOC_G_STD, &s->std_id) == 0) { tpf = &standard.frameperiod; for (i = 0; ; i++) { standard.index = i; if (v4l2_ioctl(s->fd, VIDIOC_ENUMSTD, &standard) < 0) { ret = AVERROR(errno); if (ret == AVERROR(EINVAL)) { tpf = &streamparm.parm.capture.timeperframe; break; } av_log(s1, AV_LOG_ERROR, "ioctl(VIDIOC_ENUMSTD): %s\n", av_err2str(ret)); return ret; } if (standard.id == s->std_id) { av_log(s1, AV_LOG_DEBUG, "Current standard: %s, id: %"PRIx64", frameperiod: %d/%d\n", standard.name, (uint64_t)standard.id, tpf->numerator, tpf->denominator); break; } } } else { tpf = &streamparm.parm.capture.timeperframe; } streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; if (v4l2_ioctl(s->fd, VIDIOC_G_PARM, &streamparm) < 0) { ret = AVERROR(errno); av_log(s1, AV_LOG_ERROR, "ioctl(VIDIOC_G_PARM): %s\n", av_err2str(ret)); return ret; } if (framerate_q.num && framerate_q.den) { if (streamparm.parm.capture.capability & V4L2_CAP_TIMEPERFRAME) { tpf = &streamparm.parm.capture.timeperframe; av_log(s1, AV_LOG_DEBUG, "Setting time per frame to %d/%d\n", framerate_q.den, framerate_q.num); tpf->numerator = framerate_q.den; tpf->denominator = framerate_q.num; if (v4l2_ioctl(s->fd, VIDIOC_S_PARM, &streamparm) < 0) { ret = AVERROR(errno); av_log(s1, AV_LOG_ERROR, "ioctl(VIDIOC_S_PARM): %s\n", av_err2str(ret)); return ret; } if (framerate_q.num != tpf->denominator || framerate_q.den != tpf->numerator) { av_log(s1, AV_LOG_INFO, "The driver changed the time per frame from " "%d/%d to %d/%d\n", framerate_q.den, framerate_q.num, tpf->numerator, tpf->denominator); } } else { av_log(s1, AV_LOG_WARNING, "The driver does not allow to change time per frame\n"); } } if (tpf->denominator > 0 && tpf->numerator > 0) { s1->streams[0]->avg_frame_rate.num = tpf->denominator; s1->streams[0]->avg_frame_rate.den = tpf->numerator; s1->streams[0]->r_frame_rate = s1->streams[0]->avg_frame_rate; } else av_log(s1, AV_LOG_WARNING, "Time per frame unknown\n"); return 0; }


static target_long monitor_get_tbu (const struct MonitorDef *md, int val) { CPUState *env = mon_get_cpu(); if (!env) return 0; return cpu_ppc_load_tbu(env); }


static void decorrelation(PSContext *ps, INTFLOAT (*out)[32][2], const INTFLOAT (*s)[32][2], int is34) { LOCAL_ALIGNED_16(INTFLOAT, power, [34], [PS_QMF_TIME_SLOTS]); LOCAL_ALIGNED_16(INTFLOAT, transient_gain, [34], [PS_QMF_TIME_SLOTS]); INTFLOAT *peak_decay_nrg = ps->peak_decay_nrg; INTFLOAT *power_smooth = ps->power_smooth; INTFLOAT *peak_decay_diff_smooth = ps->peak_decay_diff_smooth; INTFLOAT (*delay)[PS_QMF_TIME_SLOTS + PS_MAX_DELAY][2] = ps->delay; INTFLOAT (*ap_delay)[PS_AP_LINKS][PS_QMF_TIME_SLOTS + PS_MAX_AP_DELAY][2] = ps->ap_delay; #if !USE_FIXED const float transient_impact = 1.5f; const float a_smooth = 0.25f; ///< Smoothing coefficient #endif /* USE_FIXED */ const int8_t *k_to_i = is34 ? k_to_i_34 : k_to_i_20; int i, k, m, n; int n0 = 0, nL = 32; const INTFLOAT peak_decay_factor = Q31(0.76592833836465f); memset(power, 0, 34 * sizeof(*power)); if (is34 != ps->is34bands_old) { memset(ps->peak_decay_nrg, 0, sizeof(ps->peak_decay_nrg)); memset(ps->power_smooth, 0, sizeof(ps->power_smooth)); memset(ps->peak_decay_diff_smooth, 0, sizeof(ps->peak_decay_diff_smooth)); memset(ps->delay, 0, sizeof(ps->delay)); memset(ps->ap_delay, 0, sizeof(ps->ap_delay)); } for (k = 0; k < NR_BANDS[is34]; k++) { int i = k_to_i[k]; ps->dsp.add_squares(power[i], s[k], nL - n0); } //Transient detection #if USE_FIXED for (i = 0; i < NR_PAR_BANDS[is34]; i++) { for (n = n0; n < nL; n++) { int decayed_peak; int denom; decayed_peak = (int)(((int64_t)peak_decay_factor * \ peak_decay_nrg[i] + 0x40000000) >> 31); peak_decay_nrg[i] = FFMAX(decayed_peak, power[i][n]); power_smooth[i] += (power[i][n] - power_smooth[i] + 2) >> 2; peak_decay_diff_smooth[i] += (peak_decay_nrg[i] - power[i][n] - \ peak_decay_diff_smooth[i] + 2) >> 2; denom = peak_decay_diff_smooth[i] + (peak_decay_diff_smooth[i] >> 1); if (denom > power_smooth[i]) { int p = power_smooth[i]; while (denom < 0x40000000) { denom <<= 1; p <<= 1; } transient_gain[i][n] = p / (denom >> 16); } else { transient_gain[i][n] = 1 << 16; } } } #else for (i = 0; i < NR_PAR_BANDS[is34]; i++) { for (n = n0; n < nL; n++) { float decayed_peak = peak_decay_factor * peak_decay_nrg[i]; float denom; peak_decay_nrg[i] = FFMAX(decayed_peak, power[i][n]); power_smooth[i] += a_smooth * (power[i][n] - power_smooth[i]); peak_decay_diff_smooth[i] += a_smooth * (peak_decay_nrg[i] - power[i][n] - peak_decay_diff_smooth[i]); denom = transient_impact * peak_decay_diff_smooth[i]; transient_gain[i][n] = (denom > power_smooth[i]) ? power_smooth[i] / denom : 1.0f; } } #endif /* USE_FIXED */ //Decorrelation and transient reduction // PS_AP_LINKS - 1 // ----- // | | Q_fract_allpass[k][m]*z^-link_delay[m] - a[m]*g_decay_slope[k] //H[k][z] = z^-2 * phi_fract[k] * | | ---------------------------------------------------------------- // | | 1 - a[m]*g_decay_slope[k]*Q_fract_allpass[k][m]*z^-link_delay[m] // m = 0 //d[k][z] (out) = transient_gain_mapped[k][z] * H[k][z] * s[k][z] for (k = 0; k < NR_ALLPASS_BANDS[is34]; k++) { int b = k_to_i[k]; #if USE_FIXED int g_decay_slope; if (k - DECAY_CUTOFF[is34] <= 0) { g_decay_slope = 1 << 30; } else if (k - DECAY_CUTOFF[is34] >= 20) { g_decay_slope = 0; } else { g_decay_slope = (1 << 30) - DECAY_SLOPE * (k - DECAY_CUTOFF[is34]); } #else float g_decay_slope = 1.f - DECAY_SLOPE * (k - DECAY_CUTOFF[is34]); g_decay_slope = av_clipf(g_decay_slope, 0.f, 1.f); #endif /* USE_FIXED */ memcpy(delay[k], delay[k]+nL, PS_MAX_DELAY*sizeof(delay[k][0])); memcpy(delay[k]+PS_MAX_DELAY, s[k], numQMFSlots*sizeof(delay[k][0])); for (m = 0; m < PS_AP_LINKS; m++) { memcpy(ap_delay[k][m], ap_delay[k][m]+numQMFSlots, 5*sizeof(ap_delay[k][m][0])); } ps->dsp.decorrelate(out[k], delay[k] + PS_MAX_DELAY - 2, ap_delay[k], phi_fract[is34][k], (const INTFLOAT (*)[2]) Q_fract_allpass[is34][k], transient_gain[b], g_decay_slope, nL - n0); } for (; k < SHORT_DELAY_BAND[is34]; k++) { int i = k_to_i[k]; memcpy(delay[k], delay[k]+nL, PS_MAX_DELAY*sizeof(delay[k][0])); memcpy(delay[k]+PS_MAX_DELAY, s[k], numQMFSlots*sizeof(delay[k][0])); //H = delay 14 ps->dsp.mul_pair_single(out[k], delay[k] + PS_MAX_DELAY - 14, transient_gain[i], nL - n0); } for (; k < NR_BANDS[is34]; k++) { int i = k_to_i[k]; memcpy(delay[k], delay[k]+nL, PS_MAX_DELAY*sizeof(delay[k][0])); memcpy(delay[k]+PS_MAX_DELAY, s[k], numQMFSlots*sizeof(delay[k][0])); //H = delay 1 ps->dsp.mul_pair_single(out[k], delay[k] + PS_MAX_DELAY - 1, transient_gain[i], nL - n0); } }


void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); }


static int load_glyph(AVFilterContext *ctx, Glyph **glyph_ptr, uint32_t code) { DrawTextContext *s = ctx->priv; FT_BitmapGlyph bitmapglyph; Glyph *glyph; struct AVTreeNode *node = NULL; int ret; /* load glyph into s->face->glyph */ if (FT_Load_Char(s->face, code, s->ft_load_flags)) return AVERROR(EINVAL); /* save glyph */ if (!(glyph = av_mallocz(sizeof(*glyph))) || !(glyph->glyph = av_mallocz(sizeof(*glyph->glyph)))) { ret = AVERROR(ENOMEM); goto error; } glyph->code = code; if (FT_Get_Glyph(s->face->glyph, glyph->glyph)) { ret = AVERROR(EINVAL); goto error; } if (s->borderw) { FT_Glyph border_glyph = *glyph->glyph; if (FT_Glyph_StrokeBorder(&border_glyph, s->stroker, 0, 0) || FT_Glyph_To_Bitmap(&border_glyph, FT_RENDER_MODE_NORMAL, 0, 1)) { ret = AVERROR_EXTERNAL; goto error; } bitmapglyph = (FT_BitmapGlyph) border_glyph; glyph->border_bitmap = bitmapglyph->bitmap; } if (FT_Glyph_To_Bitmap(glyph->glyph, FT_RENDER_MODE_NORMAL, 0, 1)) { ret = AVERROR_EXTERNAL; goto error; } bitmapglyph = (FT_BitmapGlyph) *glyph->glyph; glyph->bitmap = bitmapglyph->bitmap; glyph->bitmap_left = bitmapglyph->left; glyph->bitmap_top = bitmapglyph->top; glyph->advance = s->face->glyph->advance.x >> 6; /* measure text height to calculate text_height (or the maximum text height) */ FT_Glyph_Get_CBox(*glyph->glyph, ft_glyph_bbox_pixels, &glyph->bbox); /* cache the newly created glyph */ if (!(node = av_tree_node_alloc())) { ret = AVERROR(ENOMEM); goto error; } av_tree_insert(&s->glyphs, glyph, glyph_cmp, &node); if (glyph_ptr) *glyph_ptr = glyph; return 0; error: if (glyph) av_freep(&glyph->glyph); av_freep(&glyph); av_freep(&node); return ret; }


QError *qobject_to_qerror(const QObject *obj) { if (qobject_type(obj) != QTYPE_QERROR) { return NULL; } return container_of(obj, QError, base); }


uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2) { CPU_DoubleU farg1, farg2; farg1.ll = arg1; farg2.ll = arg2; if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { /* Multiplication of zero by infinity */ farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ); } else { if (unlikely(float64_is_signaling_nan(farg1.d) || float64_is_signaling_nan(farg2.d))) { /* sNaN multiplication */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN); } farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); } return farg1.ll; }


static QObject *parse_value(JSONParserContext *ctxt, va_list *ap) { QObject *token; token = parser_context_peek_token(ctxt); if (token == NULL) { parse_error(ctxt, NULL, "premature EOI"); return NULL; } switch (token_get_type(token)) { case JSON_LCURLY: return parse_object(ctxt, ap); case JSON_LSQUARE: return parse_array(ctxt, ap); case JSON_ESCAPE: return parse_escape(ctxt, ap); case JSON_INTEGER: case JSON_FLOAT: case JSON_STRING: return parse_literal(ctxt); case JSON_KEYWORD: return parse_keyword(ctxt); default: parse_error(ctxt, token, "expecting value"); return NULL; } }


ssize_t virtio_pdu_vmarshal(V9fsPDU *pdu, size_t offset, const char *fmt, va_list ap) { V9fsState *s = pdu->s; V9fsVirtioState *v = container_of(s, V9fsVirtioState, state); VirtQueueElement *elem = &v->elems[pdu->idx]; return v9fs_iov_vmarshal(elem->in_sg, elem->in_num, offset, 1, fmt, ap); }


static void curl_multi_check_completion(BDRVCURLState *s) { int msgs_in_queue; /* Try to find done transfers, so we can free the easy * handle again. */ do { CURLMsg *msg; msg = curl_multi_info_read(s->multi, &msgs_in_queue); if (!msg) break; if (msg->msg == CURLMSG_NONE) break; switch (msg->msg) { case CURLMSG_DONE: { CURLState *state = NULL; curl_easy_getinfo(msg->easy_handle, CURLINFO_PRIVATE, (char **)&state); /* ACBs for successful messages get completed in curl_read_cb */ if (msg->data.result != CURLE_OK) { int i; for (i = 0; i < CURL_NUM_ACB; i++) { CURLAIOCB *acb = state->acb[i]; if (acb == NULL) { continue; } acb->common.cb(acb->common.opaque, -EIO); qemu_aio_release(acb); state->acb[i] = NULL; } } curl_clean_state(state); break; } default: msgs_in_queue = 0; break; } } while(msgs_in_queue); }