static int ppce500_load_device_tree(CPUPPCState *env, QEMUMachineInitArgs *args, PPCE500Params *params, hwaddr addr, hwaddr initrd_base, hwaddr initrd_size) { int ret = -1; uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) }; int fdt_size; void *fdt; uint8_t hypercall[16]; uint32_t clock_freq = 400000000; uint32_t tb_freq = 400000000; int i; char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; char soc[128]; char mpic[128]; uint32_t mpic_ph; uint32_t msi_ph; char gutil[128]; char pci[128]; char msi[128]; uint32_t *pci_map = NULL; int len; uint32_t pci_ranges[14] = { 0x2000000, 0x0, 0xc0000000, 0x0, 0xc0000000, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, 0x0, 0xe1000000, 0x0, 0x10000, }; QemuOpts *machine_opts = qemu_get_machine_opts(); const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); if (dtb_file) { char *filename; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); if (!filename) { goto out; } fdt = load_device_tree(filename, &fdt_size); if (!fdt) { goto out; } goto done; } fdt = create_device_tree(&fdt_size); if (fdt == NULL) { goto out; } /* Manipulate device tree in memory. */ qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); qemu_devtree_add_subnode(fdt, "/memory"); qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, sizeof(mem_reg_property)); qemu_devtree_add_subnode(fdt, "/chosen"); if (initrd_size) { ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); } ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", (initrd_base + initrd_size)); if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); } } ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", args->kernel_cmdline); if (ret < 0) fprintf(stderr, "couldn't set /chosen/bootargs\n"); if (kvm_enabled()) { /* Read out host's frequencies */ clock_freq = kvmppc_get_clockfreq(); tb_freq = kvmppc_get_tbfreq(); /* indicate KVM hypercall interface */ qemu_devtree_add_subnode(fdt, "/hypervisor"); qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", "linux,kvm"); kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", hypercall, sizeof(hypercall)); /* if KVM supports the idle hcall, set property indicating this */ if (kvmppc_get_hasidle(env)) { qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); } } /* Create CPU nodes */ qemu_devtree_add_subnode(fdt, "/cpus"); qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); /* We need to generate the cpu nodes in reverse order, so Linux can pick the first node as boot node and be happy */ for (i = smp_cpus - 1; i >= 0; i--) { CPUState *cpu; char cpu_name[128]; uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); cpu = qemu_get_cpu(i); if (cpu == NULL) { continue; } env = cpu->env_ptr; snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", cpu->cpu_index); qemu_devtree_add_subnode(fdt, cpu_name); qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index); qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", env->dcache_line_size); qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", env->icache_line_size); qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); if (cpu->cpu_index) { qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", cpu_release_addr); } else { qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); } } qemu_devtree_add_subnode(fdt, "/aliases"); /* XXX These should go into their respective devices' code */ snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(fdt, soc); qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, sizeof(compatible_sb)); qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, MPC8544_CCSRBAR_SIZE); /* XXX should contain a reasonable value */ qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); qemu_devtree_add_subnode(fdt, mpic); qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 0x40000); qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); mpic_ph = qemu_devtree_alloc_phandle(fdt); qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); /* * We have to generate ser1 first, because Linux takes the first * device it finds in the dt as serial output device. And we generate * devices in reverse order to the dt. */ dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, soc, mpic, "serial1", 1, false); dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, soc, mpic, "serial0", 0, true); snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, MPC8544_UTIL_OFFSET); qemu_devtree_add_subnode(fdt, gutil); qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); qemu_devtree_add_subnode(fdt, msi); qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); msi_ph = qemu_devtree_alloc_phandle(fdt); qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); qemu_devtree_setprop_cells(fdt, msi, "interrupts", 0xe0, 0x0, 0xe1, 0x0, 0xe2, 0x0, 0xe3, 0x0, 0xe4, 0x0, 0xe5, 0x0, 0xe6, 0x0, 0xe7, 0x0); qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); qemu_devtree_add_subnode(fdt, pci); qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 0x0, 0x7); pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), params->pci_first_slot, params->pci_nr_slots, &len); qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); for (i = 0; i < 14; i++) { pci_ranges[i] = cpu_to_be32(pci_ranges[i]); } qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, MPC8544_PCI_REGS_BASE, 0, 0x1000); qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); params->fixup_devtree(params, fdt); if (toplevel_compat) { qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, strlen(toplevel_compat) + 1); } done: qemu_devtree_dumpdtb(fdt, fdt_size); ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); if (ret < 0) { goto out; } g_free(fdt); ret = fdt_size; out: g_free(pci_map); return ret; }


static void acpi_get_pci_holes(Range *hole, Range *hole64) { Object *pci_host; pci_host = acpi_get_i386_pci_host(); g_assert(pci_host); hole->begin = object_property_get_int(pci_host, PCI_HOST_PROP_PCI_HOLE_START, NULL); hole->end = object_property_get_int(pci_host, PCI_HOST_PROP_PCI_HOLE_END, NULL); hole64->begin = object_property_get_int(pci_host, PCI_HOST_PROP_PCI_HOLE64_START, NULL); hole64->end = object_property_get_int(pci_host, PCI_HOST_PROP_PCI_HOLE64_END, NULL); }


static void colo_compare_complete(UserCreatable *uc, Error **errp) { CompareState *s = COLO_COMPARE(uc); Chardev *chr; char thread_name[64]; static int compare_id; if (!s->pri_indev || !s->sec_indev || !s->outdev) { error_setg(errp, "colo compare needs 'primary_in' ," "'secondary_in','outdev' property set"); return; } else if (!strcmp(s->pri_indev, s->outdev) || !strcmp(s->sec_indev, s->outdev) || !strcmp(s->pri_indev, s->sec_indev)) { error_setg(errp, "'indev' and 'outdev' could not be same " "for compare module"); return; } if (find_and_check_chardev(&chr, s->pri_indev, errp) || !qemu_chr_fe_init(&s->chr_pri_in, chr, errp)) { return; } if (find_and_check_chardev(&chr, s->sec_indev, errp) || !qemu_chr_fe_init(&s->chr_sec_in, chr, errp)) { return; } if (find_and_check_chardev(&chr, s->outdev, errp) || !qemu_chr_fe_init(&s->chr_out, chr, errp)) { return; } net_socket_rs_init(&s->pri_rs, compare_pri_rs_finalize, s->vnet_hdr); net_socket_rs_init(&s->sec_rs, compare_sec_rs_finalize, s->vnet_hdr); g_queue_init(&s->conn_list); s->connection_track_table = g_hash_table_new_full(connection_key_hash, connection_key_equal, g_free, connection_destroy); sprintf(thread_name, "colo-compare %d", compare_id); qemu_thread_create(&s->thread, thread_name, colo_compare_thread, s, QEMU_THREAD_JOINABLE); compare_id++; return; }


ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, MemoryRegion *mr) { RAMBlock *new_block; size = TARGET_PAGE_ALIGN(size); new_block = g_malloc0(sizeof(*new_block)); new_block->mr = mr; new_block->offset = find_ram_offset(size); if (host) { new_block->host = host; new_block->flags |= RAM_PREALLOC_MASK; } else { if (mem_path) { #if defined (__linux__) && !defined(TARGET_S390X) new_block->host = file_ram_alloc(new_block, size, mem_path); if (!new_block->host) { new_block->host = qemu_vmalloc(size); qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); } #else fprintf(stderr, "-mem-path option unsupported\n"); exit(1); #endif } else { #if defined(TARGET_S390X) && defined(CONFIG_KVM) /* S390 KVM requires the topmost vma of the RAM to be smaller than an system defined value, which is at least 256GB. Larger systems have larger values. We put the guest between the end of data segment (system break) and this value. We use 32GB as a base to have enough room for the system break to grow. */ new_block->host = mmap((void*)0x800000000, size, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0); if (new_block->host == MAP_FAILED) { fprintf(stderr, "Allocating RAM failed\n"); abort(); } #else if (xen_enabled()) { xen_ram_alloc(new_block->offset, size, mr); } else { new_block->host = qemu_vmalloc(size); } #endif qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); } } new_block->length = size; QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, last_ram_offset() >> TARGET_PAGE_BITS); cpu_physical_memory_set_dirty_range(new_block->offset, size, 0xff); if (kvm_enabled()) kvm_setup_guest_memory(new_block->host, size); return new_block->offset; }


static void x86_iommu_realize(DeviceState *dev, Error **errp) { X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev); MachineState *ms = MACHINE(qdev_get_machine()); MachineClass *mc = MACHINE_GET_CLASS(ms); PCMachineState *pcms = PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)); QLIST_INIT(&x86_iommu->iec_notifiers); if (!pcms) { error_setg(errp, "Machine-type '%s' not supported by IOMMU", mc->name); return; } if (x86_class->realize) { x86_class->realize(dev, errp); } x86_iommu_set_default(X86_IOMMU_DEVICE(dev)); }


static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size) { CSState *s = opaque; uint32_t saddr, iaddr, ret; saddr = addr; iaddr = ~0U; switch (saddr) { case Index_Address: ret = s->regs[saddr] & ~0x80; break; case Index_Data: if (!(s->dregs[MODE_And_ID] & MODE2)) iaddr = s->regs[Index_Address] & 0x0f; else iaddr = s->regs[Index_Address] & 0x1f; ret = s->dregs[iaddr]; if (iaddr == Error_Status_And_Initialization) { /* keep SEAL happy */ if (s->aci_counter) { ret |= 1 << 5; s->aci_counter -= 1; } } break; default: ret = s->regs[saddr]; break; } dolog ("read %d:%d -> %d\n", saddr, iaddr, ret); return ret; }


static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr, uint64_t asc, uint64_t entry, int level, target_ulong *raddr, int *flags, int rw) { CPUState *cs = CPU(s390_env_get_cpu(env)); uint64_t origin, offs, new_entry; const int pchks[4] = { PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS }; PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry); origin = entry & _REGION_ENTRY_ORIGIN; offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8; new_entry = ldq_phys(cs->as, origin + offs); PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", __func__, origin, offs, new_entry); if ((new_entry & _REGION_ENTRY_INV) != 0) { /* XXX different regions have different faults */ DPRINTF("%s: invalid region\n", __func__); trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw); return -1; } if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) { trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); return -1; } /* XXX region protection flags */ /* *flags &= ~PAGE_WRITE */ if (level == _ASCE_TYPE_SEGMENT) { return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags, rw); } /* Check region table offset and length */ offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3; if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6) || offs > (new_entry & _REGION_ENTRY_LENGTH)) { DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry); trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw); return -1; } /* yet another region */ return mmu_translate_region(env, vaddr, asc, new_entry, level - 4, raddr, flags, rw); }


static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src, InputEvent *evt) { ChannelState *s = (ChannelState *)dev; int qcode, keycode; InputKeyEvent *key; assert(evt->type == INPUT_EVENT_KIND_KEY); key = evt->u.key; qcode = qemu_input_key_value_to_qcode(key->key); trace_escc_sunkbd_event_in(qcode, QKeyCode_lookup[qcode], key->down); if (qcode == Q_KEY_CODE_CAPS_LOCK) { if (key->down) { s->caps_lock_mode ^= 1; if (s->caps_lock_mode == 2) { return; /* Drop second press */ } } else { s->caps_lock_mode ^= 2; if (s->caps_lock_mode == 3) { return; /* Drop first release */ } } } if (qcode == Q_KEY_CODE_NUM_LOCK) { if (key->down) { s->num_lock_mode ^= 1; if (s->num_lock_mode == 2) { return; /* Drop second press */ } } else { s->num_lock_mode ^= 2; if (s->num_lock_mode == 3) { return; /* Drop first release */ } } } keycode = qcode_to_keycode[qcode]; if (!key->down) { keycode |= 0x80; } trace_escc_sunkbd_event_out(keycode); put_queue(s, keycode); }


static void fmod_write_sample (HWVoiceOut *hw, uint8_t *dst, int dst_len) { int src_len1 = dst_len; int src_len2 = 0; int pos = hw->rpos + dst_len; st_sample_t *src1 = hw->mix_buf + hw->rpos; st_sample_t *src2 = NULL; if (pos > hw->samples) { src_len1 = hw->samples - hw->rpos; src2 = hw->mix_buf; src_len2 = dst_len - src_len1; pos = src_len2; } if (src_len1) { hw->clip (dst, src1, src_len1); } if (src_len2) { dst = advance (dst, src_len1 << hw->info.shift); hw->clip (dst, src2, src_len2); } hw->rpos = pos % hw->samples; }


static void dealloc_helper(void *native_in, VisitorFunc visit, Error **errp) { QapiDeallocVisitor *qdv = qapi_dealloc_visitor_new(); visit(qapi_dealloc_get_visitor(qdv), &native_in, errp); qapi_dealloc_visitor_cleanup(qdv); }


static void deinterlace_bottom_field_inplace(uint8_t *src1, int src_wrap, int width, int height) { uint8_t *src_m1, *src_0, *src_p1, *src_p2; int y; uint8_t *buf; buf = av_malloc(width); src_m1 = src1; memcpy(buf,src_m1,width); src_0=&src_m1[src_wrap]; src_p1=&src_0[src_wrap]; src_p2=&src_p1[src_wrap]; for(y=0;y<(height-2);y+=2) { deinterlace_line_inplace(buf,src_m1,src_0,src_p1,src_p2,width); src_m1 = src_p1; src_0 = src_p2; src_p1 += 2*src_wrap; src_p2 += 2*src_wrap; } /* do last line */ deinterlace_line_inplace(buf,src_m1,src_0,src_0,src_0,width); av_free(buf); }


bool net_tx_pkt_parse(struct NetTxPkt *pkt) { return net_tx_pkt_parse_headers(pkt) && net_tx_pkt_rebuild_payload(pkt); }


CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; CPUState *env; qemu_irq *pic, *irqs; memset(clk_setup, 0, sizeof(clk_setup)); /* init CPUs */ env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK], &tlb_clk_setup, sysclk); clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; /* Internal devices init */ /* Memory mapped devices registers */ /* PLB arbitrer */ ppc4xx_plb_init(env); /* PLB to OPB bridge */ ppc4xx_pob_init(env); /* OBP arbitrer */ ppc4xx_opba_init(0xef600600); /* Universal interrupt controller */ irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ dma_irqs[0] = pic[5]; dma_irqs[1] = pic[6]; dma_irqs[2] = pic[7]; dma_irqs[3] = pic[8]; ppc405_dma_init(env, dma_irqs); /* IIC controller */ ppc405_i2c_init(0xef600500, pic[2]); /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hds[0] != NULL) { serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hds[0], 1, 1); } if (serial_hds[1] != NULL) { serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hds[1], 1, 1); } /* OCM */ ppc405_ocm_init(env); /* GPT */ gpt_irqs[0] = pic[19]; gpt_irqs[1] = pic[20]; gpt_irqs[2] = pic[21]; gpt_irqs[3] = pic[22]; gpt_irqs[4] = pic[23]; ppc4xx_gpt_init(0xef600000, gpt_irqs); /* PCI */ /* Uses pic[3], pic[16], pic[18] */ /* MAL */ mal_irqs[0] = pic[11]; mal_irqs[1] = pic[12]; mal_irqs[2] = pic[13]; mal_irqs[3] = pic[14]; ppc405_mal_init(env, mal_irqs); /* Ethernet */ /* Uses pic[9], pic[15], pic[17] */ /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); return env; }


void address_space_sync_dirty_bitmap(AddressSpace *as) { FlatView *view; FlatRange *fr; view = as->current_map; FOR_EACH_FLAT_RANGE(fr, view) { MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync); } }


static uint32_t nam_readb (void *opaque, uint32_t addr) { PCIAC97LinkState *d = opaque; AC97LinkState *s = &d->ac97; dolog ("U nam readb %#x\n", addr); s->cas = 0; return ~0U; }


static target_ulong h_client_architecture_support(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { /* Working address in data buffer */ target_ulong addr = ppc64_phys_to_real(args[0]); target_ulong ov_table; uint32_t cas_pvr; sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; bool guest_radix; Error *local_err = NULL; bool raw_mode_supported = false; cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); if (local_err) { error_report_err(local_err); return H_HARDWARE; } /* Update CPUs */ if (cpu->compat_pvr != cas_pvr) { ppc_set_compat_all(cas_pvr, &local_err); if (local_err) { /* We fail to set compat mode (likely because running with KVM PR), * but maybe we can fallback to raw mode if the guest supports it. */ if (!raw_mode_supported) { error_report_err(local_err); return H_HARDWARE; } local_err = NULL; } } /* For the future use: here @ov_table points to the first option vector */ ov_table = addr; ov1_guest = spapr_ovec_parse_vector(ov_table, 1); ov5_guest = spapr_ovec_parse_vector(ov_table, 5); if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { error_report("guest requested hash and radix MMU, which is invalid."); exit(EXIT_FAILURE); } /* The radix/hash bit in byte 24 requires special handling: */ guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); /* * HPT resizing is a bit of a special case, because when enabled * we assume an HPT guest will support it until it says it * doesn't, instead of assuming it won't support it until it says * it does. Strictly speaking that approach could break for * guests which don't make a CAS call, but those are so old we * don't care about them. Without that assumption we'd have to * make at least a temporary allocation of an HPT sized for max * memory, which could be impossibly difficult under KVM HV if * maxram is large. */ if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { error_report( "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); exit(1); } if (spapr->htab_shift < maxshift) { /* Guest doesn't know about HPT resizing, so we * pre-emptively resize for the maximum permitted RAM. At * the point this is called, nothing should have been * entered into the existing HPT */ spapr_reallocate_hpt(spapr, maxshift, &error_fatal); if (kvm_enabled()) { /* For KVM PR, update the HPT pointer */ target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); kvmppc_update_sdr1(sdr1); } } } /* NOTE: there are actually a number of ov5 bits where input from the * guest is always zero, and the platform/QEMU enables them independently * of guest input. To model these properly we'd want some sort of mask, * but since they only currently apply to memory migration as defined * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need * to worry about this for now. */ ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); /* also clear the radix/hash bit from the current ov5_cas bits to * be in sync with the newly ov5 bits. Else the radix bit will be * seen as being removed and this will generate a reset loop */ spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); /* full range of negotiated ov5 capabilities */ spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); spapr_ovec_cleanup(ov5_guest); /* capabilities that have been added since CAS-generated guest reset. * if capabilities have since been removed, generate another reset */ ov5_updates = spapr_ovec_new(); spapr->cas_reboot = spapr_ovec_diff(ov5_updates, ov5_cas_old, spapr->ov5_cas); /* Now that processing is finished, set the radix/hash bit for the * guest if it requested a valid mode; otherwise terminate the boot. */ if (guest_radix) { if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { error_report("Guest requested unavailable MMU mode (radix)."); exit(EXIT_FAILURE); } spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); } else { if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && !kvmppc_has_cap_mmu_hash_v3()) { error_report("Guest requested unavailable MMU mode (hash)."); exit(EXIT_FAILURE); } } spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); if (!spapr->cas_reboot) { spapr->cas_reboot = (spapr_h_cas_compose_response(spapr, args[1], args[2], ov5_updates) != 0); } spapr_ovec_cleanup(ov5_updates); if (spapr->cas_reboot) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } else { /* If ppc_spapr_reset() did not set up a HPT but one is necessary * (because the guest isn't going to use radix) then set it up here. */ if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { /* legacy hash or new hash: */ spapr_setup_hpt_and_vrma(spapr); } } return H_SUCCESS; }


static int mode_sense_page(SCSIDiskState *s, int page, uint8_t **p_outbuf, int page_control) { static const int mode_sense_valid[0x3f] = { [MODE_PAGE_HD_GEOMETRY] = (1 << TYPE_DISK), [MODE_PAGE_FLEXIBLE_DISK_GEOMETRY] = (1 << TYPE_DISK), [MODE_PAGE_CACHING] = (1 << TYPE_DISK) | (1 << TYPE_ROM), [MODE_PAGE_CAPABILITIES] = (1 << TYPE_ROM), }; BlockDriverState *bdrv = s->bs; int cylinders, heads, secs; uint8_t *p = *p_outbuf; if ((mode_sense_valid[page] & (1 << s->qdev.type)) == 0) { return -1; } p[0] = page; /* * If Changeable Values are requested, a mask denoting those mode parameters * that are changeable shall be returned. As we currently don't support * parameter changes via MODE_SELECT all bits are returned set to zero. * The buffer was already menset to zero by the caller of this function. */ switch (page) { case MODE_PAGE_HD_GEOMETRY: p[1] = 0x16; if (page_control == 1) { /* Changeable Values */ break; } /* if a geometry hint is available, use it */ bdrv_get_geometry_hint(bdrv, &cylinders, &heads, &secs); p[2] = (cylinders >> 16) & 0xff; p[3] = (cylinders >> 8) & 0xff; p[4] = cylinders & 0xff; p[5] = heads & 0xff; /* Write precomp start cylinder, disabled */ p[6] = (cylinders >> 16) & 0xff; p[7] = (cylinders >> 8) & 0xff; p[8] = cylinders & 0xff; /* Reduced current start cylinder, disabled */ p[9] = (cylinders >> 16) & 0xff; p[10] = (cylinders >> 8) & 0xff; p[11] = cylinders & 0xff; /* Device step rate [ns], 200ns */ p[12] = 0; p[13] = 200; /* Landing zone cylinder */ p[14] = 0xff; p[15] = 0xff; p[16] = 0xff; /* Medium rotation rate [rpm], 5400 rpm */ p[20] = (5400 >> 8) & 0xff; p[21] = 5400 & 0xff; break; case MODE_PAGE_FLEXIBLE_DISK_GEOMETRY: p[1] = 0x1e; if (page_control == 1) { /* Changeable Values */ break; } /* Transfer rate [kbit/s], 5Mbit/s */ p[2] = 5000 >> 8; p[3] = 5000 & 0xff; /* if a geometry hint is available, use it */ bdrv_get_geometry_hint(bdrv, &cylinders, &heads, &secs); p[4] = heads & 0xff; p[5] = secs & 0xff; p[6] = s->cluster_size * 2; p[8] = (cylinders >> 8) & 0xff; p[9] = cylinders & 0xff; /* Write precomp start cylinder, disabled */ p[10] = (cylinders >> 8) & 0xff; p[11] = cylinders & 0xff; /* Reduced current start cylinder, disabled */ p[12] = (cylinders >> 8) & 0xff; p[13] = cylinders & 0xff; /* Device step rate [100us], 100us */ p[14] = 0; p[15] = 1; /* Device step pulse width [us], 1us */ p[16] = 1; /* Device head settle delay [100us], 100us */ p[17] = 0; p[18] = 1; /* Motor on delay [0.1s], 0.1s */ p[19] = 1; /* Motor off delay [0.1s], 0.1s */ p[20] = 1; /* Medium rotation rate [rpm], 5400 rpm */ p[28] = (5400 >> 8) & 0xff; p[29] = 5400 & 0xff; break; case MODE_PAGE_CACHING: p[0] = 8; p[1] = 0x12; if (page_control == 1) { /* Changeable Values */ break; } if (bdrv_enable_write_cache(s->bs)) { p[2] = 4; /* WCE */ } break; case MODE_PAGE_CAPABILITIES: p[1] = 0x14; if (page_control == 1) { /* Changeable Values */ break; } p[2] = 3; // CD-R & CD-RW read p[3] = 0; // Writing not supported p[4] = 0x7f; /* Audio, composite, digital out, mode 2 form 1&2, multi session */ p[5] = 0xff; /* CD DA, DA accurate, RW supported, RW corrected, C2 errors, ISRC, UPC, Bar code */ p[6] = 0x2d | (s->tray_locked ? 2 : 0); /* Locking supported, jumper present, eject, tray */ p[7] = 0; /* no volume & mute control, no changer */ p[8] = (50 * 176) >> 8; // 50x read speed p[9] = (50 * 176) & 0xff; p[10] = 0 >> 8; // No volume p[11] = 0 & 0xff; p[12] = 2048 >> 8; // 2M buffer p[13] = 2048 & 0xff; p[14] = (16 * 176) >> 8; // 16x read speed current p[15] = (16 * 176) & 0xff; p[18] = (16 * 176) >> 8; // 16x write speed p[19] = (16 * 176) & 0xff; p[20] = (16 * 176) >> 8; // 16x write speed current p[21] = (16 * 176) & 0xff; break; default: return -1; } *p_outbuf += p[1] + 2; return p[1] + 2; }


int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env) { if (!(env->cr[0] & CR0_PG_MASK)) { /* paging is disabled */ return 0; } if (env->cr[4] & CR4_PAE_MASK) { #ifdef TARGET_X86_64 if (env->hflags & HF_LMA_MASK) { target_phys_addr_t pml4e_addr; pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask; walk_pml4e(list, pml4e_addr, env->a20_mask); } else #endif { target_phys_addr_t pdpe_addr; pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask; walk_pdpe2(list, pdpe_addr, env->a20_mask); } } else { target_phys_addr_t pde_addr; bool pse; pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask; pse = !!(env->cr[4] & CR4_PSE_MASK); walk_pde2(list, pde_addr, env->a20_mask, pse); } return 0; }


void ff_h264_filter_mb_fast( H264Context *h, int mb_x, int mb_y, uint8_t *img_y, uint8_t *img_cb, uint8_t *img_cr, unsigned int linesize, unsigned int uvlinesize) { MpegEncContext * const s = &h->s; int mb_xy; int mb_type, left_type, top_type; int qp, qp0, qp1, qpc, qpc0, qpc1, qp_thresh; int chroma = !(CONFIG_GRAY && (s->flags&CODEC_FLAG_GRAY)); int chroma444 = CHROMA444; mb_xy = h->mb_xy; if(!h->h264dsp.h264_loop_filter_strength || h->pps.chroma_qp_diff) { ff_h264_filter_mb(h, mb_x, mb_y, img_y, img_cb, img_cr, linesize, uvlinesize); return; } assert(!FRAME_MBAFF); left_type= h->left_type[LTOP]; top_type= h->top_type; mb_type = s->current_picture.mb_type[mb_xy]; qp = s->current_picture.qscale_table[mb_xy]; qp0 = s->current_picture.qscale_table[mb_xy-1]; qp1 = s->current_picture.qscale_table[h->top_mb_xy]; qpc = get_chroma_qp( h, 0, qp ); qpc0 = get_chroma_qp( h, 0, qp0 ); qpc1 = get_chroma_qp( h, 0, qp1 ); qp0 = (qp + qp0 + 1) >> 1; qp1 = (qp + qp1 + 1) >> 1; qpc0 = (qpc + qpc0 + 1) >> 1; qpc1 = (qpc + qpc1 + 1) >> 1; qp_thresh = 15+52 - h->slice_alpha_c0_offset; if(qp <= qp_thresh && qp0 <= qp_thresh && qp1 <= qp_thresh && qpc <= qp_thresh && qpc0 <= qp_thresh && qpc1 <= qp_thresh) return; if( IS_INTRA(mb_type) ) { int16_t bS4[4] = {4,4,4,4}; int16_t bS3[4] = {3,3,3,3}; int16_t *bSH = FIELD_PICTURE ? bS3 : bS4; if(left_type) filter_mb_edgev( &img_y[4*0], linesize, bS4, qp0, h); if( IS_8x8DCT(mb_type) ) { filter_mb_edgev( &img_y[4*2], linesize, bS3, qp, h); if(top_type){ filter_mb_edgeh( &img_y[4*0*linesize], linesize, bSH, qp1, h); } filter_mb_edgeh( &img_y[4*2*linesize], linesize, bS3, qp, h); } else { filter_mb_edgev( &img_y[4*1], linesize, bS3, qp, h); filter_mb_edgev( &img_y[4*2], linesize, bS3, qp, h); filter_mb_edgev( &img_y[4*3], linesize, bS3, qp, h); if(top_type){ filter_mb_edgeh( &img_y[4*0*linesize], linesize, bSH, qp1, h); } filter_mb_edgeh( &img_y[4*1*linesize], linesize, bS3, qp, h); filter_mb_edgeh( &img_y[4*2*linesize], linesize, bS3, qp, h); filter_mb_edgeh( &img_y[4*3*linesize], linesize, bS3, qp, h); } if(chroma){ if(chroma444){ if(left_type){ filter_mb_edgev( &img_cb[4*0], linesize, bS4, qpc0, h); filter_mb_edgev( &img_cr[4*0], linesize, bS4, qpc0, h); } if( IS_8x8DCT(mb_type) ) { filter_mb_edgev( &img_cb[4*2], linesize, bS3, qpc, h); filter_mb_edgev( &img_cr[4*2], linesize, bS3, qpc, h); if(top_type){ filter_mb_edgeh( &img_cb[4*0*linesize], linesize, bSH, qpc1, h); filter_mb_edgeh( &img_cr[4*0*linesize], linesize, bSH, qpc1, h); } filter_mb_edgeh( &img_cb[4*2*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cr[4*2*linesize], linesize, bS3, qpc, h); } else { filter_mb_edgev( &img_cb[4*1], linesize, bS3, qpc, h); filter_mb_edgev( &img_cr[4*1], linesize, bS3, qpc, h); filter_mb_edgev( &img_cb[4*2], linesize, bS3, qpc, h); filter_mb_edgev( &img_cr[4*2], linesize, bS3, qpc, h); filter_mb_edgev( &img_cb[4*3], linesize, bS3, qpc, h); filter_mb_edgev( &img_cr[4*3], linesize, bS3, qpc, h); if(top_type){ filter_mb_edgeh( &img_cb[4*0*linesize], linesize, bSH, qpc1, h); filter_mb_edgeh( &img_cr[4*0*linesize], linesize, bSH, qpc1, h); } filter_mb_edgeh( &img_cb[4*1*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cr[4*1*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cb[4*2*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cr[4*2*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cb[4*3*linesize], linesize, bS3, qpc, h); filter_mb_edgeh( &img_cr[4*3*linesize], linesize, bS3, qpc, h); } }else{ if(left_type){ filter_mb_edgecv( &img_cb[2*0], uvlinesize, bS4, qpc0, h); filter_mb_edgecv( &img_cr[2*0], uvlinesize, bS4, qpc0, h); } filter_mb_edgecv( &img_cb[2*2], uvlinesize, bS3, qpc, h); filter_mb_edgecv( &img_cr[2*2], uvlinesize, bS3, qpc, h); if(top_type){ filter_mb_edgech( &img_cb[2*0*uvlinesize], uvlinesize, bSH, qpc1, h); filter_mb_edgech( &img_cr[2*0*uvlinesize], uvlinesize, bSH, qpc1, h); } filter_mb_edgech( &img_cb[2*2*uvlinesize], uvlinesize, bS3, qpc, h); filter_mb_edgech( &img_cr[2*2*uvlinesize], uvlinesize, bS3, qpc, h); } } return; } else { LOCAL_ALIGNED_8(int16_t, bS, [2], [4][4]); int edges; if( IS_8x8DCT(mb_type) && (h->cbp&7) == 7 ) { edges = 4; AV_WN64A(bS[0][0], 0x0002000200020002ULL); AV_WN64A(bS[0][2], 0x0002000200020002ULL); AV_WN64A(bS[1][0], 0x0002000200020002ULL); AV_WN64A(bS[1][2], 0x0002000200020002ULL); } else { int mask_edge1 = (3*(((5*mb_type)>>5)&1)) | (mb_type>>4); //(mb_type & (MB_TYPE_16x16 | MB_TYPE_8x16)) ? 3 : (mb_type & MB_TYPE_16x8) ? 1 : 0; int mask_edge0 = 3*((mask_edge1>>1) & ((5*left_type)>>5)&1); // (mb_type & (MB_TYPE_16x16 | MB_TYPE_8x16)) && (h->left_type[LTOP] & (MB_TYPE_16x16 | MB_TYPE_8x16)) ? 3 : 0; int step = 1+(mb_type>>24); //IS_8x8DCT(mb_type) ? 2 : 1; edges = 4 - 3*((mb_type>>3) & !(h->cbp & 15)); //(mb_type & MB_TYPE_16x16) && !(h->cbp & 15) ? 1 : 4; h->h264dsp.h264_loop_filter_strength( bS, h->non_zero_count_cache, h->ref_cache, h->mv_cache, h->list_count==2, edges, step, mask_edge0, mask_edge1, FIELD_PICTURE); } if( IS_INTRA(left_type) ) AV_WN64A(bS[0][0], 0x0004000400040004ULL); if( IS_INTRA(top_type) ) AV_WN64A(bS[1][0], FIELD_PICTURE ? 0x0003000300030003ULL : 0x0004000400040004ULL); #define FILTER(hv,dir,edge)\ if(AV_RN64A(bS[dir][edge])) { \ filter_mb_edge##hv( &img_y[4*edge*(dir?linesize:1)], linesize, bS[dir][edge], edge ? qp : qp##dir, h );\ if(chroma){\ if(chroma444){\ filter_mb_edge##hv( &img_cb[4*edge*(dir?linesize:1)], linesize, bS[dir][edge], edge ? qpc : qpc##dir, h );\ filter_mb_edge##hv( &img_cr[4*edge*(dir?linesize:1)], linesize, bS[dir][edge], edge ? qpc : qpc##dir, h );\ } else if(!(edge&1)) {\ filter_mb_edgec##hv( &img_cb[2*edge*(dir?uvlinesize:1)], uvlinesize, bS[dir][edge], edge ? qpc : qpc##dir, h );\ filter_mb_edgec##hv( &img_cr[2*edge*(dir?uvlinesize:1)], uvlinesize, bS[dir][edge], edge ? qpc : qpc##dir, h );\ }\ }\ } if(left_type) FILTER(v,0,0); if( edges == 1 ) { if(top_type) FILTER(h,1,0); } else if( IS_8x8DCT(mb_type) ) { FILTER(v,0,2); if(top_type) FILTER(h,1,0); FILTER(h,1,2); } else { FILTER(v,0,1); FILTER(v,0,2); FILTER(v,0,3); if(top_type) FILTER(h,1,0); FILTER(h,1,1); FILTER(h,1,2); FILTER(h,1,3); } #undef FILTER } }


static inline void downmix_2f_1r_to_mono(float *samples) { int i; for (i = 0; i < 256; i++) { samples[i] += (samples[i + 256] + samples[i + 512]); samples[i + 256] = samples[i + 512] = 0; } }


static void do_bit_allocation1(AC3DecodeContext *ctx, int chnl) { ac3_audio_block *ab = &ctx->audio_block; int sdecay, fdecay, sgain, dbknee, floor; int lowcomp = 0, fgain = 0, snroffset = 0, fastleak = 0, slowleak = 0; int psd[256], bndpsd[50], excite[50], mask[50], delta; int start = 0, end = 0, bin = 0, i = 0, j = 0, k = 0, lastbin = 0, bndstrt = 0; int bndend = 0, begin = 0, deltnseg = 0, band = 0, seg = 0, address = 0; int fscod = ctx->sync_info.fscod; uint8_t *exps, *deltoffst = 0, *deltlen = 0, *deltba = 0; uint8_t *baps; int do_delta = 0; /* initialization */ sdecay = sdecaytab[ab->sdcycod]; fdecay = fdecaytab[ab->fdcycod]; sgain = sgaintab[ab->sgaincod]; dbknee = dbkneetab[ab->dbpbcod]; floor = floortab[ab->floorcod]; if (chnl == 5) { start = ab->cplstrtmant; end = ab->cplendmant; fgain = fgaintab[ab->cplfgaincod]; snroffset = (((ab->csnroffst - 15) << 4) + ab->cplfsnroffst) << 2; fastleak = (ab->cplfleak << 8) + 768; slowleak = (ab->cplsleak << 8) + 768; exps = ab->dcplexps; baps = ab->cplbap; if (ab->cpldeltbae == AC3_DBASTR_NEW || ab->cpldeltbae == AC3_DBASTR_REUSE) { do_delta = 1; deltnseg = ab->cpldeltnseg; deltoffst = ab->cpldeltoffst; deltlen = ab->cpldeltlen; deltba = ab->cpldeltba; } } else if (chnl == 6) { start = 0; end = 7; lowcomp = 0; fastleak = 0; slowleak = 0; fgain = fgaintab[ab->lfefgaincod]; snroffset = (((ab->csnroffst - 15) << 4) + ab->lfefsnroffst) << 2; exps = ab->dlfeexps; baps = ab->lfebap; } else { start = 0; end = ab->endmant[chnl]; lowcomp = 0; fastleak = 0; slowleak = 0; fgain = fgaintab[ab->fgaincod[chnl]]; snroffset = (((ab->csnroffst - 15) << 4) + ab->fsnroffst[chnl]) << 2; exps = ab->dexps[chnl]; baps = ab->bap[chnl]; if (ab->deltbae[chnl] == AC3_DBASTR_NEW || ab->deltbae[chnl] == AC3_DBASTR_REUSE) { do_delta = 1; deltnseg = ab->deltnseg[chnl]; deltoffst = ab->deltoffst[chnl]; deltlen = ab->deltlen[chnl]; deltba = ab->deltba[chnl]; } } for (bin = start; bin < end; bin++) /* exponent mapping into psd */ psd[bin] = (3072 - ((int)(exps[bin]) << 7)); /* psd integration */ j = start; k = masktab[start]; do { lastbin = FFMIN(bndtab[k] + bndsz[k], end); bndpsd[k] = psd[j]; j++; for (i = j; i < lastbin; i++) { bndpsd[k] = logadd(bndpsd[k], psd[j]); j++; } k++; } while (end > lastbin); /* compute the excite function */ bndstrt = masktab[start]; bndend = masktab[end - 1] + 1; if (bndstrt == 0) { lowcomp = calc_lowcomp(lowcomp, bndpsd[0], bndpsd[1], 0); excite[0] = bndpsd[0] - fgain - lowcomp; lowcomp = calc_lowcomp(lowcomp, bndpsd[1], bndpsd[2], 1); excite[1] = bndpsd[1] - fgain - lowcomp; begin = 7; for (bin = 2; bin < 7; bin++) { if (bndend != 7 || bin != 6) lowcomp = calc_lowcomp(lowcomp, bndpsd[bin], bndpsd[bin + 1], bin); fastleak = bndpsd[bin] - fgain; slowleak = bndpsd[bin] - sgain; excite[bin] = fastleak - lowcomp; if (bndend != 7 || bin != 6) if (bndpsd[bin] <= bndpsd[bin + 1]) { begin = bin + 1; break; } } for (bin = begin; bin < FFMIN(bndend, 22); bin++) { if (bndend != 7 || bin != 6) lowcomp = calc_lowcomp(lowcomp, bndpsd[bin], bndpsd[bin + 1], bin); fastleak -= fdecay; fastleak = FFMAX(fastleak, bndpsd[bin] - fgain); slowleak -= sdecay; slowleak = FFMAX(slowleak, bndpsd[bin] - sgain); excite[bin] = FFMAX(fastleak - lowcomp, slowleak); } begin = 22; } else { begin = bndstrt; } for (bin = begin; bin < bndend; bin++) { fastleak -= fdecay; fastleak = FFMAX(fastleak, bndpsd[bin] - fgain); slowleak -= sdecay; slowleak = FFMAX(slowleak, bndpsd[bin] - sgain); excite[bin] = FFMAX(fastleak, slowleak); } /* compute the masking curve */ for (bin = bndstrt; bin < bndend; bin++) { if (bndpsd[bin] < dbknee) excite[bin] += ((dbknee - bndpsd[bin]) >> 2); mask[bin] = FFMAX(excite[bin], hth[bin][fscod]); } /* apply the delta bit allocation */ if (do_delta) { band = 0; for (seg = 0; seg < deltnseg + 1; seg++) { band += (int)(deltoffst[seg]); if ((int)(deltba[seg]) >= 4) delta = ((int)(deltba[seg]) - 3) << 7; else delta = ((int)(deltba[seg]) - 4) << 7; for (k = 0; k < (int)(deltlen[seg]); k++) { mask[band] += delta; band++; } } } /*compute the bit allocation */ i = start; j = masktab[start]; do { lastbin = FFMIN(bndtab[j] + bndsz[j], end); mask[j] -= snroffset; mask[j] -= floor; if (mask[j] < 0) mask[j] = 0; mask[j] &= 0x1fe0; mask[j] += floor; for (k = i; k < lastbin; k++) { address = (psd[i] - mask[j]) >> 5; address = FFMIN(63, FFMAX(0, address)); baps[i] = baptab[address]; i++; } j++; } while (end > lastbin); }


static int add_shorts_metadata(int count, const char *name, const char *sep, TiffContext *s) { char *ap; int i; int16_t *sp; if (bytestream2_get_bytes_left(&s->gb) < count * sizeof(int16_t)) return -1; sp = av_malloc(count * sizeof(int16_t)); if (!sp) return AVERROR(ENOMEM); for (i = 0; i < count; i++) sp[i] = tget_short(&s->gb, s->le); ap = shorts2str(sp, count, sep); av_freep(&sp); if (!ap) return AVERROR(ENOMEM); av_dict_set(&s->picture.metadata, name, ap, AV_DICT_DONT_STRDUP_VAL); return 0; }


int av_open_input_file(AVFormatContext **ic_ptr, const char *filename, AVInputFormat *fmt, int buf_size, AVFormatParameters *ap) { int err; AVProbeData probe_data, *pd = &probe_data; ByteIOContext *pb = NULL; void *logctx= ap && ap->prealloced_context ? *ic_ptr : NULL; pd->filename = ""; if (filename) pd->filename = filename; pd->buf = NULL; pd->buf_size = 0; if (!fmt) { /* guess format if no file can be opened */ fmt = av_probe_input_format(pd, 0); } /* Do not open file if the format does not need it. XXX: specific hack needed to handle RTSP/TCP */ if (!fmt || !(fmt->flags & AVFMT_NOFILE)) { /* if no file needed do not try to open one */ if ((err=url_fopen(&pb, filename, URL_RDONLY)) < 0) { goto fail; } if (buf_size > 0) { url_setbufsize(pb, buf_size); } if ((err = ff_probe_input_buffer(&pb, &fmt, filename, logctx, 0, 0)) < 0) { goto fail; } } /* if still no format found, error */ if (!fmt) { err = AVERROR_NOFMT; goto fail; } /* check filename in case an image number is expected */ if (fmt->flags & AVFMT_NEEDNUMBER) { if (!av_filename_number_test(filename)) { err = AVERROR_NUMEXPECTED; goto fail; } } err = av_open_input_stream(ic_ptr, pb, filename, fmt, ap); if (err) goto fail; return 0; fail: av_freep(&pd->buf); if (pb) url_fclose(pb); if (ap && ap->prealloced_context) av_free(*ic_ptr); *ic_ptr = NULL; return err; }


static int amr_probe(AVProbeData *p) { //Only check for "#!AMR" which could be amr-wb, amr-nb. //This will also trigger multichannel files: "#!AMR_MC1.0\n" and //"#!AMR-WB_MC1.0\n" (not supported) if (p->buf_size < 5) return 0; if(memcmp(p->buf,AMR_header,5)==0) return AVPROBE_SCORE_MAX; else return 0; }


static int http_read_stream(URLContext *h, uint8_t *buf, int size) { HTTPContext *s = h->priv_data; int err, new_location, read_ret; int64_t seek_ret; int reconnect_delay = 0; if (!s->hd) return AVERROR_EOF; if (s->end_chunked_post && !s->end_header) { err = http_read_header(h, &new_location); if (err < 0) return err; } #if CONFIG_ZLIB if (s->compressed) return http_buf_read_compressed(h, buf, size); #endif /* CONFIG_ZLIB */ read_ret = http_buf_read(h, buf, size); while ((read_ret < 0 && s->reconnect && (!h->is_streamed || s->reconnect_streamed) && s->filesize > 0 && s->off < s->filesize) || (read_ret == AVERROR_EOF && s->reconnect_at_eof && (!h->is_streamed || s->reconnect_streamed))) { uint64_t target = h->is_streamed ? 0 : s->off; if (read_ret == AVERROR_EXIT) return read_ret; if (reconnect_delay > s->reconnect_delay_max) return AVERROR(EIO); av_log(h, AV_LOG_WARNING, "Will reconnect at %"PRIu64" in %d second(s), error=%s.\n", s->off, reconnect_delay, av_err2str(read_ret)); err = ff_network_sleep_interruptible(1000U*1000*reconnect_delay, &h->interrupt_callback); if (err != AVERROR(ETIMEDOUT)) return err; reconnect_delay = 1 + 2*reconnect_delay; seek_ret = http_seek_internal(h, target, SEEK_SET, 1); if (seek_ret >= 0 && seek_ret != target) { av_log(h, AV_LOG_ERROR, "Failed to reconnect at %"PRIu64".\n", target); return read_ret; } read_ret = http_buf_read(h, buf, size); } return read_ret; }


static int yuv4_probe(AVProbeData *pd) { /* check file header */ if (pd->buf_size <= sizeof(Y4M_MAGIC)) return 0; if (strncmp(pd->buf, Y4M_MAGIC, sizeof(Y4M_MAGIC)-1)==0) return AVPROBE_SCORE_MAX; else return 0; }


static rwpipe *rwpipe_open( int argc, char *argv[] ) { rwpipe *this = av_mallocz( sizeof( rwpipe ) ); if ( this != NULL ) { int input[ 2 ]; int output[ 2 ]; pipe( input ); pipe( output ); this->pid = fork(); if ( this->pid == 0 ) { #define COMMAND_SIZE 10240 char *command = av_mallocz( COMMAND_SIZE ); int i; strcpy( command, "" ); for ( i = 0; i < argc; i ++ ) { av_strlcat( command, argv[ i ], COMMAND_SIZE ); av_strlcat( command, " ", COMMAND_SIZE ); } dup2( output[ 0 ], STDIN_FILENO ); dup2( input[ 1 ], STDOUT_FILENO ); close( input[ 0 ] ); close( input[ 1 ] ); close( output[ 0 ] ); close( output[ 1 ] ); execl("/bin/sh", "sh", "-c", command, (char*)NULL ); _exit( 255 ); } else { close( input[ 1 ] ); close( output[ 0 ] ); this->reader = fdopen( input[ 0 ], "r" ); this->writer = fdopen( output[ 1 ], "w" ); } } return this; }


static int validate_codec_tag(AVFormatContext *s, AVStream *st) { const AVCodecTag *avctag; int n; enum AVCodecID id = AV_CODEC_ID_NONE; unsigned int tag = 0; /** * Check that tag + id is in the table * If neither is in the table -> OK * If tag is in the table with another id -> FAIL * If id is in the table with another tag -> FAIL unless strict < normal */ for (n = 0; s->oformat->codec_tag[n]; n++) { avctag = s->oformat->codec_tag[n]; while (avctag->id != AV_CODEC_ID_NONE) { if (avpriv_toupper4(avctag->tag) == avpriv_toupper4(st->codec->codec_tag)) { id = avctag->id; if (id == st->codec->codec_id) return 1; } if (avctag->id == st->codec->codec_id) tag = avctag->tag; avctag++; } } if (id != AV_CODEC_ID_NONE) return 0; if (tag && (st->codec->strict_std_compliance >= FF_COMPLIANCE_NORMAL)) return 0; return 1; }


int coroutine_fn bdrv_co_preadv(BdrvChild *child, int64_t offset, unsigned int bytes, QEMUIOVector *qiov, BdrvRequestFlags flags) { BlockDriverState *bs = child->bs; BlockDriver *drv = bs->drv; BdrvTrackedRequest req; uint64_t align = bs->bl.request_alignment; uint8_t *head_buf = NULL; uint8_t *tail_buf = NULL; QEMUIOVector local_qiov; bool use_local_qiov = false; int ret; if (!drv) { return -ENOMEDIUM; } ret = bdrv_check_byte_request(bs, offset, bytes); if (ret < 0) { return ret; } bdrv_inc_in_flight(bs); /* Don't do copy-on-read if we read data before write operation */ if (bs->copy_on_read && !(flags & BDRV_REQ_NO_SERIALISING)) { flags |= BDRV_REQ_COPY_ON_READ; } /* Align read if necessary by padding qiov */ if (offset & (align - 1)) { head_buf = qemu_blockalign(bs, align); qemu_iovec_init(&local_qiov, qiov->niov + 2); qemu_iovec_add(&local_qiov, head_buf, offset & (align - 1)); qemu_iovec_concat(&local_qiov, qiov, 0, qiov->size); use_local_qiov = true; bytes += offset & (align - 1); offset = offset & ~(align - 1); } if ((offset + bytes) & (align - 1)) { if (!use_local_qiov) { qemu_iovec_init(&local_qiov, qiov->niov + 1); qemu_iovec_concat(&local_qiov, qiov, 0, qiov->size); use_local_qiov = true; } tail_buf = qemu_blockalign(bs, align); qemu_iovec_add(&local_qiov, tail_buf, align - ((offset + bytes) & (align - 1))); bytes = ROUND_UP(bytes, align); } tracked_request_begin(&req, bs, offset, bytes, BDRV_TRACKED_READ); ret = bdrv_aligned_preadv(bs, &req, offset, bytes, align, use_local_qiov ? &local_qiov : qiov, flags); tracked_request_end(&req); bdrv_dec_in_flight(bs); if (use_local_qiov) { qemu_iovec_destroy(&local_qiov); qemu_vfree(head_buf); qemu_vfree(tail_buf); } return ret; }


static coroutine_fn int qcow2_co_flush_to_os(BlockDriverState *bs) { BDRVQcow2State *s = bs->opaque; int ret; qemu_co_mutex_lock(&s->lock); ret = qcow2_cache_flush(bs, s->l2_table_cache); if (ret < 0) { qemu_co_mutex_unlock(&s->lock); return ret; } if (qcow2_need_accurate_refcounts(s)) { ret = qcow2_cache_flush(bs, s->refcount_block_cache); if (ret < 0) { qemu_co_mutex_unlock(&s->lock); return ret; } } qemu_co_mutex_unlock(&s->lock); return 0; }


static void test_submit_many(void) { WorkerTestData data[100]; int i; /* Start more work items than there will be threads. */ for (i = 0; i < 100; i++) { data[i].n = 0; data[i].ret = -EINPROGRESS; thread_pool_submit_aio(worker_cb, &data[i], done_cb, &data[i]); } active = 100; while (active > 0) { qemu_aio_wait(); } for (i = 0; i < 100; i++) { g_assert_cmpint(data[i].n, ==, 1); g_assert_cmpint(data[i].ret, ==, 0); } }


static inline void gen_op_jnz_ecx(TCGMemOp size, int label1) { tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); gen_extu(size, cpu_tmp0); tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); }


static int local_opendir(FsContext *ctx, V9fsPath *fs_path, V9fsFidOpenState *fs) { char buffer[PATH_MAX]; char *path = fs_path->data; fs->dir = opendir(rpath(ctx, path, buffer)); if (!fs->dir) { return -1; } return 0; }


void cpu_outw(CPUState *env, pio_addr_t addr, uint16_t val) { LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); ioport_write(1, addr, val); #ifdef CONFIG_KQEMU if (env) env->last_io_time = cpu_get_time_fast(); #endif }


static void virtio_blk_device_realize(DeviceState *dev, Error **errp) { VirtIODevice *vdev = VIRTIO_DEVICE(dev); VirtIOBlock *s = VIRTIO_BLK(dev); VirtIOBlkConf *conf = &s->conf; Error *err = NULL; static int virtio_blk_id; if (!conf->conf.bs) { error_setg(errp, "drive property not set"); return; } if (!bdrv_is_inserted(conf->conf.bs)) { error_setg(errp, "Device needs media, but drive is empty"); return; } blkconf_serial(&conf->conf, &conf->serial); s->original_wce = bdrv_enable_write_cache(conf->conf.bs); blkconf_geometry(&conf->conf, NULL, 65535, 255, 255, &err); if (err) { error_propagate(errp, err); return; } virtio_init(vdev, "virtio-blk", VIRTIO_ID_BLOCK, sizeof(struct virtio_blk_config)); s->bs = conf->conf.bs; s->rq = NULL; s->sector_mask = (s->conf.conf.logical_block_size / BDRV_SECTOR_SIZE) - 1; s->vq = virtio_add_queue(vdev, 128, virtio_blk_handle_output); s->complete_request = virtio_blk_complete_request; virtio_blk_data_plane_create(vdev, conf, &s->dataplane, &err); if (err != NULL) { error_propagate(errp, err); virtio_cleanup(vdev); return; } s->migration_state_notifier.notify = virtio_blk_migration_state_changed; add_migration_state_change_notifier(&s->migration_state_notifier); s->change = qemu_add_vm_change_state_handler(virtio_blk_dma_restart_cb, s); register_savevm(dev, "virtio-blk", virtio_blk_id++, 2, virtio_blk_save, virtio_blk_load, s); bdrv_set_dev_ops(s->bs, &virtio_block_ops, s); bdrv_set_guest_block_size(s->bs, s->conf.conf.logical_block_size); bdrv_iostatus_enable(s->bs); }


yuv2gray16_2_c_template(SwsContext *c, const uint16_t *buf0, const uint16_t *buf1, const uint16_t *ubuf0, const uint16_t *ubuf1, const uint16_t *vbuf0, const uint16_t *vbuf1, const uint16_t *abuf0, const uint16_t *abuf1, uint8_t *dest, int dstW, int yalpha, int uvalpha, int y, enum PixelFormat target) { int yalpha1 = 4095 - yalpha; \ int i; for (i = 0; i < (dstW >> 1); i++) { const int i2 = 2 * i; int Y1 = (buf0[i2 ] * yalpha1 + buf1[i2 ] * yalpha) >> 11; int Y2 = (buf0[i2+1] * yalpha1 + buf1[i2+1] * yalpha) >> 11; output_pixel(&dest[2 * i2 + 0], Y1); output_pixel(&dest[2 * i2 + 2], Y2); } }


dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) { hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); }


set_interrupt_cause(E1000State *s, int index, uint32_t val) { if (val) val |= E1000_ICR_INT_ASSERTED; s->mac_reg[ICR] = val; s->mac_reg[ICS] = val; qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); }


static int compare_litqobj_to_qobj(LiteralQObject *lhs, QObject *rhs) { if (lhs->type != qobject_type(rhs)) { return 0; } switch (lhs->type) { case QTYPE_QINT: return lhs->value.qint == qint_get_int(qobject_to_qint(rhs)); case QTYPE_QSTRING: return (strcmp(lhs->value.qstr, qstring_get_str(qobject_to_qstring(rhs))) == 0); case QTYPE_QDICT: { int i; for (i = 0; lhs->value.qdict[i].key; i++) { QObject *obj = qdict_get(qobject_to_qdict(rhs), lhs->value.qdict[i].key); if (!compare_litqobj_to_qobj(&lhs->value.qdict[i].value, obj)) { return 0; } } return 1; } case QTYPE_QLIST: { QListCompareHelper helper; helper.index = 0; helper.objs = lhs->value.qlist; helper.result = 1; qlist_iter(qobject_to_qlist(rhs), compare_helper, &helper); return helper.result; } default: break; } return 0; }


static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t asc, int rw, bool exc) { uint64_t tec; tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46; DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec); if (!exc) { return; } trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, tec); }


static int check_oflag_copied(BlockDriverState *bs, BdrvCheckResult *res) { BDRVQcowState *s = bs->opaque; uint64_t *l2_table = qemu_blockalign(bs, s->cluster_size); int ret; int refcount; int i, j; for (i = 0; i < s->l1_size; i++) { uint64_t l1_entry = s->l1_table[i]; uint64_t l2_offset = l1_entry & L1E_OFFSET_MASK; if (!l2_offset) { continue; } refcount = get_refcount(bs, l2_offset >> s->cluster_bits); if (refcount < 0) { /* don't print message nor increment check_errors */ continue; } if ((refcount == 1) != ((l1_entry & QCOW_OFLAG_COPIED) != 0)) { fprintf(stderr, "ERROR OFLAG_COPIED L2 cluster: l1_index=%d " "l1_entry=%" PRIx64 " refcount=%d\n", i, l1_entry, refcount); res->corruptions++; } ret = bdrv_pread(bs->file, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)); if (ret < 0) { fprintf(stderr, "ERROR: Could not read L2 table: %s\n", strerror(-ret)); res->check_errors++; goto fail; } for (j = 0; j < s->l2_size; j++) { uint64_t l2_entry = be64_to_cpu(l2_table[j]); uint64_t data_offset = l2_entry & L2E_OFFSET_MASK; int cluster_type = qcow2_get_cluster_type(l2_entry); if ((cluster_type == QCOW2_CLUSTER_NORMAL) || ((cluster_type == QCOW2_CLUSTER_ZERO) && (data_offset != 0))) { refcount = get_refcount(bs, data_offset >> s->cluster_bits); if (refcount < 0) { /* don't print message nor increment check_errors */ continue; } if ((refcount == 1) != ((l2_entry & QCOW_OFLAG_COPIED) != 0)) { fprintf(stderr, "ERROR OFLAG_COPIED data cluster: " "l2_entry=%" PRIx64 " refcount=%d\n", l2_entry, refcount); res->corruptions++; } } } } ret = 0; fail: qemu_vfree(l2_table); return ret; }


static int map_f(BlockBackend *blk, int argc, char **argv) { int64_t offset; int64_t nb_sectors, total_sectors; char s1[64]; int64_t num; int ret; const char *retstr; offset = 0; total_sectors = blk_nb_sectors(blk); if (total_sectors < 0) { error_report("Failed to query image length: %s", strerror(-total_sectors)); return 0; } nb_sectors = total_sectors; do { ret = map_is_allocated(blk_bs(blk), offset, nb_sectors, &num); if (ret < 0) { error_report("Failed to get allocation status: %s", strerror(-ret)); return 0; } else if (!num) { error_report("Unexpected end of image"); return 0; } retstr = ret ? " allocated" : "not allocated"; cvtstr(offset << 9ULL, s1, sizeof(s1)); printf("[% 24" PRId64 "] % 8" PRId64 "/% 8" PRId64 " sectors %s " "at offset %s (%d)\n", offset << 9ULL, num, nb_sectors, retstr, s1, ret); offset += num; nb_sectors -= num; } while (offset < total_sectors); return 0; }


fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, target_phys_addr_t io_base, BlockDriverState **fds) { fdctrl_t *fdctrl; int io_mem; int i; FLOPPY_DPRINTF("init controller\n"); fdctrl = qemu_mallocz(sizeof(fdctrl_t)); if (!fdctrl) return NULL; fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); if (fdctrl->fifo == NULL) { qemu_free(fdctrl); return NULL; } fdctrl->result_timer = qemu_new_timer(vm_clock, fdctrl_result_timer, fdctrl); fdctrl->version = 0x90; /* Intel 82078 controller */ fdctrl->irq = irq; fdctrl->dma_chann = dma_chann; fdctrl->io_base = io_base; fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */ fdctrl->sun4m = 0; if (fdctrl->dma_chann != -1) { fdctrl->dma_en = 1; DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); } else { fdctrl->dma_en = 0; } for (i = 0; i < 2; i++) { fd_init(&fdctrl->drives[i], fds[i]); } fdctrl_reset(fdctrl, 0); fdctrl->state = FD_CTRL_ACTIVE; if (mem_mapped) { io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl); cpu_register_physical_memory(io_base, 0x08, io_mem); } else { register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read, fdctrl); register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read, fdctrl); register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write, fdctrl); register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write, fdctrl); } register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl); qemu_register_reset(fdctrl_external_reset, fdctrl); for (i = 0; i < 2; i++) { fd_revalidate(&fdctrl->drives[i]); } return fdctrl; }


static void end_frame(AVFilterLink *inlink) { TransContext *trans = inlink->dst->priv; AVFilterBufferRef *inpic = inlink->cur_buf; AVFilterBufferRef *outpic = inlink->dst->outputs[0]->out_buf; AVFilterLink *outlink = inlink->dst->outputs[0]; int plane; for (plane = 0; outpic->data[plane]; plane++) { int hsub = plane == 1 || plane == 2 ? trans->hsub : 0; int vsub = plane == 1 || plane == 2 ? trans->vsub : 0; int pixstep = trans->pixsteps[plane]; int inh = inpic->video->h>>vsub; int outw = outpic->video->w>>hsub; int outh = outpic->video->h>>vsub; uint8_t *out, *in; int outlinesize, inlinesize; int x, y; out = outpic->data[plane]; outlinesize = outpic->linesize[plane]; in = inpic ->data[plane]; inlinesize = inpic ->linesize[plane]; if (trans->dir&1) { in += inpic->linesize[plane] * (inh-1); inlinesize *= -1; } if (trans->dir&2) { out += outpic->linesize[plane] * (outh-1); outlinesize *= -1; } for (y = 0; y < outh; y++) { switch (pixstep) { case 1: for (x = 0; x < outw; x++) out[x] = in[x*inlinesize + y]; break; case 2: for (x = 0; x < outw; x++) *((uint16_t *)(out + 2*x)) = *((uint16_t *)(in + x*inlinesize + y*2)); break; case 3: for (x = 0; x < outw; x++) { int32_t v = AV_RB24(in + x*inlinesize + y*3); AV_WB24(out + 3*x, v); } break; case 4: for (x = 0; x < outw; x++) *((uint32_t *)(out + 4*x)) = *((uint32_t *)(in + x*inlinesize + y*4)); break; } out += outlinesize; } } avfilter_unref_buffer(inpic); ff_draw_slice(outlink, 0, outpic->video->h, 1); ff_end_frame(outlink); avfilter_unref_buffer(outpic); }


void *block_job_create(const BlockJobDriver *driver, BlockDriverState *bs, int64_t speed, BlockDriverCompletionFunc *cb, void *opaque, Error **errp) { BlockJob *job; if (bs->job || bdrv_in_use(bs)) { error_set(errp, QERR_DEVICE_IN_USE, bdrv_get_device_name(bs)); return NULL; } bdrv_ref(bs); bdrv_set_in_use(bs, 1); job = g_malloc0(driver->instance_size); job->driver = driver; job->bs = bs; job->cb = cb; job->opaque = opaque; job->busy = true; bs->job = job; /* Only set speed when necessary to avoid NotSupported error */ if (speed != 0) { Error *local_err = NULL; block_job_set_speed(job, speed, &local_err); if (local_err) { bs->job = NULL; g_free(job); bdrv_set_in_use(bs, 0); error_propagate(errp, local_err); return NULL; } } return job; }


static int apb_pci_bridge_initfn(PCIDevice *dev) { int rc; rc = pci_bridge_initfn(dev); if (rc < 0) { return rc; } pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN); pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA); /* * command register: * According to PCI bridge spec, after reset * bus master bit is off * memory space enable bit is off * According to manual (805-1251.pdf). * the reset value should be zero unless the boot pin is tied high * (which is true) and thus it should be PCI_COMMAND_MEMORY. */ pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); pci_set_byte(dev->config + PCI_REVISION_ID, 0x11); return 0; }


static int proxy_rename(FsContext *ctx, const char *oldpath, const char *newpath) { int retval; V9fsString oldname, newname; v9fs_string_init(&oldname); v9fs_string_init(&newname); v9fs_string_sprintf(&oldname, "%s", oldpath); v9fs_string_sprintf(&newname, "%s", newpath); retval = v9fs_request(ctx->private, T_RENAME, NULL, "ss", &oldname, &newname); v9fs_string_free(&oldname); v9fs_string_free(&newname); if (retval < 0) { errno = -retval; } return retval; }


void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask) { if (addr & mask) { qemu_log("unaligned access addr=%x mask=%x, wr=%d\n", addr, mask, wr); if (!(env->sregs[SR_MSR] & MSR_EE)) { return; } env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ | (dr & 31) << 5; if (mask == 3) { env->sregs[SR_ESR] |= 1 << 11; } helper_raise_exception(EXCP_HW_EXCP); } }


static void gdb_breakpoint_remove_all(CPUState *env) { cpu_breakpoint_remove_all(env, BP_GDB); #ifndef CONFIG_USER_ONLY cpu_watchpoint_remove_all(env, BP_GDB); #endif }


static void handle_pending_signal(CPUArchState *cpu_env, int sig) { CPUState *cpu = ENV_GET_CPU(cpu_env); abi_ulong handler; sigset_t set; target_sigset_t target_old_set; struct target_sigaction *sa; TaskState *ts = cpu->opaque; struct emulated_sigtable *k = &ts->sigtab[sig - 1]; trace_user_handle_signal(cpu_env, sig); /* dequeue signal */ k->pending = 0; sig = gdb_handlesig(cpu, sig); if (!sig) { sa = NULL; handler = TARGET_SIG_IGN; } else { sa = &sigact_table[sig - 1]; handler = sa->_sa_handler; } if (sig == TARGET_SIGSEGV && sigismember(&ts->signal_mask, SIGSEGV)) { /* Guest has blocked SIGSEGV but we got one anyway. Assume this * is a forced SIGSEGV (ie one the kernel handles via force_sig_info * because it got a real MMU fault), and treat as if default handler. */ handler = TARGET_SIG_DFL; } if (handler == TARGET_SIG_DFL) { /* default handler : ignore some signal. The other are job control or fatal */ if (sig == TARGET_SIGTSTP || sig == TARGET_SIGTTIN || sig == TARGET_SIGTTOU) { kill(getpid(),SIGSTOP); } else if (sig != TARGET_SIGCHLD && sig != TARGET_SIGURG && sig != TARGET_SIGWINCH && sig != TARGET_SIGCONT) { force_sig(sig); } } else if (handler == TARGET_SIG_IGN) { /* ignore sig */ } else if (handler == TARGET_SIG_ERR) { force_sig(sig); } else { /* compute the blocked signals during the handler execution */ sigset_t *blocked_set; target_to_host_sigset(&set, &sa->sa_mask); /* SA_NODEFER indicates that the current signal should not be blocked during the handler */ if (!(sa->sa_flags & TARGET_SA_NODEFER)) sigaddset(&set, target_to_host_signal(sig)); /* save the previous blocked signal state to restore it at the end of the signal execution (see do_sigreturn) */ host_to_target_sigset_internal(&target_old_set, &ts->signal_mask); /* block signals in the handler */ blocked_set = ts->in_sigsuspend ? &ts->sigsuspend_mask : &ts->signal_mask; sigorset(&ts->signal_mask, blocked_set, &set); ts->in_sigsuspend = 0; /* if the CPU is in VM86 mode, we restore the 32 bit values */ #if defined(TARGET_I386) && !defined(TARGET_X86_64) { CPUX86State *env = cpu_env; if (env->eflags & VM_MASK) save_v86_state(env); } #endif /* prepare the stack frame of the virtual CPU */ #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) \ || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) /* These targets do not have traditional signals. */ setup_rt_frame(sig, sa, &k->info, &target_old_set, cpu_env); #else if (sa->sa_flags & TARGET_SA_SIGINFO) setup_rt_frame(sig, sa, &k->info, &target_old_set, cpu_env); else setup_frame(sig, sa, &target_old_set, cpu_env); #endif if (sa->sa_flags & TARGET_SA_RESETHAND) { sa->_sa_handler = TARGET_SIG_DFL; } } }


static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { uint32_t level, diff; int i, bit, line; for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { level = s->olevel[i] & s->dir[i]; for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { bit = ffs(diff) - 1; line = bit + 32 * i; qemu_set_irq(s->handler[line], (level >> bit) & 1); } s->prev_level[i] = level; } }


int kvm_init(int smp_cpus) { static const char upgrade_note[] = "Please upgrade to at least kernel 2.6.29 or recent kvm-kmod\n" "(see http://sourceforge.net/projects/kvm).\n"; KVMState *s; int ret; int i; if (smp_cpus > 1) { fprintf(stderr, "No SMP KVM support, use '-smp 1'\n"); return -EINVAL; } s = qemu_mallocz(sizeof(KVMState)); #ifdef KVM_CAP_SET_GUEST_DEBUG TAILQ_INIT(&s->kvm_sw_breakpoints); #endif for (i = 0; i < ARRAY_SIZE(s->slots); i++) s->slots[i].slot = i; s->vmfd = -1; s->fd = open("/dev/kvm", O_RDWR); if (s->fd == -1) { fprintf(stderr, "Could not access KVM kernel module: %m\n"); ret = -errno; goto err; } ret = kvm_ioctl(s, KVM_GET_API_VERSION, 0); if (ret < KVM_API_VERSION) { if (ret > 0) ret = -EINVAL; fprintf(stderr, "kvm version too old\n"); goto err; } if (ret > KVM_API_VERSION) { ret = -EINVAL; fprintf(stderr, "kvm version not supported\n"); goto err; } s->vmfd = kvm_ioctl(s, KVM_CREATE_VM, 0); if (s->vmfd < 0) goto err; /* initially, KVM allocated its own memory and we had to jump through * hooks to make phys_ram_base point to this. Modern versions of KVM * just use a user allocated buffer so we can use regular pages * unmodified. Make sure we have a sufficiently modern version of KVM. */ if (!kvm_check_extension(s, KVM_CAP_USER_MEMORY)) { ret = -EINVAL; fprintf(stderr, "kvm does not support KVM_CAP_USER_MEMORY\n%s", upgrade_note); goto err; } /* There was a nasty bug in < kvm-80 that prevents memory slots from being * destroyed properly. Since we rely on this capability, refuse to work * with any kernel without this capability. */ if (!kvm_check_extension(s, KVM_CAP_DESTROY_MEMORY_REGION_WORKS)) { ret = -EINVAL; fprintf(stderr, "KVM kernel module broken (DESTROY_MEMORY_REGION).\n%s", upgrade_note); goto err; } #ifdef KVM_CAP_COALESCED_MMIO s->coalesced_mmio = kvm_check_extension(s, KVM_CAP_COALESCED_MMIO); #else s->coalesced_mmio = 0; #endif s->broken_set_mem_region = 1; #ifdef KVM_CAP_JOIN_MEMORY_REGIONS_WORKS ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_JOIN_MEMORY_REGIONS_WORKS); if (ret > 0) { s->broken_set_mem_region = 0; } #endif ret = kvm_arch_init(s, smp_cpus); if (ret < 0) goto err; kvm_state = s; return 0; err: if (s) { if (s->vmfd != -1) close(s->vmfd); if (s->fd != -1) close(s->fd); } qemu_free(s); return ret; }


static void unpack_alpha(GetBitContext *gb, uint16_t *dst, int num_coeffs, const int num_bits) { const int mask = (1 << num_bits) - 1; int i, idx, val, alpha_val; idx = 0; alpha_val = mask; do { do { if (get_bits1(gb)) val = get_bits(gb, num_bits); else { int sign; val = get_bits(gb, num_bits == 16 ? 7 : 4); sign = val & 1; val = (val + 2) >> 1; if (sign) val = -val; } alpha_val = (alpha_val + val) & mask; if (num_bits == 16) dst[idx++] = alpha_val >> 6; else dst[idx++] = (alpha_val << 2) | (alpha_val >> 6); if (idx == num_coeffs - 1) break; } while (get_bits1(gb)); val = get_bits(gb, 4); if (!val) val = get_bits(gb, 11); if (idx + val > num_coeffs) val = num_coeffs - idx; if (num_bits == 16) for (i = 0; i < val; i++) dst[idx++] = alpha_val >> 6; else for (i = 0; i < val; i++) dst[idx++] = (alpha_val << 2) | (alpha_val >> 6); } while (idx < num_coeffs); }


static int virtconsole_initfn(VirtIOSerialPort *port) { VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); VirtIOSerialPortInfo *info = DO_UPCAST(VirtIOSerialPortInfo, qdev, vcon->port.dev.info); if (port->id == 0 && !info->is_console) { error_report("Port number 0 on virtio-serial devices reserved for virtconsole devices for backward compatibility."); return -1; } if (vcon->chr) { qemu_chr_add_handlers(vcon->chr, chr_can_read, chr_read, chr_event, vcon); info->have_data = flush_buf; info->guest_open = guest_open; info->guest_close = guest_close; } return 0; }


static int ppc_hash32_get_physical_address(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, target_ulong eaddr, int rw, int access_type) { bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); if (real_mode) { ctx->raddr = eaddr; ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; return 0; } else { int ret = -1; /* Try to find a BAT */ if (env->nb_BATs != 0) { ret = ppc_hash32_get_bat(env, ctx, eaddr, rw, access_type); } if (ret < 0) { /* We didn't match any BAT entry or don't have BATs */ ret = get_segment32(env, ctx, eaddr, rw, access_type); } return ret; } }


static int vmdk_read(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, int nb_sectors) { BDRVVmdkState *s = bs->opaque; int ret; uint64_t n, index_in_cluster; VmdkExtent *extent = NULL; uint64_t cluster_offset; while (nb_sectors > 0) { extent = find_extent(s, sector_num, extent); if (!extent) { return -EIO; } ret = get_cluster_offset( bs, extent, NULL, sector_num << 9, 0, &cluster_offset); index_in_cluster = sector_num % extent->cluster_sectors; n = extent->cluster_sectors - index_in_cluster; if (n > nb_sectors) n = nb_sectors; if (ret) { /* if not allocated, try to read from parent image, if exist */ if (bs->backing_hd) { if (!vmdk_is_cid_valid(bs)) return -EINVAL; ret = bdrv_read(bs->backing_hd, sector_num, buf, n); if (ret < 0) return ret; } else { memset(buf, 0, 512 * n); } } else { ret = bdrv_pread(extent->file, cluster_offset + index_in_cluster * 512, buf, n * 512); if (ret < 0) { return ret; } } nb_sectors -= n; sector_num += n; buf += n * 512; } return 0; }


static bool migrate_params_check(MigrationParameters *params, Error **errp) { if (params->has_compress_level && (params->compress_level < 0 || params->compress_level > 9)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "compress_level", "is invalid, it should be in the range of 0 to 9"); return false; } if (params->has_compress_threads && (params->compress_threads < 1 || params->compress_threads > 255)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "compress_threads", "is invalid, it should be in the range of 1 to 255"); return false; } if (params->has_decompress_threads && (params->decompress_threads < 1 || params->decompress_threads > 255)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "decompress_threads", "is invalid, it should be in the range of 1 to 255"); return false; } if (params->has_cpu_throttle_initial && (params->cpu_throttle_initial < 1 || params->cpu_throttle_initial > 99)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cpu_throttle_initial", "an integer in the range of 1 to 99"); return false; } if (params->has_cpu_throttle_increment && (params->cpu_throttle_increment < 1 || params->cpu_throttle_increment > 99)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cpu_throttle_increment", "an integer in the range of 1 to 99"); return false; } if (params->has_max_bandwidth && (params->max_bandwidth < 0 || params->max_bandwidth > SIZE_MAX)) { error_setg(errp, "Parameter 'max_bandwidth' expects an integer in the" " range of 0 to %zu bytes/second", SIZE_MAX); return false; } if (params->has_downtime_limit && (params->downtime_limit < 0 || params->downtime_limit > MAX_MIGRATE_DOWNTIME)) { error_setg(errp, "Parameter 'downtime_limit' expects an integer in " "the range of 0 to %d milliseconds", MAX_MIGRATE_DOWNTIME); return false; } if (params->has_x_checkpoint_delay && (params->x_checkpoint_delay < 0)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "x_checkpoint_delay", "is invalid, it should be positive"); return false; } if (params->has_x_multifd_channels && (params->x_multifd_channels < 1 || params->x_multifd_channels > 255)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "multifd_channels", "is invalid, it should be in the range of 1 to 255"); return false; } if (params->has_x_multifd_page_count && (params->x_multifd_page_count < 1 || params->x_multifd_page_count > 10000)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "multifd_page_count", "is invalid, it should be in the range of 1 to 10000"); return false; } if (params->has_xbzrle_cache_size && (params->xbzrle_cache_size < qemu_target_page_size() || !is_power_of_2(params->xbzrle_cache_size))) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "xbzrle_cache_size", "is invalid, it should be bigger than target page size" " and a power of two"); return false; } return true; }


int add_exec(struct ex_list **ex_ptr, int do_pty, char *exec, struct in_addr addr, int port) { struct ex_list *tmp_ptr; /* First, check if the port is "bound" */ for (tmp_ptr = *ex_ptr; tmp_ptr; tmp_ptr = tmp_ptr->ex_next) { if (port == tmp_ptr->ex_fport && addr.s_addr == tmp_ptr->ex_addr.s_addr) return -1; } tmp_ptr = *ex_ptr; *ex_ptr = (struct ex_list *)malloc(sizeof(struct ex_list)); (*ex_ptr)->ex_fport = port; (*ex_ptr)->ex_addr = addr; (*ex_ptr)->ex_pty = do_pty; (*ex_ptr)->ex_exec = (do_pty == 3) ? exec : strdup(exec); (*ex_ptr)->ex_next = tmp_ptr; return 0; }


static void dec_sextb(DisasContext *dc) { LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0); if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) { cpu_abort(dc->env, "hardware sign extender is not available\n"); } tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); }


static void mdct512(AC3MDCTContext *mdct, int32_t *out, int16_t *in) { int i, re, im, n, n2, n4; int16_t *rot = mdct->rot_tmp; IComplex *x = mdct->cplx_tmp; n = 1 << mdct->nbits; n2 = n >> 1; n4 = n >> 2; /* shift to simplify computations */ for (i = 0; i <n4; i++) rot[i] = -in[i + 3*n4]; memcpy(&rot[n4], &in[0], 3*n4*sizeof(*in)); /* pre rotation */ for (i = 0; i < n4; i++) { re = ((int)rot[ 2*i] - (int)rot[ n-1-2*i]) >> 1; im = -((int)rot[n2+2*i] - (int)rot[n2-1-2*i]) >> 1; CMUL(x[i].re, x[i].im, re, im, -mdct->xcos1[i], mdct->xsin1[i]); } fft(mdct, x, mdct->nbits - 2); /* post rotation */ for (i = 0; i < n4; i++) { re = x[i].re; im = x[i].im; CMUL(out[n2-1-2*i], out[2*i], re, im, mdct->xsin1[i], mdct->xcos1[i]); } }


static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) { VT686PMState *s = opaque; uint32_t val; addr &= 0x0f; switch (addr) { case 0x00: val = acpi_pm1_evt_get_sts(&s->ar, s->ar.tmr.overflow_time); break; case 0x02: val = s->ar.pm1.evt.en; break; case 0x04: val = s->ar.pm1.cnt.cnt; break; default: val = 0; break; } DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val); return val; }


static int get_cod(Jpeg2000DecoderContext *s, Jpeg2000CodingStyle *c, uint8_t *properties) { Jpeg2000CodingStyle tmp; int compno, ret; if (bytestream2_get_bytes_left(&s->g) < 5) tmp.csty = bytestream2_get_byteu(&s->g); // get progression order tmp.prog_order = bytestream2_get_byteu(&s->g); tmp.nlayers = bytestream2_get_be16u(&s->g); tmp.mct = bytestream2_get_byteu(&s->g); // multiple component transformation if ((ret = get_cox(s, &tmp)) < 0) return ret; for (compno = 0; compno < s->ncomponents; compno++) if (!(properties[compno] & HAD_COC)) memcpy(c + compno, &tmp, sizeof(tmp)); return 0;


static av_cold void construct_perm_table(TwinContext *tctx,enum FrameType ftype) { int block_size; const ModeTab *mtab = tctx->mtab; int size = tctx->avctx->channels*mtab->fmode[ftype].sub; int16_t *tmp_perm = (int16_t *) tctx->tmp_buf; if (ftype == FT_PPC) { size = tctx->avctx->channels; block_size = mtab->ppc_shape_len; } else block_size = mtab->size / mtab->fmode[ftype].sub; permutate_in_line(tmp_perm, tctx->n_div[ftype], size, block_size, tctx->length[ftype], tctx->length_change[ftype], ftype); transpose_perm(tctx->permut[ftype], tmp_perm, tctx->n_div[ftype], tctx->length[ftype], tctx->length_change[ftype]); linear_perm(tctx->permut[ftype], tctx->permut[ftype], size, size*block_size); }


yuv2rgb_1_c_template(SwsContext *c, const int16_t *buf0, const int16_t *ubuf[2], const int16_t *vbuf[2], const int16_t *abuf0, uint8_t *dest, int dstW, int uvalpha, int y, enum PixelFormat target, int hasAlpha) { const int16_t *ubuf0 = ubuf[0], *vbuf0 = vbuf[0]; int i; if (uvalpha < 2048) { for (i = 0; i < (dstW >> 1); i++) { int Y1 = (buf0[i * 2 ] + 64) >> 7; int Y2 = (buf0[i * 2 + 1] + 64) >> 7; int U = (ubuf0[i] + 64) >> 7; int V = (vbuf0[i] + 64) >> 7; int A1, A2; const void *r = c->table_rV[V + YUVRGB_TABLE_HEADROOM], *g = (c->table_gU[U + YUVRGB_TABLE_HEADROOM] + c->table_gV[V + YUVRGB_TABLE_HEADROOM]), *b = c->table_bU[U + YUVRGB_TABLE_HEADROOM]; if (hasAlpha) { A1 = (abuf0[i * 2 ] + 64) >> 7; A2 = (abuf0[i * 2 + 1] + 64) >> 7; } yuv2rgb_write(dest, i, Y1, Y2, hasAlpha ? A1 : 0, hasAlpha ? A2 : 0, r, g, b, y, target, hasAlpha); } } else { const int16_t *ubuf1 = ubuf[1], *vbuf1 = vbuf[1]; for (i = 0; i < (dstW >> 1); i++) { int Y1 = (buf0[i * 2 ] + 64) >> 7; int Y2 = (buf0[i * 2 + 1] + 64) >> 7; int U = (ubuf0[i] + ubuf1[i] + 128) >> 8; int V = (vbuf0[i] + vbuf1[i] + 128) >> 8; int A1, A2; const void *r = c->table_rV[V + YUVRGB_TABLE_HEADROOM], *g = (c->table_gU[U + YUVRGB_TABLE_HEADROOM] + c->table_gV[V + YUVRGB_TABLE_HEADROOM]), *b = c->table_bU[U + YUVRGB_TABLE_HEADROOM]; if (hasAlpha) { A1 = (abuf0[i * 2 ] + 64) >> 7; A2 = (abuf0[i * 2 + 1] + 64) >> 7; } yuv2rgb_write(dest, i, Y1, Y2, hasAlpha ? A1 : 0, hasAlpha ? A2 : 0, r, g, b, y, target, hasAlpha); } } }


void *qemu_vmalloc(size_t size) { /* FIXME: this is not exactly optimal solution since VirtualAlloc has 64Kb granularity, but at least it guarantees us that the memory is page aligned. */ if (!size) { abort(); } return oom_check(VirtualAlloc(NULL, size, MEM_COMMIT, PAGE_READWRITE)); }


static int real_seek(AVFormatContext *avf, int stream, int64_t min_ts, int64_t ts, int64_t max_ts, int flags) { ConcatContext *cat = avf->priv_data; int ret, left, right; if (stream >= 0) { if (stream >= avf->nb_streams) return AVERROR(EINVAL); rescale_interval(avf->streams[stream]->time_base, AV_TIME_BASE_Q, &min_ts, &ts, &max_ts); } left = 0; right = cat->nb_files; while (right - left > 1) { int mid = (left + right) / 2; if (ts < cat->files[mid].start_time) right = mid; else left = mid; } if ((ret = open_file(avf, left)) < 0) return ret; ret = try_seek(avf, stream, min_ts, ts, max_ts, flags); if (ret < 0 && !(flags & AVSEEK_FLAG_BACKWARD) && left < cat->nb_files - 1 && cat->files[left + 1].start_time < max_ts) { if ((ret = open_file(avf, left + 1)) < 0) return ret; ret = try_seek(avf, stream, min_ts, ts, max_ts, flags); } return ret; }


static void FUNC(dequant)(int16_t *coeffs, int16_t log2_size) { int shift = 15 - BIT_DEPTH - log2_size; int x, y; int size = 1 << log2_size; if (shift > 0) { int offset = 1 << (shift - 1); for (y = 0; y < size; y++) { for (x = 0; x < size; x++) { *coeffs = (*coeffs + offset) >> shift; coeffs++; } } } else { for (y = 0; y < size; y++) { for (x = 0; x < size; x++) { *coeffs = *coeffs << -shift; coeffs++; } } } }


vpc_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, QEMUIOVector *qiov, int flags) { BDRVVPCState *s = bs->opaque; int ret; int64_t image_offset; int64_t n_bytes; int64_t bytes_done = 0; VHDFooter *footer = (VHDFooter *) s->footer_buf; QEMUIOVector local_qiov; if (be32_to_cpu(footer->type) == VHD_FIXED) { return bdrv_co_preadv(bs->file, offset, bytes, qiov, 0); } qemu_co_mutex_lock(&s->lock); qemu_iovec_init(&local_qiov, qiov->niov); while (bytes > 0) { image_offset = get_image_offset(bs, offset, false); n_bytes = MIN(bytes, s->block_size - (offset % s->block_size)); if (image_offset == -1) { qemu_iovec_memset(qiov, bytes_done, 0, n_bytes); } else { qemu_iovec_reset(&local_qiov); qemu_iovec_concat(&local_qiov, qiov, bytes_done, n_bytes); ret = bdrv_co_preadv(bs->file, image_offset, n_bytes, &local_qiov, 0); if (ret < 0) { goto fail; } } bytes -= n_bytes; offset += n_bytes; bytes_done += n_bytes; } ret = 0; fail: qemu_iovec_destroy(&local_qiov); qemu_co_mutex_unlock(&s->lock); return ret; }


long do_rt_sigreturn(CPUMIPSState *env) { struct target_rt_sigframe *frame; abi_ulong frame_addr; sigset_t blocked; frame_addr = env->active_tc.gpr[29]; trace_user_do_rt_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { goto badframe; } target_to_host_sigset(&blocked, &frame->rs_uc.tuc_sigmask); set_sigmask(&blocked); restore_sigcontext(env, &frame->rs_uc.tuc_mcontext); if (do_sigaltstack(frame_addr + offsetof(struct target_rt_sigframe, rs_uc.tuc_stack), 0, get_sp_from_cpustate(env)) == -EFAULT) goto badframe; env->active_tc.PC = env->CP0_EPC; mips_set_hflags_isa_mode_from_pc(env); /* I am not sure this is right, but it seems to work * maybe a problem with nested signals ? */ env->CP0_EPC = 0; return -TARGET_QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV/*, current*/); return 0; }


static CharDriverState *qemu_chr_open_socket(QemuOpts *opts) { CharDriverState *chr = NULL; TCPCharDriver *s = NULL; int fd = -1; int is_listen; int is_waitconnect; int do_nodelay; int is_unix; int is_telnet; is_listen = qemu_opt_get_bool(opts, "server", 0); is_waitconnect = qemu_opt_get_bool(opts, "wait", 1); is_telnet = qemu_opt_get_bool(opts, "telnet", 0); do_nodelay = !qemu_opt_get_bool(opts, "delay", 1); is_unix = qemu_opt_get(opts, "path") != NULL; if (!is_listen) is_waitconnect = 0; chr = g_malloc0(sizeof(CharDriverState)); s = g_malloc0(sizeof(TCPCharDriver)); if (is_unix) { if (is_listen) { fd = unix_listen_opts(opts); } else { fd = unix_connect_opts(opts); } } else { if (is_listen) { fd = inet_listen_opts(opts, 0, NULL); } else { fd = inet_connect_opts(opts, true, NULL, NULL); } } if (fd < 0) { goto fail; } if (!is_waitconnect) socket_set_nonblock(fd); s->connected = 0; s->fd = -1; s->listen_fd = -1; s->msgfd = -1; s->is_unix = is_unix; s->do_nodelay = do_nodelay && !is_unix; chr->opaque = s; chr->chr_write = tcp_chr_write; chr->chr_close = tcp_chr_close; chr->get_msgfd = tcp_get_msgfd; chr->chr_add_client = tcp_chr_add_client; if (is_listen) { s->listen_fd = fd; qemu_set_fd_handler2(s->listen_fd, NULL, tcp_chr_accept, NULL, chr); if (is_telnet) s->do_telnetopt = 1; } else { s->connected = 1; s->fd = fd; socket_set_nodelay(fd); tcp_chr_connect(chr); } /* for "info chardev" monitor command */ chr->filename = g_malloc(256); if (is_unix) { snprintf(chr->filename, 256, "unix:%s%s", qemu_opt_get(opts, "path"), qemu_opt_get_bool(opts, "server", 0) ? ",server" : ""); } else if (is_telnet) { snprintf(chr->filename, 256, "telnet:%s:%s%s", qemu_opt_get(opts, "host"), qemu_opt_get(opts, "port"), qemu_opt_get_bool(opts, "server", 0) ? ",server" : ""); } else { snprintf(chr->filename, 256, "tcp:%s:%s%s", qemu_opt_get(opts, "host"), qemu_opt_get(opts, "port"), qemu_opt_get_bool(opts, "server", 0) ? ",server" : ""); } if (is_listen && is_waitconnect) { printf("QEMU waiting for connection on: %s\n", chr->filename); tcp_chr_accept(chr); socket_set_nonblock(s->listen_fd); } return chr; fail: if (fd >= 0) closesocket(fd); g_free(s); g_free(chr); return NULL; }


void qtest_qmpv_discard_response(QTestState *s, const char *fmt, va_list ap) { bool has_reply = false; int nesting = 0; /* Send QMP request */ socket_sendf(s->qmp_fd, fmt, ap); /* Receive reply */ while (!has_reply || nesting > 0) { ssize_t len; char c; len = read(s->qmp_fd, &c, 1); if (len == -1 && errno == EINTR) { continue; } if (len == -1 || len == 0) { fprintf(stderr, "Broken pipe\n"); exit(1); } switch (c) { case '{': nesting++; has_reply = true; break; case '}': nesting--; break; } } }


static av_noinline void FUNC(hl_decode_mb_444)(H264Context *h) { const int mb_x = h->mb_x; const int mb_y = h->mb_y; const int mb_xy = h->mb_xy; const int mb_type = h->cur_pic.f.mb_type[mb_xy]; uint8_t *dest[3]; int linesize; int i, j, p; int *block_offset = &h->block_offset[0]; const int transform_bypass = !SIMPLE && (h->qscale == 0 && h->sps.transform_bypass); const int plane_count = (SIMPLE || !CONFIG_GRAY || !(h->flags & CODEC_FLAG_GRAY)) ? 3 : 1; for (p = 0; p < plane_count; p++) { dest[p] = h->cur_pic.f.data[p] + ((mb_x << PIXEL_SHIFT) + mb_y * h->linesize) * 16; h->vdsp.prefetch(dest[p] + (h->mb_x & 3) * 4 * h->linesize + (64 << PIXEL_SHIFT), h->linesize, 4); } h->list_counts[mb_xy] = h->list_count; if (!SIMPLE && MB_FIELD) { linesize = h->mb_linesize = h->mb_uvlinesize = h->linesize * 2; block_offset = &h->block_offset[48]; if (mb_y & 1) // FIXME move out of this function? for (p = 0; p < 3; p++) dest[p] -= h->linesize * 15; if (FRAME_MBAFF) { int list; for (list = 0; list < h->list_count; list++) { if (!USES_LIST(mb_type, list)) continue; if (IS_16X16(mb_type)) { int8_t *ref = &h->ref_cache[list][scan8[0]]; fill_rectangle(ref, 4, 4, 8, (16 + *ref) ^ (h->mb_y & 1), 1); } else { for (i = 0; i < 16; i += 4) { int ref = h->ref_cache[list][scan8[i]]; if (ref >= 0) fill_rectangle(&h->ref_cache[list][scan8[i]], 2, 2, 8, (16 + ref) ^ (h->mb_y & 1), 1); } } } } } else { linesize = h->mb_linesize = h->mb_uvlinesize = h->linesize; } if (!SIMPLE && IS_INTRA_PCM(mb_type)) { if (PIXEL_SHIFT) { const int bit_depth = h->sps.bit_depth_luma; GetBitContext gb; init_get_bits(&gb, (uint8_t *)h->intra_pcm_ptr, 768 * bit_depth); for (p = 0; p < plane_count; p++) for (i = 0; i < 16; i++) { uint16_t *tmp = (uint16_t *)(dest[p] + i * linesize); for (j = 0; j < 16; j++) tmp[j] = get_bits(&gb, bit_depth); } } else { for (p = 0; p < plane_count; p++) for (i = 0; i < 16; i++) memcpy(dest[p] + i * linesize, (uint8_t *)h->intra_pcm_ptr + p * 256 + i * 16, 16); } } else { if (IS_INTRA(mb_type)) { if (h->deblocking_filter) xchg_mb_border(h, dest[0], dest[1], dest[2], linesize, linesize, 1, 1, SIMPLE, PIXEL_SHIFT); for (p = 0; p < plane_count; p++) hl_decode_mb_predict_luma(h, mb_type, 1, SIMPLE, transform_bypass, PIXEL_SHIFT, block_offset, linesize, dest[p], p); if (h->deblocking_filter) xchg_mb_border(h, dest[0], dest[1], dest[2], linesize, linesize, 0, 1, SIMPLE, PIXEL_SHIFT); } else { FUNC(hl_motion_444)(h, dest[0], dest[1], dest[2], h->me.qpel_put, h->h264chroma.put_h264_chroma_pixels_tab, h->me.qpel_avg, h->h264chroma.avg_h264_chroma_pixels_tab, h->h264dsp.weight_h264_pixels_tab, h->h264dsp.biweight_h264_pixels_tab); } for (p = 0; p < plane_count; p++) hl_decode_mb_idct_luma(h, mb_type, 1, SIMPLE, transform_bypass, PIXEL_SHIFT, block_offset, linesize, dest[p], p); if (h->cbp || IS_INTRA(mb_type)) { h->dsp.clear_blocks(h->mb); h->dsp.clear_blocks(h->mb + (24 * 16 << PIXEL_SHIFT)); } } }


static void msvideo1_decode_8bit(Msvideo1Context *s) { int block_ptr, pixel_ptr; int total_blocks; int pixel_x, pixel_y; /* pixel width and height iterators */ int block_x, block_y; /* block width and height iterators */ int blocks_wide, blocks_high; /* width and height in 4x4 blocks */ int block_inc; int row_dec; /* decoding parameters */ int stream_ptr; unsigned char byte_a, byte_b; unsigned short flags; int skip_blocks; unsigned char colors[8]; unsigned char *pixels = s->frame.data[0]; unsigned char *prev_pixels = s->prev_frame.data[0]; int stride = s->frame.linesize[0]; stream_ptr = 0; skip_blocks = 0; blocks_wide = s->avctx->width / 4; blocks_high = s->avctx->height / 4; total_blocks = blocks_wide * blocks_high; block_inc = 4; row_dec = stride + 4; for (block_y = blocks_high; block_y > 0; block_y--) { block_ptr = ((block_y * 4) - 1) * stride; for (block_x = blocks_wide; block_x > 0; block_x--) { /* check if this block should be skipped */ if (skip_blocks) { COPY_PREV_BLOCK(); block_ptr += block_inc; skip_blocks--; total_blocks--; continue; } pixel_ptr = block_ptr; /* get the next two bytes in the encoded data stream */ CHECK_STREAM_PTR(2); byte_a = s->buf[stream_ptr++]; byte_b = s->buf[stream_ptr++]; /* check if the decode is finished */ if ((byte_a == 0) && (byte_b == 0) && (total_blocks == 0)) return; else if ((byte_b & 0xFC) == 0x84) { /* skip code, but don't count the current block */ skip_blocks = ((byte_b - 0x84) << 8) + byte_a - 1; COPY_PREV_BLOCK(); } else if (byte_b < 0x80) { /* 2-color encoding */ flags = (byte_b << 8) | byte_a; CHECK_STREAM_PTR(2); colors[0] = s->buf[stream_ptr++]; colors[1] = s->buf[stream_ptr++]; for (pixel_y = 0; pixel_y < 4; pixel_y++) { for (pixel_x = 0; pixel_x < 4; pixel_x++, flags >>= 1) pixels[pixel_ptr++] = colors[(flags & 0x1) ^ 1]; pixel_ptr -= row_dec; } } else if (byte_b >= 0x90) { /* 8-color encoding */ flags = (byte_b << 8) | byte_a; CHECK_STREAM_PTR(8); memcpy(colors, &s->buf[stream_ptr], 8); stream_ptr += 8; for (pixel_y = 0; pixel_y < 4; pixel_y++) { for (pixel_x = 0; pixel_x < 4; pixel_x++, flags >>= 1) pixels[pixel_ptr++] = colors[((pixel_y & 0x2) << 1) + (pixel_x & 0x2) + ((flags & 0x1) ^ 1)]; pixel_ptr -= row_dec; } } else { /* 1-color encoding */ colors[0] = byte_a; for (pixel_y = 0; pixel_y < 4; pixel_y++) { for (pixel_x = 0; pixel_x < 4; pixel_x++) pixels[pixel_ptr++] = colors[0]; pixel_ptr -= row_dec; } } block_ptr += block_inc; total_blocks--; } } /* make the palette available on the way out */ if (s->avctx->pix_fmt == PIX_FMT_PAL8) memcpy(s->frame.data[1], s->palette, PALETTE_COUNT * 4); }


static int lrc_read_header(AVFormatContext *s) { LRCContext *lrc = s->priv_data; AVBPrint line; AVStream *st; st = avformat_new_stream(s, NULL); if(!st) { return AVERROR(ENOMEM); } avpriv_set_pts_info(st, 64, 1, 1000); lrc->ts_offset = 0; st->codecpar->codec_type = AVMEDIA_TYPE_SUBTITLE; st->codecpar->codec_id = AV_CODEC_ID_TEXT; av_bprint_init(&line, 0, AV_BPRINT_SIZE_UNLIMITED); while(!avio_feof(s->pb)) { int64_t pos = read_line(&line, s->pb); int64_t header_offset = find_header(line.str); if(header_offset >= 0) { char *comma_offset = strchr(line.str, ':'); if(comma_offset) { char *right_bracket_offset = strchr(line.str, ']'); if(!right_bracket_offset) { continue; } *right_bracket_offset = *comma_offset = '\0'; if(strcmp(line.str + 1, "offset") || sscanf(comma_offset + 1, "%"SCNd64, &lrc->ts_offset) != 1) { av_dict_set(&s->metadata, line.str + 1, comma_offset + 1, 0); } *comma_offset = ':'; *right_bracket_offset = ']'; } } else { AVPacket *sub; int64_t ts_start = AV_NOPTS_VALUE; int64_t ts_stroffset = 0; int64_t ts_stroffset_incr = 0; int64_t ts_strlength = count_ts(line.str); while((ts_stroffset_incr = read_ts(line.str + ts_stroffset, &ts_start)) != 0) { ts_stroffset += ts_stroffset_incr; sub = ff_subtitles_queue_insert(&lrc->q, line.str + ts_strlength, line.len - ts_strlength, 0); if(!sub) { return AVERROR(ENOMEM); } sub->pos = pos; sub->pts = ts_start - lrc->ts_offset; sub->duration = -1; } } } ff_subtitles_queue_finalize(s, &lrc->q); ff_metadata_conv_ctx(s, NULL, ff_lrc_metadata_conv); return 0; }


static int asf_write_header1(AVFormatContext *s, int64_t file_size, int64_t data_chunk_size) { ASFContext *asf = s->priv_data; AVIOContext *pb = s->pb; AVDictionaryEntry *tags[5]; int header_size, n, extra_size, extra_size2, wav_extra_size, file_time; int has_title; int metadata_count; AVCodecParameters *par; int64_t header_offset, cur_pos, hpos; int bit_rate; int64_t duration; ff_metadata_conv(&s->metadata, ff_asf_metadata_conv, NULL); tags[0] = av_dict_get(s->metadata, "title", NULL, 0); tags[1] = av_dict_get(s->metadata, "author", NULL, 0); tags[2] = av_dict_get(s->metadata, "copyright", NULL, 0); tags[3] = av_dict_get(s->metadata, "comment", NULL, 0); tags[4] = av_dict_get(s->metadata, "rating", NULL, 0); duration = asf->duration + PREROLL_TIME * 10000; has_title = tags[0] || tags[1] || tags[2] || tags[3] || tags[4]; metadata_count = av_dict_count(s->metadata); bit_rate = 0; for (n = 0; n < s->nb_streams; n++) { par = s->streams[n]->codecpar; avpriv_set_pts_info(s->streams[n], 32, 1, 1000); /* 32 bit pts in ms */ bit_rate += par->bit_rate; } if (asf->is_streamed) { put_chunk(s, 0x4824, 0, 0xc00); /* start of stream (length will be patched later) */ } put_guid(pb, &ff_asf_header); avio_wl64(pb, -1); /* header length, will be patched after */ avio_wl32(pb, 3 + has_title + !!metadata_count + s->nb_streams); /* number of chunks in header */ avio_w8(pb, 1); /* ??? */ avio_w8(pb, 2); /* ??? */ /* file header */ header_offset = avio_tell(pb); hpos = put_header(pb, &ff_asf_file_header); put_guid(pb, &ff_asf_my_guid); avio_wl64(pb, file_size); file_time = 0; avio_wl64(pb, unix_to_file_time(file_time)); avio_wl64(pb, asf->nb_packets); /* number of packets */ avio_wl64(pb, duration); /* end time stamp (in 100ns units) */ avio_wl64(pb, asf->duration); /* duration (in 100ns units) */ avio_wl64(pb, PREROLL_TIME); /* start time stamp */ avio_wl32(pb, (asf->is_streamed || !pb->seekable) ? 3 : 2); /* ??? */ avio_wl32(pb, s->packet_size); /* packet size */ avio_wl32(pb, s->packet_size); /* packet size */ avio_wl32(pb, bit_rate); /* Nominal data rate in bps */ end_header(pb, hpos); /* unknown headers */ hpos = put_header(pb, &ff_asf_head1_guid); put_guid(pb, &ff_asf_head2_guid); avio_wl32(pb, 6); avio_wl16(pb, 0); end_header(pb, hpos); /* title and other infos */ if (has_title) { int len; uint8_t *buf; AVIOContext *dyn_buf; if (avio_open_dyn_buf(&dyn_buf) < 0) return AVERROR(ENOMEM); hpos = put_header(pb, &ff_asf_comment_header); for (n = 0; n < FF_ARRAY_ELEMS(tags); n++) { len = tags[n] ? avio_put_str16le(dyn_buf, tags[n]->value) : 0; avio_wl16(pb, len); } len = avio_close_dyn_buf(dyn_buf, &buf); avio_write(pb, buf, len); av_freep(&buf); end_header(pb, hpos); } if (metadata_count) { AVDictionaryEntry *tag = NULL; hpos = put_header(pb, &ff_asf_extended_content_header); avio_wl16(pb, metadata_count); while ((tag = av_dict_get(s->metadata, "", tag, AV_DICT_IGNORE_SUFFIX))) { put_str16(pb, tag->key); avio_wl16(pb, 0); put_str16(pb, tag->value); } end_header(pb, hpos); } /* chapters using ASF markers */ if (!asf->is_streamed && s->nb_chapters) { int ret; if (ret = asf_write_markers(s)) return ret; } /* stream headers */ for (n = 0; n < s->nb_streams; n++) { int64_t es_pos; // ASFStream *stream = &asf->streams[n]; par = s->streams[n]->codecpar; asf->streams[n].num = n + 1; asf->streams[n].seq = 0; switch (par->codec_type) { case AVMEDIA_TYPE_AUDIO: wav_extra_size = 0; extra_size = 18 + wav_extra_size; extra_size2 = 8; break; default: case AVMEDIA_TYPE_VIDEO: wav_extra_size = par->extradata_size; extra_size = 0x33 + wav_extra_size; extra_size2 = 0; break; } hpos = put_header(pb, &ff_asf_stream_header); if (par->codec_type == AVMEDIA_TYPE_AUDIO) { put_guid(pb, &ff_asf_audio_stream); put_guid(pb, &ff_asf_audio_conceal_spread); } else { put_guid(pb, &ff_asf_video_stream); put_guid(pb, &ff_asf_video_conceal_none); } avio_wl64(pb, 0); /* ??? */ es_pos = avio_tell(pb); avio_wl32(pb, extra_size); /* wav header len */ avio_wl32(pb, extra_size2); /* additional data len */ avio_wl16(pb, n + 1); /* stream number */ avio_wl32(pb, 0); /* ??? */ if (par->codec_type == AVMEDIA_TYPE_AUDIO) { /* WAVEFORMATEX header */ int wavsize = ff_put_wav_header(s, pb, par); if (wavsize < 0) return -1; if (wavsize != extra_size) { cur_pos = avio_tell(pb); avio_seek(pb, es_pos, SEEK_SET); avio_wl32(pb, wavsize); /* wav header len */ avio_seek(pb, cur_pos, SEEK_SET); } /* ERROR Correction */ avio_w8(pb, 0x01); if (par->codec_id == AV_CODEC_ID_ADPCM_G726 || !par->block_align) { avio_wl16(pb, 0x0190); avio_wl16(pb, 0x0190); } else { avio_wl16(pb, par->block_align); avio_wl16(pb, par->block_align); } avio_wl16(pb, 0x01); avio_w8(pb, 0x00); } else { avio_wl32(pb, par->width); avio_wl32(pb, par->height); avio_w8(pb, 2); /* ??? */ avio_wl16(pb, 40 + par->extradata_size); /* size */ /* BITMAPINFOHEADER header */ ff_put_bmp_header(pb, par, ff_codec_bmp_tags, 1); } end_header(pb, hpos); } /* media comments */ hpos = put_header(pb, &ff_asf_codec_comment_header); put_guid(pb, &ff_asf_codec_comment1_header); avio_wl32(pb, s->nb_streams); for (n = 0; n < s->nb_streams; n++) { const AVCodecDescriptor *codec_desc; const char *desc; par = s->streams[n]->codecpar; codec_desc = avcodec_descriptor_get(par->codec_id); if (par->codec_type == AVMEDIA_TYPE_AUDIO) avio_wl16(pb, 2); else if (par->codec_type == AVMEDIA_TYPE_VIDEO) avio_wl16(pb, 1); else avio_wl16(pb, -1); if (par->codec_id == AV_CODEC_ID_WMAV2) desc = "Windows Media Audio V8"; else desc = codec_desc ? codec_desc->name : NULL; if (desc) { AVIOContext *dyn_buf; uint8_t *buf; int len; if (avio_open_dyn_buf(&dyn_buf) < 0) return AVERROR(ENOMEM); avio_put_str16le(dyn_buf, desc); len = avio_close_dyn_buf(dyn_buf, &buf); avio_wl16(pb, len / 2); // "number of characters" = length in bytes / 2 avio_write(pb, buf, len); av_freep(&buf); } else avio_wl16(pb, 0); avio_wl16(pb, 0); /* no parameters */ /* id */ if (par->codec_type == AVMEDIA_TYPE_AUDIO) { avio_wl16(pb, 2); avio_wl16(pb, par->codec_tag); } else { avio_wl16(pb, 4); avio_wl32(pb, par->codec_tag); } if (!par->codec_tag) return -1; } end_header(pb, hpos); /* patch the header size fields */ cur_pos = avio_tell(pb); header_size = cur_pos - header_offset; if (asf->is_streamed) { header_size += 8 + 30 + DATA_HEADER_SIZE; avio_seek(pb, header_offset - 10 - 30, SEEK_SET); avio_wl16(pb, header_size); avio_seek(pb, header_offset - 2 - 30, SEEK_SET); avio_wl16(pb, header_size); header_size -= 8 + 30 + DATA_HEADER_SIZE; } header_size += 24 + 6; avio_seek(pb, header_offset - 14, SEEK_SET); avio_wl64(pb, header_size); avio_seek(pb, cur_pos, SEEK_SET); /* movie chunk, followed by packets of packet_size */ asf->data_offset = cur_pos; put_guid(pb, &ff_asf_data_header); avio_wl64(pb, data_chunk_size); put_guid(pb, &ff_asf_my_guid); avio_wl64(pb, asf->nb_packets); /* nb packets */ avio_w8(pb, 1); /* ??? */ avio_w8(pb, 1); /* ??? */ return 0; }


void qemu_aio_wait(void) { sigset_t set; int nb_sigs; #if !defined(QEMU_IMG) && !defined(QEMU_NBD) if (qemu_bh_poll()) return; #endif sigemptyset(&set); sigaddset(&set, aio_sig_num); sigwait(&set, &nb_sigs); qemu_aio_poll(); }


static void config_error(Monitor *mon, const char *fmt, ...) { va_list ap; va_start(ap, fmt); if (mon) { monitor_vprintf(mon, fmt, ap); } else { fprintf(stderr, "qemu: "); vfprintf(stderr, fmt, ap); exit(1); } va_end(ap); }


static int coroutine_fn raw_co_writev(BlockDriverState *bs, int64_t sector_num, int nb_sectors, QEMUIOVector *qiov) { BLKDBG_EVENT(bs->file, BLKDBG_WRITE_AIO); return bdrv_co_writev(bs->file, sector_num, nb_sectors, qiov); }


void g_free(void *ptr) { /* FIXME: We should unmark the reserved pages here. However this gets complicated when one target page spans multiple host pages, so we don't bother. */ size_t *p; p = (size_t *)((char *)ptr - 16); munmap(p, *p); }


static SCSIGenericReq *scsi_new_request(SCSIDevice *d, uint32_t tag, uint32_t lun) { SCSIRequest *req; req = scsi_req_alloc(sizeof(SCSIGenericReq), d, tag, lun); return DO_UPCAST(SCSIGenericReq, req, req); }


static void test_reconnect(void) { gchar *path = g_strdup_printf("/%s/vhost-user/reconnect/subprocess", qtest_get_arch()); g_test_trap_subprocess(path, 0, 0); g_test_trap_assert_passed(); }


int64_t qdict_get_try_int(const QDict *qdict, const char *key, int64_t def_value) { QObject *obj; obj = qdict_get(qdict, key); if (!obj || qobject_type(obj) != QTYPE_QINT) return def_value; return qint_get_int(qobject_to_qint(obj)); }