static void *spapr_create_fdt_skel(hwaddr initrd_base, hwaddr initrd_size, hwaddr kernel_size, bool little_endian, const char *boot_device, const char *kernel_cmdline, uint32_t epow_irq) { void *fdt; CPUState *cs; uint32_t start_prop = cpu_to_be32(initrd_base); uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); GString *hypertas = g_string_sized_new(256); GString *qemu_hypertas = g_string_sized_new(256); uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; int smt = kvmppc_smt_threads(); unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; add_str(hypertas, "hcall-pft"); add_str(hypertas, "hcall-term"); add_str(hypertas, "hcall-dabr"); add_str(hypertas, "hcall-interrupt"); add_str(hypertas, "hcall-tce"); add_str(hypertas, "hcall-vio"); add_str(hypertas, "hcall-splpar"); add_str(hypertas, "hcall-bulk"); add_str(hypertas, "hcall-set-mode"); add_str(qemu_hypertas, "hcall-memop1"); fdt = g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create(fdt, FDT_MAX_SIZE))); if (kernel_size) { _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); } if (initrd_size) { _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); } _FDT((fdt_finish_reservemap(fdt))); /* Root node */ _FDT((fdt_begin_node(fdt, ""))); _FDT((fdt_property_string(fdt, "device_type", "chrp"))); _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); /* /chosen */ _FDT((fdt_begin_node(fdt, "chosen"))); /* Set Form1_affinity */ _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); _FDT((fdt_property(fdt, "linux,initrd-start", &start_prop, sizeof(start_prop)))); _FDT((fdt_property(fdt, "linux,initrd-end", &end_prop, sizeof(end_prop)))); if (kernel_size) { uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), cpu_to_be64(kernel_size) }; _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); if (little_endian) { _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); } } if (boot_device) { _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); } if (boot_menu) { _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); } _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); _FDT((fdt_end_node(fdt))); /* cpus */ _FDT((fdt_begin_node(fdt, "cpus"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; DeviceClass *dc = DEVICE_GET_CLASS(cs); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); int index = ppc_get_vcpu_dt_id(cpu); char *nodename; uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 0xffffffff, 0xffffffff}; uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; uint32_t page_sizes_prop[64]; size_t page_sizes_prop_size; if ((index % smt) != 0) { continue; } nodename = g_strdup_printf("%s@%x", dc->fw_name, index); _FDT((fdt_begin_node(fdt, nodename))); g_free(nodename); _FDT((fdt_property_cell(fdt, "reg", index))); _FDT((fdt_property_string(fdt, "device_type", "cpu"))); _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); _FDT((fdt_property_cell(fdt, "d-cache-block-size", env->dcache_line_size))); _FDT((fdt_property_cell(fdt, "d-cache-line-size", env->dcache_line_size))); _FDT((fdt_property_cell(fdt, "i-cache-block-size", env->icache_line_size))); _FDT((fdt_property_cell(fdt, "i-cache-line-size", env->icache_line_size))); if (pcc->l1_dcache_size) { _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); } else { fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); } if (pcc->l1_icache_size) { _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); } else { fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); } _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); _FDT((fdt_property_string(fdt, "status", "okay"))); _FDT((fdt_property(fdt, "64-bit", NULL, 0))); if (env->spr_cb[SPR_PURR].oea_read) { _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); } if (env->mmu_model & POWERPC_MMU_1TSEG) { _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", segs, sizeof(segs)))); } /* Advertise VMX/VSX (vector extensions) if available * 0 / no property == no vector extensions * 1 == VMX / Altivec available * 2 == VSX available */ if (env->insns_flags & PPC_ALTIVEC) { uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); } /* Advertise DFP (Decimal Floating Point) if available * 0 / no property == no DFP * 1 == DFP available */ if (env->insns_flags2 & PPC2_DFP) { _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); } page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, sizeof(page_sizes_prop)); if (page_sizes_prop_size) { _FDT((fdt_property(fdt, "ibm,segment-page-sizes", page_sizes_prop, page_sizes_prop_size))); } _FDT((fdt_property_cell(fdt, "ibm,chip-id", cs->cpu_index / cpus_per_socket))); _FDT((fdt_end_node(fdt))); } _FDT((fdt_end_node(fdt))); /* RTAS */ _FDT((fdt_begin_node(fdt, "rtas"))); if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { add_str(hypertas, "hcall-multi-tce"); } _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, hypertas->len))); g_string_free(hypertas, TRUE); _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, qemu_hypertas->len))); g_string_free(qemu_hypertas, TRUE); _FDT((fdt_property(fdt, "ibm,associativity-reference-points", refpoints, sizeof(refpoints)))); _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); _FDT((fdt_end_node(fdt))); /* interrupt controller */ _FDT((fdt_begin_node(fdt, "interrupt-controller"))); _FDT((fdt_property_string(fdt, "device_type", "PowerPC-External-Interrupt-Presentation"))); _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", interrupt_server_ranges_prop, sizeof(interrupt_server_ranges_prop)))); _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); _FDT((fdt_end_node(fdt))); /* vdevice */ _FDT((fdt_begin_node(fdt, "vdevice"))); _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); _FDT((fdt_end_node(fdt))); /* event-sources */ spapr_events_fdt_skel(fdt, epow_irq); /* /hypervisor node */ if (kvm_enabled()) { uint8_t hypercall[16]; /* indicate KVM hypercall interface */ _FDT((fdt_begin_node(fdt, "hypervisor"))); _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); if (kvmppc_has_cap_fixup_hcalls()) { * Older KVM versions with older guest kernels were broken with the * magic page, don't allow the guest to map it. kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, sizeof(hypercall)); _FDT((fdt_property(fdt, "hcall-instructions", hypercall, sizeof(hypercall)))); } _FDT((fdt_end_node(fdt))); } _FDT((fdt_end_node(fdt))); /* close root node */ _FDT((fdt_finish(fdt))); return fdt; }


static void vga_screen_dump(void *opaque, const char *filename) { VGAState *s = (VGAState *)opaque; if (!(s->ar_index & 0x20)) vga_screen_dump_blank(s, filename); else if (s->gr[6] & 1) vga_screen_dump_graphic(s, filename); else vga_screen_dump_text(s, filename); }


static void bamboo_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; PCIBus *pcibus; CPUState *env; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t entry = 0; target_phys_addr_t loadaddr = 0; target_long initrd_size = 0; int success; int i; /* Setup CPU. */ env = ppc440ep_init(&ram_size, &pcibus, pci_irq_nrs, 1, cpu_model); if (pcibus) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { /* There are no PCI NICs on the Bamboo board, but there are * PCI slots, so we can pick whatever default model we want. */ pci_nic_init_nofail(&nd_table[i], "e1000", NULL); } } /* Load kernel. */ if (kernel_filename) { success = load_uimage(kernel_filename, &entry, &loadaddr, NULL); if (success < 0) { success = load_elf(kernel_filename, NULL, NULL, &elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); entry = elf_entry; loadaddr = elf_lowaddr; } /* XXX try again as binary */ if (success < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } } /* Load initrd. */ if (initrd_filename) { initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, ram_size - RAMDISK_ADDR); if (initrd_size < 0) { fprintf(stderr, "qemu: could not load ram disk '%s' at %x\n", initrd_filename, RAMDISK_ADDR); exit(1); } } /* If we're loading a kernel directly, we must load the device tree too. */ if (kernel_filename) { if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, initrd_size, kernel_cmdline) < 0) { fprintf(stderr, "couldn't load device tree\n"); exit(1); } cpu_synchronize_state(env); /* Set initial guest state. */ env->gpr[1] = (16<<20) - 8; env->gpr[3] = FDT_ADDR; env->nip = entry; /* XXX we currently depend on KVM to create some initial TLB entries. */ } if (kvm_enabled()) kvmppc_init(); }


static int show_hwaccels(void *optctx, const char *opt, const char *arg) { int i; printf("Hardware acceleration methods:\n"); for (i = 0; hwaccels[i].name; i++) { printf("%s\n", hwaccels[i].name); } printf("\n"); return 0; }


static int Faac_encode_frame(AVCodecContext *avctx, AVPacket *avpkt, const AVFrame *frame, int *got_packet_ptr) { FaacAudioContext *s = avctx->priv_data; int bytes_written, ret; int num_samples = frame ? frame->nb_samples : 0; void *samples = frame ? frame->data[0] : NULL; if ((ret = ff_alloc_packet2(avctx, avpkt, (7 + 768) * avctx->channels))) { av_log(avctx, AV_LOG_ERROR, "Error getting output packet\n"); return ret; } bytes_written = faacEncEncode(s->faac_handle, samples, num_samples * avctx->channels, avpkt->data, avpkt->size); if (bytes_written < 0) { av_log(avctx, AV_LOG_ERROR, "faacEncEncode() error\n"); return bytes_written; } /* add current frame to the queue */ if (frame) { if ((ret = ff_af_queue_add(&s->afq, frame)) < 0) return ret; } if (!bytes_written) return 0; /* Get the next frame pts/duration */ ff_af_queue_remove(&s->afq, avctx->frame_size, &avpkt->pts, &avpkt->duration); avpkt->size = bytes_written; *got_packet_ptr = 1; return 0; }


static int check_mv(H264Context *h, long b_idx, long bn_idx, int mvy_limit){ int v; v = h->ref_cache[0][b_idx] != h->ref_cache[0][bn_idx] | h->mv_cache[0][b_idx][0] - h->mv_cache[0][bn_idx][0] + 3 >= 7U | FFABS( h->mv_cache[0][b_idx][1] - h->mv_cache[0][bn_idx][1] ) >= mvy_limit; if(h->list_count==2){ if(!v) v = h->ref_cache[1][b_idx] != h->ref_cache[1][bn_idx] | h->mv_cache[1][b_idx][0] - h->mv_cache[1][bn_idx][0] + 3 >= 7U | FFABS( h->mv_cache[1][b_idx][1] - h->mv_cache[1][bn_idx][1] ) >= mvy_limit; if(v){ if(h->ref_cache[0][b_idx] != h->ref_cache[1][bn_idx] | h->ref_cache[1][b_idx] != h->ref_cache[0][bn_idx]) return 1; return h->mv_cache[0][b_idx][0] - h->mv_cache[1][bn_idx][0] + 3 >= 7U | FFABS( h->mv_cache[0][b_idx][1] - h->mv_cache[1][bn_idx][1] ) >= mvy_limit | h->mv_cache[1][b_idx][0] - h->mv_cache[0][bn_idx][0] + 3 >= 7U | FFABS( h->mv_cache[1][b_idx][1] - h->mv_cache[0][bn_idx][1] ) >= mvy_limit; } } return v; }


static int decode_band_types(AACContext *ac, enum BandType band_type[120], int band_type_run_end[120], GetBitContext *gb, IndividualChannelStream *ics) { int g, idx = 0; const int bits = (ics->window_sequence[0] == EIGHT_SHORT_SEQUENCE) ? 3 : 5; for (g = 0; g < ics->num_window_groups; g++) { int k = 0; while (k < ics->max_sfb) { uint8_t sect_end = k; int sect_len_incr; int sect_band_type = get_bits(gb, 4); if (sect_band_type == 12) { av_log(ac->avctx, AV_LOG_ERROR, "invalid band type\n"); return -1; } while ((sect_len_incr = get_bits(gb, bits)) == (1 << bits) - 1) sect_end += sect_len_incr; sect_end += sect_len_incr; if (get_bits_left(gb) < 0) { av_log(ac->avctx, AV_LOG_ERROR, overread_err); return -1; } if (sect_end > ics->max_sfb) { av_log(ac->avctx, AV_LOG_ERROR, "Number of bands (%d) exceeds limit (%d).\n", sect_end, ics->max_sfb); return -1; } for (; k < sect_end; k++) { band_type [idx] = sect_band_type; band_type_run_end[idx++] = sect_end; } } } return 0; }


static void unassign_storage(SCCB *sccb) { MemoryRegion *mr = NULL; AssignStorage *assign_info = (AssignStorage *) sccb; sclpMemoryHotplugDev *mhd = get_sclp_memory_hotplug_dev(); assert(mhd); ram_addr_t unassign_addr = (assign_info->rn - 1) * mhd->rzm; MemoryRegion *sysmem = get_system_memory(); /* if the addr is a multiple of 256 MB */ if ((unassign_addr % MEM_SECTION_SIZE == 0) && (unassign_addr >= mhd->padded_ram_size)) { mhd->standby_state_map[(unassign_addr - mhd->padded_ram_size) / MEM_SECTION_SIZE] = 0; /* find the specified memory region and destroy it */ mr = memory_region_find(sysmem, unassign_addr, 1).mr; if (mr) { int i; int is_removable = 1; ram_addr_t map_offset = (unassign_addr - mhd->padded_ram_size - (unassign_addr - mhd->padded_ram_size) % mhd->standby_subregion_size); /* Mark all affected subregions as 'standby' once again */ for (i = 0; i < (mhd->standby_subregion_size / MEM_SECTION_SIZE); i++) { if (mhd->standby_state_map[i + map_offset / MEM_SECTION_SIZE]) { is_removable = 0; break; } } if (is_removable) { memory_region_del_subregion(sysmem, mr); object_unparent(OBJECT(mr)); g_free(mr); } } } sccb->h.response_code = cpu_to_be16(SCLP_RC_NORMAL_COMPLETION); }


static int vpc_read(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, int nb_sectors) { BDRVVPCState *s = bs->opaque; int ret; int64_t offset; int64_t sectors, sectors_per_block; VHDFooter *footer = (VHDFooter *) s->footer_buf; if (cpu_to_be32(footer->type) == VHD_FIXED) { return bdrv_read(bs->file, sector_num, buf, nb_sectors); } while (nb_sectors > 0) { offset = get_sector_offset(bs, sector_num, 0); sectors_per_block = s->block_size >> BDRV_SECTOR_BITS; sectors = sectors_per_block - (sector_num % sectors_per_block); if (sectors > nb_sectors) { sectors = nb_sectors; } if (offset == -1) { memset(buf, 0, sectors * BDRV_SECTOR_SIZE); } else { ret = bdrv_pread(bs->file, offset, buf, sectors * BDRV_SECTOR_SIZE); if (ret != sectors * BDRV_SECTOR_SIZE) { return -1; } } nb_sectors -= sectors; sector_num += sectors; buf += sectors * BDRV_SECTOR_SIZE; } return 0; }


BlockDriverAIOCB *dma_bdrv_io( BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num, DMAIOFunc *io_func, BlockDriverCompletionFunc *cb, void *opaque, bool to_dev) { DMAAIOCB *dbs = qemu_aio_get(&dma_aio_pool, bs, cb, opaque); dbs->acb = NULL; dbs->bs = bs; dbs->sg = sg; dbs->sector_num = sector_num; dbs->sg_cur_index = 0; dbs->sg_cur_byte = 0; dbs->to_dev = to_dev; dbs->io_func = io_func; dbs->bh = NULL; qemu_iovec_init(&dbs->iov, sg->nsg); dma_bdrv_cb(dbs, 0); if (!dbs->acb) { qemu_aio_release(dbs); return NULL; } return &dbs->common; }


static int avr_probe(AVProbeData *p) { if (AV_RL32(p->buf) == MKTAG('2', 'B', 'I', 'T')) return AVPROBE_SCORE_EXTENSION; return 0; }


QList *qobject_to_qlist(const QObject *obj) { if (qobject_type(obj) != QTYPE_QLIST) { return NULL; } return container_of(obj, QList, base); }


static void *spapr_create_fdt_skel(const char *cpu_model, target_phys_addr_t rma_size, target_phys_addr_t initrd_base, target_phys_addr_t initrd_size, target_phys_addr_t kernel_size, const char *boot_device, const char *kernel_cmdline, long hash_shift) { void *fdt; CPUPPCState *env; uint64_t mem_reg_property[2]; uint32_t start_prop = cpu_to_be32(initrd_base); uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)}; char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk"; uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; int i; char *modelname; int smt = kvmppc_smt_threads(); unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), cpu_to_be32(0x0), cpu_to_be32(0x0), cpu_to_be32(0x0)}; char mem_name[32]; target_phys_addr_t node0_size, mem_start; #define _FDT(exp) \ do { \ int ret = (exp); \ if (ret < 0) { \ fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ #exp, fdt_strerror(ret)); \ exit(1); \ } \ } while (0) fdt = g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create(fdt, FDT_MAX_SIZE))); if (kernel_size) { _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); if (initrd_size) { _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); _FDT((fdt_finish_reservemap(fdt))); /* Root node */ _FDT((fdt_begin_node(fdt, ""))); _FDT((fdt_property_string(fdt, "device_type", "chrp"))); _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); /* /chosen */ _FDT((fdt_begin_node(fdt, "chosen"))); /* Set Form1_affinity */ _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); _FDT((fdt_property(fdt, "linux,initrd-start", &start_prop, sizeof(start_prop)))); _FDT((fdt_property(fdt, "linux,initrd-end", &end_prop, sizeof(end_prop)))); if (kernel_size) { uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), cpu_to_be64(kernel_size) }; _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); _FDT((fdt_end_node(fdt))); /* memory node(s) */ node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; if (rma_size > node0_size) { rma_size = node0_size; /* RMA */ mem_reg_property[0] = 0; mem_reg_property[1] = cpu_to_be64(rma_size); _FDT((fdt_begin_node(fdt, "memory@0"))); _FDT((fdt_property_string(fdt, "device_type", "memory"))); _FDT((fdt_property(fdt, "reg", mem_reg_property, sizeof(mem_reg_property)))); _FDT((fdt_property(fdt, "ibm,associativity", associativity, sizeof(associativity)))); _FDT((fdt_end_node(fdt))); /* RAM: Node 0 */ if (node0_size > rma_size) { mem_reg_property[0] = cpu_to_be64(rma_size); mem_reg_property[1] = cpu_to_be64(node0_size - rma_size); sprintf(mem_name, "memory@" TARGET_FMT_lx, rma_size); _FDT((fdt_begin_node(fdt, mem_name))); _FDT((fdt_property_string(fdt, "device_type", "memory"))); _FDT((fdt_property(fdt, "reg", mem_reg_property, sizeof(mem_reg_property)))); _FDT((fdt_property(fdt, "ibm,associativity", associativity, sizeof(associativity)))); _FDT((fdt_end_node(fdt))); /* RAM: Node 1 and beyond */ mem_start = node0_size; for (i = 1; i < nb_numa_nodes; i++) { mem_reg_property[0] = cpu_to_be64(mem_start); mem_reg_property[1] = cpu_to_be64(node_mem[i]); associativity[3] = associativity[4] = cpu_to_be32(i); sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); _FDT((fdt_begin_node(fdt, mem_name))); _FDT((fdt_property_string(fdt, "device_type", "memory"))); _FDT((fdt_property(fdt, "reg", mem_reg_property, sizeof(mem_reg_property)))); _FDT((fdt_property(fdt, "ibm,associativity", associativity, sizeof(associativity)))); _FDT((fdt_end_node(fdt))); mem_start += node_mem[i]; /* cpus */ _FDT((fdt_begin_node(fdt, "cpus"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); modelname = g_strdup(cpu_model); for (i = 0; i < strlen(modelname); i++) { modelname[i] = toupper(modelname[i]); /* This is needed during FDT finalization */ spapr->cpu_model = g_strdup(modelname); for (env = first_cpu; env != NULL; env = env->next_cpu) { int index = env->cpu_index; uint32_t servers_prop[smp_threads]; uint32_t gservers_prop[smp_threads * 2]; char *nodename; uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 0xffffffff, 0xffffffff}; uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; uint32_t page_sizes_prop[64]; size_t page_sizes_prop_size; if ((index % smt) != 0) { continue; if (asprintf(&nodename, "%s@%x", modelname, index) < 0) { fprintf(stderr, "Allocation failure\n"); exit(1); _FDT((fdt_begin_node(fdt, nodename))); free(nodename); _FDT((fdt_property_cell(fdt, "reg", index))); _FDT((fdt_property_string(fdt, "device_type", "cpu"))); _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); _FDT((fdt_property_cell(fdt, "dcache-block-size", env->dcache_line_size))); _FDT((fdt_property_cell(fdt, "icache-block-size", env->icache_line_size))); _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); _FDT((fdt_property(fdt, "ibm,pft-size", pft_size_prop, sizeof(pft_size_prop)))); _FDT((fdt_property_string(fdt, "status", "okay"))); _FDT((fdt_property(fdt, "64-bit", NULL, 0))); /* Build interrupt servers and gservers properties */ for (i = 0; i < smp_threads; i++) { servers_prop[i] = cpu_to_be32(index + i); /* Hack, direct the group queues back to cpu 0 */ gservers_prop[i*2] = cpu_to_be32(index + i); gservers_prop[i*2 + 1] = 0; _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", servers_prop, sizeof(servers_prop)))); _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", gservers_prop, sizeof(gservers_prop)))); if (env->mmu_model & POWERPC_MMU_1TSEG) { _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", segs, sizeof(segs)))); /* Advertise VMX/VSX (vector extensions) if available * 0 / no property == no vector extensions * 1 == VMX / Altivec available * 2 == VSX available */ if (env->insns_flags & PPC_ALTIVEC) { uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); /* Advertise DFP (Decimal Floating Point) if available * 0 / no property == no DFP * 1 == DFP available */ if (env->insns_flags2 & PPC2_DFP) { _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); _FDT((fdt_end_node(fdt))); g_free(modelname); _FDT((fdt_end_node(fdt))); /* RTAS */ _FDT((fdt_begin_node(fdt, "rtas"))); _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, sizeof(hypertas_prop)))); _FDT((fdt_property(fdt, "ibm,associativity-reference-points", refpoints, sizeof(refpoints)))); _FDT((fdt_end_node(fdt))); /* interrupt controller */ _FDT((fdt_begin_node(fdt, "interrupt-controller"))); _FDT((fdt_property_string(fdt, "device_type", "PowerPC-External-Interrupt-Presentation"))); _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", interrupt_server_ranges_prop, sizeof(interrupt_server_ranges_prop)))); _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); _FDT((fdt_end_node(fdt))); /* vdevice */ _FDT((fdt_begin_node(fdt, "vdevice"))); _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); _FDT((fdt_end_node(fdt))); _FDT((fdt_end_node(fdt))); /* close root node */ _FDT((fdt_finish(fdt))); return fdt;


void checkasm_check_jpeg2000dsp(void) { LOCAL_ALIGNED_32(uint8_t, ref, [BUF_SIZE*3]); LOCAL_ALIGNED_32(uint8_t, new, [BUF_SIZE*3]); Jpeg2000DSPContext h; ff_jpeg2000dsp_init(&h); if (check_func(h.mct_decode[FF_DWT53], "jpeg2000_rct_int")) check_mct(&ref[BUF_SIZE*0], &ref[BUF_SIZE*1], &ref[BUF_SIZE*2], &new[BUF_SIZE*0], &new[BUF_SIZE*1], &new[BUF_SIZE*2]); report("mct_decode"); }


static int skip_check(MpegEncContext *s, Picture *p, Picture *ref){ int x, y, plane; int score=0; int64_t score64=0; for(plane=0; plane<3; plane++){ const int stride= p->linesize[plane]; const int bw= plane ? 1 : 2; for(y=0; y<s->mb_height*bw; y++){ for(x=0; x<s->mb_width*bw; x++){ int v= s->dsp.frame_skip_cmp[1](s, p->data[plane] + 8*(x + y*stride), ref->data[plane] + 8*(x + y*stride), stride, 8); switch(s->avctx->frame_skip_exp){ case 0: score= FFMAX(score, v); break; case 1: score+= ABS(v);break; case 2: score+= v*v;break; case 3: score64+= ABS(v*v*(int64_t)v);break; case 4: score64+= v*v*(int64_t)(v*v);break; } } } } if(score) score64= score; if(score64 < s->avctx->frame_skip_threshold) return 1; if(score64 < ((s->avctx->frame_skip_factor * (int64_t)s->lambda)>>8)) return 1; return 0; }


static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int type) { target_phys_addr_t hash; target_ulong vsid; int ds, pr, target_page_bits; int ret, ret2; pr = msr_pr; ctx->eaddr = eaddr; #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { ppc_slb_t *slb; target_ulong pageaddr; int segment_bits; LOG_MMU("Check SLBs\n"); slb = slb_lookup(env, eaddr); if (!slb) { return -5; } if (slb->vsid & SLB_VSID_B) { vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; segment_bits = 40; } else { vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; segment_bits = 28; } target_page_bits = (slb->vsid & SLB_VSID_L) ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP) : (slb->vsid & SLB_VSID_KS)); ds = 0; ctx->nx = !!(slb->vsid & SLB_VSID_N); pageaddr = eaddr & ((1ULL << segment_bits) - (1ULL << target_page_bits)); if (slb->vsid & SLB_VSID_B) { hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits); } else { hash = vsid ^ (pageaddr >> target_page_bits); } /* Only 5 bits of the page index are used in the AVPN */ ctx->ptem = (slb->vsid & SLB_VSID_PTEM) | ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80)); } else #endif /* defined(TARGET_PPC64) */ { target_ulong sr, pgidx; sr = env->sr[eaddr >> 28]; ctx->key = (((sr & 0x20000000) && (pr != 0)) || ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; ds = sr & 0x80000000 ? 1 : 0; ctx->nx = sr & 0x10000000 ? 1 : 0; vsid = sr & 0x00FFFFFF; target_page_bits = TARGET_PAGE_BITS; LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx " ir=%d dr=%d pr=%d %d t=%d\n", eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, rw, type); pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits; hash = vsid ^ pgidx; ctx->ptem = (vsid << 7) | (pgidx >> 10); } LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid); ret = -1; if (!ds) { /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); ctx->hash[0] = hash; ctx->hash[1] = ~hash; /* Initialize real address with an invalid value */ ctx->raddr = (target_phys_addr_t)-1ULL; if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || env->mmu_model == POWERPC_MMU_SOFT_74xx)) { /* Software TLB search */ ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); } else { LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[0]); /* Primary table lookup */ ret = find_pte(env, ctx, 0, rw, type, target_page_bits); if (ret < 0) { /* Secondary table lookup */ if (eaddr != 0xEFFFFFFF) LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx " pg_addr=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[1]); ret2 = find_pte(env, ctx, 1, rw, type, target_page_bits); if (ret2 != -1) ret = ret2; } } #if defined (DUMP_PAGE_TABLES) if (qemu_log_enabled()) { target_phys_addr_t curaddr; uint32_t a0, a1, a2, a3; qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx "\n", sdr, mask + 0x80); for (curaddr = sdr; curaddr < (sdr + mask + 0x80); curaddr += 16) { a0 = ldl_phys(curaddr); a1 = ldl_phys(curaddr + 4); a2 = ldl_phys(curaddr + 8); a3 = ldl_phys(curaddr + 12); if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n", curaddr, a0, a1, a2, a3); } } } #endif } else { LOG_MMU("No access allowed\n"); ret = -3; } } else { LOG_MMU("direct store...\n"); /* Direct-store segment : absolutely *BUGGY* for now */ switch (type) { case ACCESS_INT: /* Integer load/store : only access allowed */ break; case ACCESS_CODE: /* No code fetch is allowed in direct-store areas */ return -4; case ACCESS_FLOAT: /* Floating point load/store */ return -4; case ACCESS_RES: /* lwarx, ldarx or srwcx. */ return -4; case ACCESS_CACHE: /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ /* Should make the instruction do no-op. * As it already do no-op, it's quite easy :-) */ ctx->raddr = eaddr; return 0; case ACCESS_EXT: /* eciwx or ecowx */ return -4; default: qemu_log("ERROR: instruction should not need " "address translation\n"); return -4; } if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { ctx->raddr = eaddr; ret = 2; } else { ret = -2; } } return ret; }


static always_inline void gen_op_subfco (void) { gen_op_move_T2_T0(); gen_op_subf(); gen_op_check_subfc(); gen_op_check_subfo(); }


static void ivshmem_read(void *opaque, const uint8_t *buf, int size) { IVShmemState *s = opaque; int incoming_fd, tmp_fd; int guest_max_eventfd; long incoming_posn; if (fifo8_is_empty(&s->incoming_fifo) && size == sizeof(incoming_posn)) { memcpy(&incoming_posn, buf, size); } else { const uint8_t *p; uint32_t num; IVSHMEM_DPRINTF("short read of %d bytes\n", size); num = MAX(size, sizeof(long) - fifo8_num_used(&s->incoming_fifo)); fifo8_push_all(&s->incoming_fifo, buf, num); if (fifo8_num_used(&s->incoming_fifo) < sizeof(incoming_posn)) { return; } size -= num; buf += num; p = fifo8_pop_buf(&s->incoming_fifo, sizeof(incoming_posn), &num); g_assert(num == sizeof(incoming_posn)); memcpy(&incoming_posn, p, sizeof(incoming_posn)); if (size > 0) { fifo8_push_all(&s->incoming_fifo, buf, size); } } if (incoming_posn < -1) { IVSHMEM_DPRINTF("invalid incoming_posn %ld\n", incoming_posn); return; } /* pick off s->server_chr->msgfd and store it, posn should accompany msg */ tmp_fd = qemu_chr_fe_get_msgfd(s->server_chr); IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd); /* make sure we have enough space for this guest */ if (incoming_posn >= s->nb_peers) { if (increase_dynamic_storage(s, incoming_posn) < 0) { error_report("increase_dynamic_storage() failed"); if (tmp_fd != -1) { } return; } } if (tmp_fd == -1) { /* if posn is positive and unseen before then this is our posn*/ if ((incoming_posn >= 0) && (s->peers[incoming_posn].eventfds == NULL)) { /* receive our posn */ s->vm_id = incoming_posn; return; } else { /* otherwise an fd == -1 means an existing guest has gone away */ IVSHMEM_DPRINTF("posn %ld has gone away\n", incoming_posn); close_guest_eventfds(s, incoming_posn); return; } } /* because of the implementation of get_msgfd, we need a dup */ incoming_fd = dup(tmp_fd); if (incoming_fd == -1) { fprintf(stderr, "could not allocate file descriptor %s\n", strerror(errno)); return; } /* if the position is -1, then it's shared memory region fd */ if (incoming_posn == -1) { void * map_ptr; s->max_peer = 0; if (check_shm_size(s, incoming_fd) == -1) { exit(-1); } /* mmap the region and map into the BAR2 */ map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, incoming_fd, 0); memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", s->ivshmem_size, map_ptr); vmstate_register_ram(&s->ivshmem, DEVICE(s)); IVSHMEM_DPRINTF("guest h/w addr = %p, size = %" PRIu64 "\n", map_ptr, s->ivshmem_size); memory_region_add_subregion(&s->bar, 0, &s->ivshmem); /* only store the fd if it is successfully mapped */ s->shm_fd = incoming_fd; return; } /* each guest has an array of eventfds, and we keep track of how many * guests for each VM */ guest_max_eventfd = s->peers[incoming_posn].nb_eventfds; if (guest_max_eventfd == 0) { /* one eventfd per MSI vector */ s->peers[incoming_posn].eventfds = g_new(EventNotifier, s->vectors); } /* this is an eventfd for a particular guest VM */ IVSHMEM_DPRINTF("eventfds[%ld][%d] = %d\n", incoming_posn, guest_max_eventfd, incoming_fd); event_notifier_init_fd(&s->peers[incoming_posn].eventfds[guest_max_eventfd], incoming_fd); /* increment count for particular guest */ s->peers[incoming_posn].nb_eventfds++; /* keep track of the maximum VM ID */ if (incoming_posn > s->max_peer) { s->max_peer = incoming_posn; } if (incoming_posn == s->vm_id) { s->eventfd_chr[guest_max_eventfd] = create_eventfd_chr_device(s, &s->peers[s->vm_id].eventfds[guest_max_eventfd], guest_max_eventfd); } if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { ivshmem_add_eventfd(s, incoming_posn, guest_max_eventfd); } }


static void kvm_s390_flic_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); S390FLICStateClass *fsc = S390_FLIC_COMMON_CLASS(oc); dc->realize = kvm_s390_flic_realize; dc->vmsd = &kvm_s390_flic_vmstate; dc->reset = kvm_s390_flic_reset; fsc->register_io_adapter = kvm_s390_register_io_adapter; fsc->io_adapter_map = kvm_s390_io_adapter_map; fsc->add_adapter_routes = kvm_s390_add_adapter_routes; fsc->release_adapter_routes = kvm_s390_release_adapter_routes; fsc->clear_io_irq = kvm_s390_clear_io_flic; }


static bool machine_get_kernel_irqchip(Object *obj, Error **errp) { MachineState *ms = MACHINE(obj); return ms->kernel_irqchip; }


void bdrv_init_with_whitelist(void) { use_bdrv_whitelist = 1; bdrv_init(); }


static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2, int insn, int rd) { TCGv val1 = gen_load_gpr(dc, rd); TCGv dst = gen_dest_gpr(dc, rd); TCGv_i32 r_asi = gen_get_asi(dc, insn); gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); tcg_temp_free_i32(r_asi); gen_store_gpr(dc, rd, dst); }


static void rng_random_finalize(Object *obj) { RndRandom *s = RNG_RANDOM(obj); qemu_set_fd_handler(s->fd, NULL, NULL, NULL); if (s->fd != -1) { qemu_close(s->fd); } g_free(s->filename); }


static void blend_image_rgb(AVFilterContext *ctx, AVFrame *dst, const AVFrame *src, int x, int y) { blend_image_packed_rgb(ctx, dst, src, 0, x, y, 0); }


static int update_frame_pool(AVCodecContext *avctx, AVFrame *frame) { FramePool *pool = avctx->internal->pool; int i, ret; switch (avctx->codec_type) { case AVMEDIA_TYPE_VIDEO: { uint8_t *data[4]; int linesize[4]; int size[4] = { 0 }; int w = frame->width; int h = frame->height; int tmpsize, unaligned; if (pool->format == frame->format && pool->width == frame->width && pool->height == frame->height) return 0; avcodec_align_dimensions2(avctx, &w, &h, pool->stride_align); do { // NOTE: do not align linesizes individually, this breaks e.g. assumptions // that linesize[0] == 2*linesize[1] in the MPEG-encoder for 4:2:2 av_image_fill_linesizes(linesize, avctx->pix_fmt, w); // increase alignment of w for next try (rhs gives the lowest bit set in w) w += w & ~(w - 1); unaligned = 0; for (i = 0; i < 4; i++) unaligned |= linesize[i] % pool->stride_align[i]; } while (unaligned); tmpsize = av_image_fill_pointers(data, avctx->pix_fmt, h, NULL, linesize); if (tmpsize < 0) return -1; for (i = 0; i < 3 && data[i + 1]; i++) size[i] = data[i + 1] - data[i]; size[i] = tmpsize - (data[i] - data[0]); for (i = 0; i < 4; i++) { av_buffer_pool_uninit(&pool->pools[i]); pool->linesize[i] = linesize[i]; if (size[i]) { pool->pools[i] = av_buffer_pool_init(size[i] + 16 + STRIDE_ALIGN - 1, CONFIG_MEMORY_POISONING ? NULL : av_buffer_allocz); if (!pool->pools[i]) { ret = AVERROR(ENOMEM); goto fail; } } } pool->format = frame->format; pool->width = frame->width; pool->height = frame->height; break; } case AVMEDIA_TYPE_AUDIO: { int ch = av_frame_get_channels(frame); //av_get_channel_layout_nb_channels(frame->channel_layout); int planar = av_sample_fmt_is_planar(frame->format); int planes = planar ? ch : 1; if (pool->format == frame->format && pool->planes == planes && pool->channels == ch && frame->nb_samples == pool->samples) return 0; av_buffer_pool_uninit(&pool->pools[0]); ret = av_samples_get_buffer_size(&pool->linesize[0], ch, frame->nb_samples, frame->format, 0); if (ret < 0) goto fail; pool->pools[0] = av_buffer_pool_init(pool->linesize[0], NULL); if (!pool->pools[0]) { ret = AVERROR(ENOMEM); goto fail; } pool->format = frame->format; pool->planes = planes; pool->channels = ch; pool->samples = frame->nb_samples; break; } default: av_assert0(0); } return 0; fail: for (i = 0; i < 4; i++) av_buffer_pool_uninit(&pool->pools[i]); pool->format = -1; pool->planes = pool->channels = pool->samples = 0; pool->width = pool->height = 0; return ret; }


int vring_pop(VirtIODevice *vdev, Vring *vring, VirtQueueElement *elem) { struct vring_desc desc; unsigned int i, head, found = 0, num = vring->vr.num; uint16_t avail_idx, last_avail_idx; int ret; /* Initialize elem so it can be safely unmapped */ elem->in_num = elem->out_num = 0; /* If there was a fatal error then refuse operation */ if (vring->broken) { ret = -EFAULT; goto out; } /* Check it isn't doing very strange things with descriptor numbers. */ last_avail_idx = vring->last_avail_idx; avail_idx = vring_get_avail_idx(vdev, vring); barrier(); /* load indices now and not again later */ if (unlikely((uint16_t)(avail_idx - last_avail_idx) > num)) { error_report("Guest moved used index from %u to %u", last_avail_idx, avail_idx); ret = -EFAULT; goto out; } /* If there's nothing new since last we looked. */ if (avail_idx == last_avail_idx) { ret = -EAGAIN; goto out; } /* Only get avail ring entries after they have been exposed by guest. */ smp_rmb(); /* Grab the next descriptor number they're advertising, and increment * the index we've seen. */ head = vring_get_avail_ring(vdev, vring, last_avail_idx % num); elem->index = head; /* If their number is silly, that's an error. */ if (unlikely(head >= num)) { error_report("Guest says index %u > %u is available", head, num); ret = -EFAULT; goto out; } i = head; do { if (unlikely(i >= num)) { error_report("Desc index is %u > %u, head = %u", i, num, head); ret = -EFAULT; goto out; } if (unlikely(++found > num)) { error_report("Loop detected: last one at %u vq size %u head %u", i, num, head); ret = -EFAULT; goto out; } copy_in_vring_desc(vdev, &vring->vr.desc[i], &desc); /* Ensure descriptor is loaded before accessing fields */ barrier(); if (desc.flags & VRING_DESC_F_INDIRECT) { ret = get_indirect(vdev, vring, elem, &desc); if (ret < 0) { goto out; } continue; } ret = get_desc(vring, elem, &desc); if (ret < 0) { goto out; } i = desc.next; } while (desc.flags & VRING_DESC_F_NEXT); /* On success, increment avail index. */ vring->last_avail_idx++; if (virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) { vring_avail_event(&vring->vr) = virtio_tswap16(vdev, vring->last_avail_idx); } return head; out: assert(ret < 0); if (ret == -EFAULT) { vring->broken = true; } vring_unmap_element(elem); return ret; }


static void cpu_ppc_hdecr_cb(void *opaque) { PowerPCCPU *cpu = opaque; _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1); }


void qemu_system_killed(int signal, pid_t pid) { shutdown_signal = signal; shutdown_pid = pid; no_shutdown = 0; qemu_system_shutdown_request(); }


static void gen_spr_405 (CPUPPCState *env) { spr_register(env, SPR_4xx_CCR0, "CCR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00700000); /* Debug */ /* XXX : not implemented */ spr_register(env, SPR_405_DBCR1, "DBCR1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_DVC1, "DVC1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_DVC2, "DVC2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_IAC3, "IAC3", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_IAC4, "IAC4", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Storage control */ spr_register(env, SPR_405_SLER, "SLER", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_40x_sler, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_SU0R, "SU0R", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* SPRG */ spr_register(env, SPR_USPRG0, "USPRG0", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); spr_register(env, SPR_SPRG4, "SPRG4", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_USPRG4, "USPRG4", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); spr_register(env, SPR_SPRG5, "SPRG5", SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_USPRG5, "USPRG5", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); spr_register(env, SPR_SPRG6, "SPRG6", SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_USPRG6, "USPRG6", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); spr_register(env, SPR_SPRG7, "SPRG7", SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_USPRG7, "USPRG7", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); }


static void realtime_init(void) { if (enable_mlock) { if (os_mlock() < 0) { fprintf(stderr, "qemu: locking memory failed\n"); exit(1); } } }


int net_init_hubport(const NetClientOptions *opts, const char *name, NetClientState *peer, Error **errp) { const NetdevHubPortOptions *hubport; assert(opts->type == NET_CLIENT_OPTIONS_KIND_HUBPORT); assert(!peer); hubport = opts->u.hubport; net_hub_add_port(hubport->hubid, name); return 0; }


static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { uint32_t tmp; bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; if (old_spsel != new_spsel) { tmp = env->v7m.other_sp; env->v7m.other_sp = env->regs[13]; env->regs[13] = tmp; env->v7m.control = deposit32(env->v7m.control, R_V7M_CONTROL_SPSEL_SHIFT, R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); } }


void qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id) { QXLCursor *cursor; fprintf(stderr, ": %s", qxl_name(qxl_cursor_cmd, cmd->type)); switch (cmd->type) { case QXL_CURSOR_SET: fprintf(stderr, " +%d+%d visible %s, shape @ 0x%" PRIx64, cmd->u.set.position.x, cmd->u.set.position.y, cmd->u.set.visible ? "yes" : "no", cmd->u.set.shape); cursor = qxl_phys2virt(qxl, cmd->u.set.shape, group_id); fprintf(stderr, " type %s size %dx%d hot-spot +%d+%d" " unique 0x%" PRIx64 " data-size %d", qxl_name(spice_cursor_type, cursor->header.type), cursor->header.width, cursor->header.height, cursor->header.hot_spot_x, cursor->header.hot_spot_y, cursor->header.unique, cursor->data_size); break; case QXL_CURSOR_MOVE: fprintf(stderr, " +%d+%d", cmd->u.position.x, cmd->u.position.y); break; } }


static void filter_mb(VP8Context *s, uint8_t *dst[3], VP8Macroblock *mb, int mb_x, int mb_y) { int filter_level, inner_limit, hev_thresh, mbedge_lim, bedge_lim; filter_level_for_mb(s, mb, &filter_level, &inner_limit, &hev_thresh); if (!filter_level) return; mbedge_lim = 2*(filter_level+2) + inner_limit; bedge_lim = 2* filter_level + inner_limit; if (mb_x) { s->vp8dsp.vp8_h_loop_filter16(dst[0], s->linesize, mbedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter8 (dst[1], s->uvlinesize, mbedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter8 (dst[2], s->uvlinesize, mbedge_lim, inner_limit, hev_thresh); } if (!mb->skip || mb->mode == MODE_I4x4 || mb->mode == VP8_MVMODE_SPLIT) { s->vp8dsp.vp8_h_loop_filter16_inner(dst[0]+ 4, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter16_inner(dst[0]+ 8, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter16_inner(dst[0]+12, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter8_inner (dst[1]+ 4, s->uvlinesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_h_loop_filter8_inner (dst[2]+ 4, s->uvlinesize, bedge_lim, inner_limit, hev_thresh); } if (mb_y) { s->vp8dsp.vp8_v_loop_filter16(dst[0], s->linesize, mbedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter8 (dst[1], s->uvlinesize, mbedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter8 (dst[2], s->uvlinesize, mbedge_lim, inner_limit, hev_thresh); } if (!mb->skip || mb->mode == MODE_I4x4 || mb->mode == VP8_MVMODE_SPLIT) { s->vp8dsp.vp8_v_loop_filter16_inner(dst[0]+ 4*s->linesize, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter16_inner(dst[0]+ 8*s->linesize, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter16_inner(dst[0]+12*s->linesize, s->linesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter8_inner (dst[1]+ 4*s->uvlinesize, s->uvlinesize, bedge_lim, inner_limit, hev_thresh); s->vp8dsp.vp8_v_loop_filter8_inner (dst[2]+ 4*s->uvlinesize, s->uvlinesize, bedge_lim, inner_limit, hev_thresh); } }


static uint64_t memcard_read(void *opaque, target_phys_addr_t addr, unsigned size) { MilkymistMemcardState *s = opaque; uint32_t r = 0; addr >>= 2; switch (addr) { case R_CMD: if (!s->enabled) { r = 0xff; } else { r = s->response[s->response_read_ptr++]; if (s->response_read_ptr > s->response_len) { error_report("milkymist_memcard: " "read more cmd bytes than available. Clipping."); s->response_read_ptr = 0; } } break; case R_DAT: if (!s->enabled) { r = 0xffffffff; } else { r = 0; r |= sd_read_data(s->card) << 24; r |= sd_read_data(s->card) << 16; r |= sd_read_data(s->card) << 8; r |= sd_read_data(s->card); } break; case R_CLK2XDIV: case R_ENABLE: case R_PENDING: case R_START: r = s->regs[addr]; break; default: error_report("milkymist_memcard: read access to unknown register 0x" TARGET_FMT_plx, addr << 2); break; } trace_milkymist_memcard_memory_read(addr << 2, r); return r; }


START_TEST(qstring_get_str_test) { QString *qstring; const char *ret_str; const char *str = "QEMU/KVM"; qstring = qstring_from_str(str); ret_str = qstring_get_str(qstring); fail_unless(strcmp(ret_str, str) == 0); QDECREF(qstring); }


static inline void set_bit(uint32_t *field, int bit) { field[bit >> 5] |= 1 << (bit & 0x1F); }


static int vdi_co_read(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, int nb_sectors) { BDRVVdiState *s = bs->opaque; uint32_t bmap_entry; uint32_t block_index; uint32_t sector_in_block; uint32_t n_sectors; int ret; logout("\n"); restart: block_index = sector_num / s->block_sectors; sector_in_block = sector_num % s->block_sectors; n_sectors = s->block_sectors - sector_in_block; if (n_sectors > nb_sectors) { n_sectors = nb_sectors; } logout("will read %u sectors starting at sector %" PRIu64 "\n", n_sectors, sector_num); /* prepare next AIO request */ bmap_entry = le32_to_cpu(s->bmap[block_index]); if (!VDI_IS_ALLOCATED(bmap_entry)) { /* Block not allocated, return zeros, no need to wait. */ memset(buf, 0, n_sectors * SECTOR_SIZE); ret = 0; } else { uint64_t offset = s->header.offset_data / SECTOR_SIZE + (uint64_t)bmap_entry * s->block_sectors + sector_in_block; ret = bdrv_read(bs->file, offset, buf, n_sectors); } logout("%u sectors read\n", n_sectors); nb_sectors -= n_sectors; sector_num += n_sectors; buf += n_sectors * SECTOR_SIZE; if (ret >= 0 && nb_sectors > 0) { goto restart; } return ret; }


static void hmp_cont_cb(void *opaque, int err) { Monitor *mon = opaque; if (!err) { hmp_cont(mon, NULL); } }


static int64_t buffered_get_rate_limit(void *opaque) { QEMUFileBuffered *s = opaque; return s->xfer_limit; }


static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr, uint64_t asc, uint64_t st_entry, target_ulong *raddr, int *flags, int rw) { CPUState *cs = CPU(s390_env_get_cpu(env)); uint64_t origin, offs, pt_entry; if (st_entry & _SEGMENT_ENTRY_RO) { *flags &= ~PAGE_WRITE; } if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) { /* Decode EDAT1 segment frame absolute address (1MB page) */ *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff); PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry); return 0; } /* Look up 4KB page entry */ origin = st_entry & _SEGMENT_ENTRY_ORIGIN; offs = (vaddr & VADDR_PX) >> 9; pt_entry = ldq_phys(cs->as, origin + offs); PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", __func__, origin, offs, pt_entry); return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw); }


static int64_t coroutine_fn bdrv_co_get_block_status_above(BlockDriverState *bs, BlockDriverState *base, int64_t sector_num, int nb_sectors, int *pnum, BlockDriverState **file) { BlockDriverState *p; int64_t ret = 0; bool first = true; assert(bs != base); for (p = bs; p != base; p = backing_bs(p)) { ret = bdrv_co_get_block_status(p, sector_num, nb_sectors, pnum, file); if (ret < 0) { break; } if (ret & BDRV_BLOCK_ZERO && ret & BDRV_BLOCK_EOF && !first) { /* * Reading beyond the end of the file continues to read * zeroes, but we can only widen the result to the * unallocated length we learned from an earlier * iteration. */ *pnum = nb_sectors; } if (ret & (BDRV_BLOCK_ZERO | BDRV_BLOCK_DATA)) { break; } /* [sector_num, pnum] unallocated on this layer, which could be only * the first part of [sector_num, nb_sectors]. */ nb_sectors = MIN(nb_sectors, *pnum); first = false; } return ret; }


static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) { OpenPICState *opp = opaque; uint32_t retval; int idx; DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); retval = 0xFFFFFFFF; if (addr & 0xF) { return retval; } addr = addr & 0xFFF0; idx = addr >> 5; if (addr & 0x10) { /* EXDE / IFEDE / IEEDE */ retval = read_IRQreg_idr(opp, idx); } else { /* EXVP / IFEVP / IEEVP */ retval = read_IRQreg_ivpr(opp, idx); } DPRINTF("%s: => 0x%08x\n", __func__, retval); return retval; }


static CharDriverState *chr_baum_init(const char *id, ChardevBackend *backend, ChardevReturn *ret, Error **errp) { BaumDriverState *baum; CharDriverState *chr; brlapi_handle_t *handle; #if defined(CONFIG_SDL) #if SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) SDL_SysWMinfo info; #endif #endif int tty; baum = g_malloc0(sizeof(BaumDriverState)); baum->chr = chr = qemu_chr_alloc(); chr->opaque = baum; chr->chr_write = baum_write; chr->chr_accept_input = baum_accept_input; chr->chr_close = baum_close; handle = g_malloc0(brlapi_getHandleSize()); baum->brlapi = handle; baum->brlapi_fd = brlapi__openConnection(handle, NULL, NULL); if (baum->brlapi_fd == -1) { error_setg(errp, "brlapi__openConnection: %s", brlapi_strerror(brlapi_error_location())); goto fail_handle; } baum->cellCount_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, baum_cellCount_timer_cb, baum); if (brlapi__getDisplaySize(handle, &baum->x, &baum->y) == -1) { error_setg(errp, "brlapi__getDisplaySize: %s", brlapi_strerror(brlapi_error_location())); goto fail; } #if defined(CONFIG_SDL) #if SDL_COMPILEDVERSION < SDL_VERSIONNUM(2, 0, 0) memset(&info, 0, sizeof(info)); SDL_VERSION(&info.version); if (SDL_GetWMInfo(&info)) tty = info.info.x11.wmwindow; else #endif #endif tty = BRLAPI_TTY_DEFAULT; if (brlapi__enterTtyMode(handle, tty, NULL) == -1) { error_setg(errp, "brlapi__enterTtyMode: %s", brlapi_strerror(brlapi_error_location())); goto fail; } qemu_set_fd_handler(baum->brlapi_fd, baum_chr_read, NULL, baum); return chr; fail: timer_free(baum->cellCount_timer); brlapi__closeConnection(handle); fail_handle: g_free(handle); g_free(chr); g_free(baum); return NULL; }


QemuOpts *qemu_opts_create(QemuOptsList *list, const char *id, int fail_if_exists) { QemuOpts *opts = NULL; if (id) { if (!id_wellformed(id)) { qerror_report(QERR_INVALID_PARAMETER_VALUE, "id", "an identifier"); error_printf_unless_qmp("Identifiers consist of letters, digits, '-', '.', '_', starting with a letter.\n"); return NULL; } opts = qemu_opts_find(list, id); if (opts != NULL) { if (fail_if_exists && !list->merge_lists) { qerror_report(QERR_DUPLICATE_ID, id, list->name); return NULL; } else { return opts; } } } else if (list->merge_lists) { opts = qemu_opts_find(list, NULL); if (opts) { return opts; } } opts = g_malloc0(sizeof(*opts)); if (id) { opts->id = g_strdup(id); } opts->list = list; loc_save(&opts->loc); QTAILQ_INIT(&opts->head); QTAILQ_INSERT_TAIL(&list->head, opts, next); return opts; }


static int yuv4_read_header(AVFormatContext *s) { char header[MAX_YUV4_HEADER + 10]; // Include headroom for // the longest option char *tokstart, *tokend, *header_end; int i; AVIOContext *pb = s->pb; int width = -1, height = -1, raten = 0, rated = 0, aspectn = 0, aspectd = 0; enum AVPixelFormat pix_fmt = AV_PIX_FMT_NONE, alt_pix_fmt = AV_PIX_FMT_NONE; enum AVChromaLocation chroma_sample_location = AVCHROMA_LOC_UNSPECIFIED; AVStream *st; enum AVFieldOrder field_order; for (i = 0; i < MAX_YUV4_HEADER; i++) { header[i] = avio_r8(pb); if (header[i] == '\n') { header[i + 1] = 0x20; // Add a space after last option. // Makes parsing "444" vs "444alpha" easier. header[i + 2] = 0; break; } } if (i == MAX_YUV4_HEADER) return -1; if (strncmp(header, Y4M_MAGIC, strlen(Y4M_MAGIC))) return -1; header_end = &header[i + 1]; // Include space for (tokstart = &header[strlen(Y4M_MAGIC) + 1]; tokstart < header_end; tokstart++) { if (*tokstart == 0x20) continue; switch (*tokstart++) { case 'W': // Width. Required. width = strtol(tokstart, &tokend, 10); tokstart = tokend; break; case 'H': // Height. Required. height = strtol(tokstart, &tokend, 10); tokstart = tokend; break; case 'C': // Color space if (strncmp("420jpeg", tokstart, 7) == 0) { pix_fmt = AV_PIX_FMT_YUV420P; chroma_sample_location = AVCHROMA_LOC_CENTER; } else if (strncmp("420mpeg2", tokstart, 8) == 0) { pix_fmt = AV_PIX_FMT_YUV420P; chroma_sample_location = AVCHROMA_LOC_LEFT; } else if (strncmp("420paldv", tokstart, 8) == 0) { pix_fmt = AV_PIX_FMT_YUV420P; chroma_sample_location = AVCHROMA_LOC_TOPLEFT; } else if (strncmp("420p16", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV420P16; } else if (strncmp("422p16", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV422P16; } else if (strncmp("444p16", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV444P16; } else if (strncmp("420p14", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV420P14; } else if (strncmp("422p14", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV422P14; } else if (strncmp("444p14", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV444P14; } else if (strncmp("420p12", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV420P12; } else if (strncmp("422p12", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV422P12; } else if (strncmp("444p12", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV444P12; } else if (strncmp("420p10", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV420P10; } else if (strncmp("422p10", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV422P10; } else if (strncmp("444p10", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_YUV444P10; } else if (strncmp("420p9", tokstart, 5) == 0) { pix_fmt = AV_PIX_FMT_YUV420P9; } else if (strncmp("422p9", tokstart, 5) == 0) { pix_fmt = AV_PIX_FMT_YUV422P9; } else if (strncmp("444p9", tokstart, 5) == 0) { pix_fmt = AV_PIX_FMT_YUV444P9; } else if (strncmp("420", tokstart, 3) == 0) { pix_fmt = AV_PIX_FMT_YUV420P; chroma_sample_location = AVCHROMA_LOC_CENTER; } else if (strncmp("411", tokstart, 3) == 0) { pix_fmt = AV_PIX_FMT_YUV411P; } else if (strncmp("422", tokstart, 3) == 0) { pix_fmt = AV_PIX_FMT_YUV422P; } else if (strncmp("444alpha", tokstart, 8) == 0 ) { av_log(s, AV_LOG_ERROR, "Cannot handle 4:4:4:4 " "YUV4MPEG stream.\n"); return -1; } else if (strncmp("444", tokstart, 3) == 0) { pix_fmt = AV_PIX_FMT_YUV444P; } else if (strncmp("mono16", tokstart, 6) == 0) { pix_fmt = AV_PIX_FMT_GRAY16; } else if (strncmp("mono", tokstart, 4) == 0) { pix_fmt = AV_PIX_FMT_GRAY8; } else { av_log(s, AV_LOG_ERROR, "YUV4MPEG stream contains an unknown " "pixel format.\n"); return -1; } while (tokstart < header_end && *tokstart != 0x20) tokstart++; break; case 'I': // Interlace type switch (*tokstart++){ case '?': field_order = AV_FIELD_UNKNOWN; break; case 'p': field_order = AV_FIELD_PROGRESSIVE; break; case 't': field_order = AV_FIELD_TT; break; case 'b': field_order = AV_FIELD_BB; break; case 'm': av_log(s, AV_LOG_ERROR, "YUV4MPEG stream contains mixed " "interlaced and non-interlaced frames.\n"); default: av_log(s, AV_LOG_ERROR, "YUV4MPEG has invalid header.\n"); return AVERROR(EINVAL); } break; case 'F': // Frame rate sscanf(tokstart, "%d:%d", &raten, &rated); // 0:0 if unknown while (tokstart < header_end && *tokstart != 0x20) tokstart++; break; case 'A': // Pixel aspect sscanf(tokstart, "%d:%d", &aspectn, &aspectd); // 0:0 if unknown while (tokstart < header_end && *tokstart != 0x20) tokstart++; break; case 'X': // Vendor extensions if (strncmp("YSCSS=", tokstart, 6) == 0) { // Older nonstandard pixel format representation tokstart += 6; if (strncmp("420JPEG", tokstart, 7) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P; else if (strncmp("420MPEG2", tokstart, 8) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P; else if (strncmp("420PALDV", tokstart, 8) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P; else if (strncmp("420P9", tokstart, 5) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P9; else if (strncmp("422P9", tokstart, 5) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P9; else if (strncmp("444P9", tokstart, 5) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P9; else if (strncmp("420P10", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P10; else if (strncmp("422P10", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P10; else if (strncmp("444P10", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P10; else if (strncmp("420P12", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P12; else if (strncmp("422P12", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P12; else if (strncmp("444P12", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P12; else if (strncmp("420P14", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P14; else if (strncmp("422P14", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P14; else if (strncmp("444P14", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P14; else if (strncmp("420P16", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV420P16; else if (strncmp("422P16", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P16; else if (strncmp("444P16", tokstart, 6) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P16; else if (strncmp("411", tokstart, 3) == 0) alt_pix_fmt = AV_PIX_FMT_YUV411P; else if (strncmp("422", tokstart, 3) == 0) alt_pix_fmt = AV_PIX_FMT_YUV422P; else if (strncmp("444", tokstart, 3) == 0) alt_pix_fmt = AV_PIX_FMT_YUV444P; } while (tokstart < header_end && *tokstart != 0x20) tokstart++; break; } } if (width == -1 || height == -1) { av_log(s, AV_LOG_ERROR, "YUV4MPEG has invalid header.\n"); return -1; } if (pix_fmt == AV_PIX_FMT_NONE) { if (alt_pix_fmt == AV_PIX_FMT_NONE) pix_fmt = AV_PIX_FMT_YUV420P; else pix_fmt = alt_pix_fmt; } if (raten <= 0 || rated <= 0) { // Frame rate unknown raten = 25; rated = 1; } if (aspectn == 0 && aspectd == 0) { // Pixel aspect unknown aspectd = 1; } st = avformat_new_stream(s, NULL); if (!st) return AVERROR(ENOMEM); st->codec->width = width; st->codec->height = height; av_reduce(&raten, &rated, raten, rated, (1UL << 31) - 1); avpriv_set_pts_info(st, 64, rated, raten); st->avg_frame_rate = av_inv_q(st->time_base); st->codec->pix_fmt = pix_fmt; st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = AV_CODEC_ID_RAWVIDEO; st->sample_aspect_ratio = (AVRational){ aspectn, aspectd }; st->codec->chroma_sample_location = chroma_sample_location; st->codec->field_order = field_order; return 0; }


static uint64_t uart_read(void *opaque, target_phys_addr_t offset, unsigned size) { UartState *s = (UartState *)opaque; uint32_t c = 0; offset >>= 2; if (offset > R_MAX) { return 0; } else if (offset == R_TX_RX) { uart_read_rx_fifo(s, &c); return c; } return s->r[offset]; }


static av_cold void alloc_temp(HYuvContext *s) { int i; if (s->bitstream_bpp<24) { for (i=0; i<3; i++) { s->temp[i]= av_malloc(s->width + 16); } } else { s->temp[0]= av_mallocz(4*s->width + 16); } }


static int r3d_read_red1(AVFormatContext *s) { AVStream *st = avformat_new_stream(s, NULL); char filename[258]; int tmp; int av_unused tmp2; AVRational framerate; if (!st) return AVERROR(ENOMEM); st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = CODEC_ID_JPEG2000; tmp = avio_r8(s->pb); // major version tmp2 = avio_r8(s->pb); // minor version av_dlog(s, "version %d.%d\n", tmp, tmp2); tmp = avio_rb16(s->pb); // unknown av_dlog(s, "unknown1 %d\n", tmp); tmp = avio_rb32(s->pb); avpriv_set_pts_info(st, 32, 1, tmp); tmp = avio_rb32(s->pb); // filenum av_dlog(s, "filenum %d\n", tmp); avio_skip(s->pb, 32); // unknown st->codec->width = avio_rb32(s->pb); st->codec->height = avio_rb32(s->pb); tmp = avio_rb16(s->pb); // unknown av_dlog(s, "unknown2 %d\n", tmp); framerate.num = avio_rb16(s->pb); framerate.den = avio_rb16(s->pb); if (framerate.num && framerate.den) st->r_frame_rate = st->avg_frame_rate = framerate; tmp = avio_r8(s->pb); // audio channels av_dlog(s, "audio channels %d\n", tmp); if (tmp > 0) { AVStream *ast = avformat_new_stream(s, NULL); if (!ast) return AVERROR(ENOMEM); ast->codec->codec_type = AVMEDIA_TYPE_AUDIO; ast->codec->codec_id = CODEC_ID_PCM_S32BE; ast->codec->channels = tmp; avpriv_set_pts_info(ast, 32, 1, st->time_base.den); } avio_read(s->pb, filename, 257); filename[sizeof(filename)-1] = 0; av_dict_set(&st->metadata, "filename", filename, 0); av_dlog(s, "filename %s\n", filename); av_dlog(s, "resolution %dx%d\n", st->codec->width, st->codec->height); av_dlog(s, "timescale %d\n", st->time_base.den); av_dlog(s, "frame rate %d/%d\n", framerate.num, framerate.den); return 0; }


unsigned int avpriv_toupper4(unsigned int x) { return av_toupper(x & 0xFF) + (av_toupper((x >> 8) & 0xFF) << 8) + (av_toupper((x >> 16) & 0xFF) << 16) + (av_toupper((x >> 24) & 0xFF) << 24); }


void pcie_cap_slot_hot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { uint8_t *exp_cap; pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); object_unparent(OBJECT(dev)); pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDS); pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), PCI_EXP_HP_EV_PDC); }


int av_write_trailer(AVFormatContext *s) { int ret; while(s->packet_buffer){ int ret; AVPacketList *pktl= s->packet_buffer; //av_log(s, AV_LOG_DEBUG, "write_trailer st:%d dts:%lld\n", pktl->pkt.stream_index, pktl->pkt.dts); truncate_ts(s->streams[pktl->pkt.stream_index], &pktl->pkt); ret= s->oformat->write_packet(s, &pktl->pkt); s->packet_buffer= pktl->next; av_free_packet(&pktl->pkt); av_freep(&pktl); if(ret<0) return ret; } ret = s->oformat->write_trailer(s); av_freep(&s->priv_data); return ret; }


int ff_dca_xll_filter_frame(DCAXllDecoder *s, AVFrame *frame) { AVCodecContext *avctx = s->avctx; DCAContext *dca = avctx->priv_data; DCAExssAsset *asset = &dca->exss.assets[0]; DCAXllChSet *p = &s->chset[0], *c; enum AVMatrixEncoding matrix_encoding = AV_MATRIX_ENCODING_NONE; int i, j, k, ret, shift, nsamples, request_mask; int ch_remap[DCA_SPEAKER_COUNT]; // Force lossy downmixed output during recovery if (dca->packet & DCA_PACKET_RECOVERY) { for (i = 0, c = s->chset; i < s->nchsets; i++, c++) { if (i < s->nactivechsets) force_lossy_output(s, c); if (!c->primary_chset) c->dmix_embedded = 0; } s->scalable_lsbs = 0; s->fixed_lsb_width = 0; } // Filter frequency bands for active channel sets s->output_mask = 0; for (i = 0, c = s->chset; i < s->nactivechsets; i++, c++) { chs_filter_band_data(s, c, 0); if (c->residual_encode != (1 << c->nchannels) - 1 && (ret = combine_residual_frame(s, c)) < 0) return ret; if (s->scalable_lsbs) chs_assemble_msbs_lsbs(s, c, 0); if (c->nfreqbands > 1) { chs_filter_band_data(s, c, 1); chs_assemble_msbs_lsbs(s, c, 1); } s->output_mask |= c->ch_mask; } // Undo hierarchial downmix and/or apply scaling for (i = 1, c = &s->chset[1]; i < s->nchsets; i++, c++) { if (!is_hier_dmix_chset(c)) continue; if (i >= s->nactivechsets) { for (j = 0; j < c->nfreqbands; j++) if (c->bands[j].dmix_embedded) scale_down_mix(s, c, j); break; } for (j = 0; j < c->nfreqbands; j++) if (c->bands[j].dmix_embedded) undo_down_mix(s, c, j); } // Assemble frequency bands for active channel sets if (s->nfreqbands > 1) { for (i = 0; i < s->nactivechsets; i++) if ((ret = chs_assemble_freq_bands(s, &s->chset[i])) < 0) return ret; } // Normalize to regular 5.1 layout if downmixing if (dca->request_channel_layout) { if (s->output_mask & DCA_SPEAKER_MASK_Lss) { s->output_samples[DCA_SPEAKER_Ls] = s->output_samples[DCA_SPEAKER_Lss]; s->output_mask = (s->output_mask & ~DCA_SPEAKER_MASK_Lss) | DCA_SPEAKER_MASK_Ls; } if (s->output_mask & DCA_SPEAKER_MASK_Rss) { s->output_samples[DCA_SPEAKER_Rs] = s->output_samples[DCA_SPEAKER_Rss]; s->output_mask = (s->output_mask & ~DCA_SPEAKER_MASK_Rss) | DCA_SPEAKER_MASK_Rs; } } // Handle downmixing to stereo request if (dca->request_channel_layout == DCA_SPEAKER_LAYOUT_STEREO && DCA_HAS_STEREO(s->output_mask) && p->dmix_embedded && (p->dmix_type == DCA_DMIX_TYPE_LoRo || p->dmix_type == DCA_DMIX_TYPE_LtRt)) request_mask = DCA_SPEAKER_LAYOUT_STEREO; else request_mask = s->output_mask; if (!ff_dca_set_channel_layout(avctx, ch_remap, request_mask)) return AVERROR(EINVAL); avctx->sample_rate = p->freq << (s->nfreqbands - 1); switch (p->storage_bit_res) { case 16: avctx->sample_fmt = AV_SAMPLE_FMT_S16P; shift = 16 - p->pcm_bit_res; break; case 20: case 24: avctx->sample_fmt = AV_SAMPLE_FMT_S32P; shift = 24 - p->pcm_bit_res; break; default: return AVERROR(EINVAL); } avctx->bits_per_raw_sample = p->storage_bit_res; avctx->profile = FF_PROFILE_DTS_HD_MA; avctx->bit_rate = 0; frame->nb_samples = nsamples = s->nframesamples << (s->nfreqbands - 1); if ((ret = ff_get_buffer(avctx, frame, 0)) < 0) return ret; // Downmix primary channel set to stereo if (request_mask != s->output_mask) { ff_dca_downmix_to_stereo_fixed(s->dcadsp, s->output_samples, p->dmix_coeff, nsamples, s->output_mask); } for (i = 0; i < avctx->channels; i++) { int32_t *samples = s->output_samples[ch_remap[i]]; if (frame->format == AV_SAMPLE_FMT_S16P) { int16_t *plane = (int16_t *)frame->extended_data[i]; for (k = 0; k < nsamples; k++) plane[k] = av_clip_int16(samples[k] * (1 << shift)); } else { int32_t *plane = (int32_t *)frame->extended_data[i]; for (k = 0; k < nsamples; k++) plane[k] = clip23(samples[k] * (1 << shift)) * (1 << 8); } } if (!asset->one_to_one_map_ch_to_spkr) { if (asset->representation_type == DCA_REPR_TYPE_LtRt) matrix_encoding = AV_MATRIX_ENCODING_DOLBY; else if (asset->representation_type == DCA_REPR_TYPE_LhRh) matrix_encoding = AV_MATRIX_ENCODING_DOLBYHEADPHONE; } else if (request_mask != s->output_mask && p->dmix_type == DCA_DMIX_TYPE_LtRt) { matrix_encoding = AV_MATRIX_ENCODING_DOLBY; } if ((ret = ff_side_data_update_matrix_encoding(frame, matrix_encoding)) < 0) return ret; return 0; }


static void nbd_refresh_limits(BlockDriverState *bs, Error **errp) { bs->bl.max_discard = UINT32_MAX >> BDRV_SECTOR_BITS; bs->bl.max_transfer_length = UINT32_MAX >> BDRV_SECTOR_BITS; }


static void posix_aio_read(void *opaque) { PosixAioState *s = opaque; ssize_t len; /* read all bytes from signal pipe */ for (;;) { char bytes[16]; len = read(s->rfd, bytes, sizeof(bytes)); if (len == -1 && errno == EINTR) continue; /* try again */ if (len == sizeof(bytes)) continue; /* more to read */ break; } posix_aio_process_queue(s); }


static int qemu_rdma_register_and_get_keys(RDMAContext *rdma, RDMALocalBlock *block, uint8_t *host_addr, uint32_t *lkey, uint32_t *rkey, int chunk, uint8_t *chunk_start, uint8_t *chunk_end) { if (block->mr) { if (lkey) { *lkey = block->mr->lkey; } if (rkey) { *rkey = block->mr->rkey; } return 0; } /* allocate memory to store chunk MRs */ if (!block->pmr) { block->pmr = g_malloc0(block->nb_chunks * sizeof(struct ibv_mr *)); if (!block->pmr) { return -1; } } /* * If 'rkey', then we're the destination, so grant access to the source. * * If 'lkey', then we're the source VM, so grant access only to ourselves. */ if (!block->pmr[chunk]) { uint64_t len = chunk_end - chunk_start; DDPRINTF("Registering %" PRIu64 " bytes @ %p\n", len, chunk_start); block->pmr[chunk] = ibv_reg_mr(rdma->pd, chunk_start, len, (rkey ? (IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE) : 0)); if (!block->pmr[chunk]) { perror("Failed to register chunk!"); fprintf(stderr, "Chunk details: block: %d chunk index %d" " start %" PRIu64 " end %" PRIu64 " host %" PRIu64 " local %" PRIu64 " registrations: %d\n", block->index, chunk, (uint64_t) chunk_start, (uint64_t) chunk_end, (uint64_t) host_addr, (uint64_t) block->local_host_addr, rdma->total_registrations); return -1; } rdma->total_registrations++; } if (lkey) { *lkey = block->pmr[chunk]->lkey; } if (rkey) { *rkey = block->pmr[chunk]->rkey; } return 0; }


static int get_logical_cpus(AVCodecContext *avctx) { int ret, nb_cpus = 1; #if HAVE_SCHED_GETAFFINITY && defined(CPU_COUNT) cpu_set_t cpuset; CPU_ZERO(&cpuset); ret = sched_getaffinity(0, sizeof(cpuset), &cpuset); if (!ret) { nb_cpus = CPU_COUNT(&cpuset); } #elif HAVE_GETSYSTEMINFO SYSTEM_INFO sysinfo; GetSystemInfo(&sysinfo); nb_cpus = sysinfo.dwNumberOfProcessors; #elif HAVE_SYSCTL && defined(HW_NCPU) int mib[2] = { CTL_HW, HW_NCPU }; size_t len = sizeof(nb_cpus); ret = sysctl(mib, 2, &nb_cpus, &len, NULL, 0); if (ret == -1) nb_cpus = 0; #elif HAVE_SYSCONF && defined(_SC_NPROC_ONLN) nb_cpus = sysconf(_SC_NPROC_ONLN); #elif HAVE_SYSCONF && defined(_SC_NPROCESSORS_ONLN) nb_cpus = sysconf(_SC_NPROCESSORS_ONLN); #endif av_log(avctx, AV_LOG_DEBUG, "detected %d logical cores\n", nb_cpus); return FFMIN(nb_cpus, MAX_AUTO_THREADS); }


static av_cold int ljpeg_encode_close(AVCodecContext *avctx) { LJpegEncContext *s = avctx->priv_data; av_frame_free(&avctx->coded_frame); av_freep(&s->scratch); return 0; }


bool timerlistgroup_run_timers(QEMUTimerListGroup *tlg) { QEMUClockType type; bool progress = false; for (type = 0; type < QEMU_CLOCK_MAX; type++) { progress |= timerlist_run_timers(tlg->tl[type]); } return progress; }


static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) { target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Load and decode. FIXME: handle endianness. */ cpu_physical_memory_read (addr, (void *) &ctrl->channels[c].current_c, sizeof ctrl->channels[c].current_c); D(dump_c(c, &ctrl->channels[c].current_c)); /* I guess this should update the current pos. */ ctrl->channels[c].regs[RW_SAVED_DATA] = (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; }


static void sigfd_handler(void *opaque) { int fd = (intptr_t)opaque; struct qemu_signalfd_siginfo info; struct sigaction action; ssize_t len; while (1) { do { len = read(fd, &info, sizeof(info)); } while (len == -1 && errno == EINTR); if (len == -1 && errno == EAGAIN) { break; } if (len != sizeof(info)) { printf("read from sigfd returned %zd: %m\n", len); return; } sigaction(info.ssi_signo, NULL, &action); if ((action.sa_flags & SA_SIGINFO) && action.sa_sigaction) { action.sa_sigaction(info.ssi_signo, (siginfo_t *)&info, NULL); } else if (action.sa_handler) { action.sa_handler(info.ssi_signo); } } }


build_srat(GArray *table_data, GArray *linker) { AcpiSystemResourceAffinityTable *srat; AcpiSratProcessorAffinity *core; AcpiSratMemoryAffinity *numamem; int i; uint64_t curnode; int srat_start, numa_start, slots; uint64_t mem_len, mem_base, next_base; PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); ram_addr_t hotplugabble_address_space_size = object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, NULL); srat_start = table_data->len; srat = acpi_data_push(table_data, sizeof *srat); srat->reserved1 = cpu_to_le32(1); core = (void *)(srat + 1); for (i = 0; i < pcms->apic_id_limit; ++i) { core = acpi_data_push(table_data, sizeof *core); core->type = ACPI_SRAT_PROCESSOR; core->length = sizeof(*core); core->local_apic_id = i; curnode = pcms->node_cpu[i]; core->proximity_lo = curnode; memset(core->proximity_hi, 0, 3); core->local_sapic_eid = 0; core->flags = cpu_to_le32(1); } /* the memory map is a bit tricky, it contains at least one hole * from 640k-1M and possibly another one from 3.5G-4G. */ next_base = 0; numa_start = table_data->len; numamem = acpi_data_push(table_data, sizeof *numamem); acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); next_base = 1024 * 1024; for (i = 1; i < pcms->numa_nodes + 1; ++i) { mem_base = next_base; mem_len = pcms->node_mem[i - 1]; if (i == 1) { mem_len -= 1024 * 1024; } next_base = mem_base + mem_len; /* Cut out the ACPI_PCI hole */ if (mem_base <= pcms->below_4g_mem_size && next_base > pcms->below_4g_mem_size) { mem_len -= next_base - pcms->below_4g_mem_size; if (mem_len > 0) { numamem = acpi_data_push(table_data, sizeof *numamem); acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, MEM_AFFINITY_ENABLED); } mem_base = 1ULL << 32; mem_len = next_base - pcms->below_4g_mem_size; next_base += (1ULL << 32) - pcms->below_4g_mem_size; } numamem = acpi_data_push(table_data, sizeof *numamem); acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, MEM_AFFINITY_ENABLED); } slots = (table_data->len - numa_start) / sizeof *numamem; for (; slots < pcms->numa_nodes + 2; slots++) { numamem = acpi_data_push(table_data, sizeof *numamem); acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); } /* * Entry is required for Windows to enable memory hotplug in OS. * Memory devices may override proximity set by this entry, * providing _PXM method if necessary. */ if (hotplugabble_address_space_size) { numamem = acpi_data_push(table_data, sizeof *numamem); acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, hotplugabble_address_space_size, 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); } build_header(linker, table_data, (void *)(table_data->data + srat_start), "SRAT", table_data->len - srat_start, 1, NULL); }


static inline bool gluster_supports_zerofill(void) { return 0; }


static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type, uint64_t asc, int rw) { CPUState *cs = CPU(s390_env_get_cpu(env)); int ilen = ILEN_LATER; int bits = trans_bits(env, asc); /* Code accesses have an undefined ilc. */ if (rw == 2) { ilen = 2; } DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); trigger_pgm_exception(env, type, ilen); }


build_dsdt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, PcPciInfo *pci, MachineState *machine) { CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); PCMachineState *pcms = PC_MACHINE(machine); uint32_t nr_mem = machine->ram_slots; int root_bus_limit = 0xFF; PCIBus *bus = NULL; int i; dsdt = init_aml_allocator(); /* Reserve space for header */ acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); build_dbg_aml(dsdt); if (misc->is_piix4) { sb_scope = aml_scope("_SB"); dev = aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(1))); aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); build_hpet_aml(dsdt); build_piix4_pm(dsdt); build_piix4_isa_bridge(dsdt); build_isa_devices_aml(dsdt); build_piix4_pci_hotplug(dsdt); build_piix4_pci0_int(dsdt); } else { sb_scope = aml_scope("_SB"); aml_append(sb_scope, aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c)); aml_append(sb_scope, aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01)); field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); aml_append(field, aml_named_field("PCIB", 8)); aml_append(sb_scope, field); aml_append(dsdt, sb_scope); sb_scope = aml_scope("_SB"); dev = aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(1))); aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); build_hpet_aml(dsdt); build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); build_q35_pci0_int(dsdt); } build_cpu_hotplug_aml(dsdt); build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, pm->mem_hp_io_len); scope = aml_scope("_GPE"); { aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); if (misc->is_piix4) { method = aml_method("_E01", 0, AML_NOTSERIALIZED); aml_append(method, aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); aml_append(scope, method); } else { aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); } method = aml_method("_E02", 0, AML_NOTSERIALIZED); aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); aml_append(scope, method); method = aml_method("_E03", 0, AML_NOTSERIALIZED); aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); aml_append(scope, method); aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); } aml_append(dsdt, scope); bus = PC_MACHINE(machine)->bus; if (bus) { QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num = pci_bus_num(bus); uint8_t numa_node = pci_bus_numa_node(bus); /* look only for expander root buses */ if (!pci_bus_is_root(bus)) { continue; } if (bus_num < root_bus_limit) { root_bus_limit = bus_num - 1; } scope = aml_scope("\\_SB"); dev = aml_device("PC%.02X", bus_num); aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); if (numa_node != NUMA_NODE_UNASSIGNED) { aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); } aml_append(dev, build_prt(false)); crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), io_ranges, mem_ranges); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); } } scope = aml_scope("\\_SB.PCI0"); /* build PCI0._CRS */ crs = aml_resource_template(); aml_append(crs, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0, root_bus_limit, 0x0000, root_bus_limit + 1)); aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); aml_append(crs, aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, AML_ENTIRE_RANGE, 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); for (i = 0; i < io_ranges->len; i++) { entry = g_ptr_array_index(io_ranges, i); aml_append(crs, aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, AML_ENTIRE_RANGE, 0x0000, entry->base, entry->limit, 0x0000, entry->limit - entry->base + 1)); } aml_append(crs, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_CACHEABLE, AML_READ_WRITE, 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); for (i = 0; i < mem_ranges->len; i++) { entry = g_ptr_array_index(mem_ranges, i); aml_append(crs, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, 0, entry->base, entry->limit, 0, entry->limit - entry->base + 1)); } if (pci->w64.begin) { aml_append(crs, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_CACHEABLE, AML_READ_WRITE, 0, pci->w64.begin, pci->w64.end - 1, 0, pci->w64.end - pci->w64.begin)); } aml_append(scope, aml_name_decl("_CRS", crs)); /* reserve GPE0 block resources */ dev = aml_device("GPE0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); /* device present, functioning, decoding, not shown in UI */ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); g_ptr_array_free(io_ranges, true); g_ptr_array_free(mem_ranges, true); /* reserve PCIHP resources */ if (pm->pcihp_io_len) { dev = aml_device("PHPR"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); aml_append(dev, aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); /* device present, functioning, decoding, not shown in UI */ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, pm->pcihp_io_len) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); } aml_append(dsdt, scope); /* create S3_ / S4_ / S5_ packages if necessary */ scope = aml_scope("\\"); if (!pm->s3_disabled) { pkg = aml_package(4); aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ aml_append(pkg, aml_int(0)); /* reserved */ aml_append(pkg, aml_int(0)); /* reserved */ aml_append(scope, aml_name_decl("_S3", pkg)); } if (!pm->s4_disabled) { pkg = aml_package(4); aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ aml_append(pkg, aml_int(pm->s4_val)); aml_append(pkg, aml_int(0)); /* reserved */ aml_append(pkg, aml_int(0)); /* reserved */ aml_append(scope, aml_name_decl("_S4", pkg)); } pkg = aml_package(4); aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ aml_append(pkg, aml_int(0)); /* reserved */ aml_append(pkg, aml_int(0)); /* reserved */ aml_append(scope, aml_name_decl("_S5", pkg)); aml_append(dsdt, scope); /* create fw_cfg node, unconditionally */ { /* when using port i/o, the 8-bit data register *always* overlaps * with half of the 16-bit control register. Hence, the total size * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), "dma_enabled", NULL) ? ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : FW_CFG_CTL_SIZE; scope = aml_scope("\\_SB.PCI0"); dev = aml_device("FWCF"); aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); /* device present, functioning, decoding, not shown in UI */ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); } if (misc->applesmc_io_base) { scope = aml_scope("\\_SB.PCI0.ISA"); dev = aml_device("SMC"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); /* device present, functioning, decoding, not shown in UI */ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 0x01, APPLESMC_MAX_DATA_LENGTH) ); aml_append(crs, aml_irq_no_flags(6)); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); } if (misc->pvpanic_port) { scope = aml_scope("\\_SB.PCI0.ISA"); dev = aml_device("PEVT"); aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); crs = aml_resource_template(); aml_append(crs, aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, aml_int(misc->pvpanic_port), 1)); field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field("PEPT", 8)); aml_append(dev, field); /* device present, functioning, decoding, shown in UI */ aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); method = aml_method("RDPT", 0, AML_NOTSERIALIZED); aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); aml_append(method, aml_return(aml_local(0))); aml_append(dev, method); method = aml_method("WRPT", 1, AML_NOTSERIALIZED); aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); aml_append(dev, method); aml_append(scope, dev); aml_append(dsdt, scope); } sb_scope = aml_scope("\\_SB"); { build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm); build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, pm->mem_hp_io_len); { Object *pci_host; PCIBus *bus = NULL; pci_host = acpi_get_i386_pci_host(); if (pci_host) { bus = PCI_HOST_BRIDGE(pci_host)->bus; } if (bus) { Aml *scope = aml_scope("PCI0"); /* Scan all PCI buses. Generate tables to support hotplug. */ build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); if (misc->tpm_version != TPM_VERSION_UNSPEC) { dev = aml_device("ISA.TPM"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); crs = aml_resource_template(); aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); } aml_append(sb_scope, scope); } } aml_append(dsdt, sb_scope); } /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - dsdt->buf->len), "DSDT", dsdt->buf->len, 1, NULL, NULL); free_aml_allocator(); }


static void setup_frame(int sig, struct target_sigaction * ka, target_sigset_t *set, CPUMIPSState *regs) { struct sigframe *frame; abi_ulong frame_addr; int i; frame_addr = get_sigframe(ka, regs, sizeof(*frame)); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) goto give_sigsegv; install_sigtramp(frame->sf_code, TARGET_NR_sigreturn); if(setup_sigcontext(regs, &frame->sf_sc)) goto give_sigsegv; for(i = 0; i < TARGET_NSIG_WORDS; i++) { if(__put_user(set->sig[i], &frame->sf_mask.sig[i])) goto give_sigsegv; } /* * Arguments to signal handler: * * a0 = signal number * a1 = 0 (should be cause) * a2 = pointer to struct sigcontext * * $25 and PC point to the signal handler, $29 points to the * struct sigframe. */ regs->active_tc.gpr[ 4] = sig; regs->active_tc.gpr[ 5] = 0; regs->active_tc.gpr[ 6] = frame_addr + offsetof(struct sigframe, sf_sc); regs->active_tc.gpr[29] = frame_addr; regs->active_tc.gpr[31] = frame_addr + offsetof(struct sigframe, sf_code); /* The original kernel code sets CP0_EPC to the handler * since it returns to userland using eret * we cannot do this here, and we must set PC directly */ regs->active_tc.PC = regs->active_tc.gpr[25] = ka->_sa_handler; mips_set_hflags_isa_mode_from_pc(regs); unlock_user_struct(frame, frame_addr, 1); return; give_sigsegv: unlock_user_struct(frame, frame_addr, 1); force_sig(TARGET_SIGSEGV/*, current*/); }


void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2, uint32_t crfD) { CPU_DoubleU farg1, farg2; uint32_t ret = 0; farg1.ll = arg1; farg2.ll = arg2; if (unlikely(float64_is_any_nan(farg1.d) || float64_is_any_nan(farg2.d))) { ret = 0x01UL; } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) { ret = 0x08UL; } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) { ret = 0x04UL; } else { ret = 0x02UL; } env->fpscr &= ~(0x0F << FPSCR_FPRF); env->fpscr |= ret << FPSCR_FPRF; env->crf[crfD] = ret; if (unlikely(ret == 0x01UL)) { if (float64_is_signaling_nan(farg1.d) || float64_is_signaling_nan(farg2.d)) { /* sNaN comparison */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXVC); } else { /* qNaN comparison */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC); } } }


static void taihu_cpld_writew (void *opaque, hwaddr addr, uint32_t value) { taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); }


void ff_imdct_calc_sse(MDCTContext *s, FFTSample *output, const FFTSample *input, FFTSample *tmp) { long k, n8, n4, n2, n; const uint16_t *revtab = s->fft.revtab; const FFTSample *tcos = s->tcos; const FFTSample *tsin = s->tsin; const FFTSample *in1, *in2; FFTComplex *z = (FFTComplex *)tmp; n = 1 << s->nbits; n2 = n >> 1; n4 = n >> 2; n8 = n >> 3; asm volatile ("movaps %0, %%xmm7\n\t"::"m"(*p1m1p1m1)); /* pre rotation */ in1 = input; in2 = input + n2 - 4; /* Complex multiplication Two complex products per iteration, we could have 4 with 8 xmm registers, 8 with 16 xmm registers. Maybe we should unroll more. */ for (k = 0; k < n4; k += 2) { asm volatile ( "movaps %0, %%xmm0 \n\t" // xmm0 = r0 X r1 X : in2 "movaps %1, %%xmm3 \n\t" // xmm3 = X i1 X i0: in1 "movlps %2, %%xmm1 \n\t" // xmm1 = X X R1 R0: tcos "movlps %3, %%xmm2 \n\t" // xmm2 = X X I1 I0: tsin "shufps $95, %%xmm0, %%xmm0 \n\t" // xmm0 = r1 r1 r0 r0 "shufps $160,%%xmm3, %%xmm3 \n\t" // xmm3 = i1 i1 i0 i0 "unpcklps %%xmm2, %%xmm1 \n\t" // xmm1 = I1 R1 I0 R0 "movaps %%xmm1, %%xmm2 \n\t" // xmm2 = I1 R1 I0 R0 "xorps %%xmm7, %%xmm2 \n\t" // xmm2 = -I1 R1 -I0 R0 "mulps %%xmm1, %%xmm0 \n\t" // xmm0 = rI rR rI rR "shufps $177,%%xmm2, %%xmm2 \n\t" // xmm2 = R1 -I1 R0 -I0 "mulps %%xmm2, %%xmm3 \n\t" // xmm3 = Ri -Ii Ri -Ii "addps %%xmm3, %%xmm0 \n\t" // xmm0 = result ::"m"(in2[-2*k]), "m"(in1[2*k]), "m"(tcos[k]), "m"(tsin[k]) ); /* Should be in the same block, hack for gcc2.95 & gcc3 */ asm ( "movlps %%xmm0, %0 \n\t" "movhps %%xmm0, %1 \n\t" :"=m"(z[revtab[k]]), "=m"(z[revtab[k + 1]]) ); } ff_fft_calc_sse(&s->fft, z); /* Not currently needed, added for safety */ asm volatile ("movaps %0, %%xmm7\n\t"::"m"(*p1m1p1m1)); /* post rotation + reordering */ for (k = 0; k < n4; k += 2) { asm ( "movaps %0, %%xmm0 \n\t" // xmm0 = i1 r1 i0 r0: z "movlps %1, %%xmm1 \n\t" // xmm1 = X X R1 R0: tcos "movaps %%xmm0, %%xmm3 \n\t" // xmm3 = i1 r1 i0 r0 "movlps %2, %%xmm2 \n\t" // xmm2 = X X I1 I0: tsin "shufps $160,%%xmm0, %%xmm0 \n\t" // xmm0 = r1 r1 r0 r0 "shufps $245,%%xmm3, %%xmm3 \n\t" // xmm3 = i1 i1 i0 i0 "unpcklps %%xmm2, %%xmm1 \n\t" // xmm1 = I1 R1 I0 R0 "movaps %%xmm1, %%xmm2 \n\t" // xmm2 = I1 R1 I0 R0 "xorps %%xmm7, %%xmm2 \n\t" // xmm2 = -I1 R1 -I0 R0 "mulps %%xmm1, %%xmm0 \n\t" // xmm0 = rI rR rI rR "shufps $177,%%xmm2, %%xmm2 \n\t" // xmm2 = R1 -I1 R0 -I0 "mulps %%xmm2, %%xmm3 \n\t" // xmm3 = Ri -Ii Ri -Ii "addps %%xmm3, %%xmm0 \n\t" // xmm0 = result "movaps %%xmm0, %0 \n\t" :"+m"(z[k]) :"m"(tcos[k]), "m"(tsin[k]) ); } /* Mnemonics: 0 = z[k].re 1 = z[k].im 2 = z[k + 1].re 3 = z[k + 1].im 4 = z[-k - 2].re 5 = z[-k - 2].im 6 = z[-k - 1].re 7 = z[-k - 1].im */ k = 16-n; asm volatile("movaps %0, %%xmm7 \n\t"::"m"(*m1m1m1m1)); asm volatile( "1: \n\t" "movaps -16(%4,%0), %%xmm1 \n\t" // xmm1 = 4 5 6 7 = z[-2-k] "neg %0 \n\t" "movaps (%4,%0), %%xmm0 \n\t" // xmm0 = 0 1 2 3 = z[k] "xorps %%xmm7, %%xmm0 \n\t" // xmm0 = -0 -1 -2 -3 "movaps %%xmm0, %%xmm2 \n\t" // xmm2 = -0 -1 -2 -3 "shufps $141,%%xmm1, %%xmm0 \n\t" // xmm0 = -1 -3 4 6 "shufps $216,%%xmm1, %%xmm2 \n\t" // xmm2 = -0 -2 5 7 "shufps $156,%%xmm0, %%xmm0 \n\t" // xmm0 = -1 6 -3 4 ! "shufps $156,%%xmm2, %%xmm2 \n\t" // xmm2 = -0 7 -2 5 ! "movaps %%xmm0, (%1,%0) \n\t" // output[2*k] "movaps %%xmm2, (%2,%0) \n\t" // output[n2+2*k] "neg %0 \n\t" "shufps $27, %%xmm0, %%xmm0 \n\t" // xmm0 = 4 -3 6 -1 "xorps %%xmm7, %%xmm0 \n\t" // xmm0 = -4 3 -6 1 ! "shufps $27, %%xmm2, %%xmm2 \n\t" // xmm2 = 5 -2 7 -0 ! "movaps %%xmm0, -16(%2,%0) \n\t" // output[n2-4-2*k] "movaps %%xmm2, -16(%3,%0) \n\t" // output[n-4-2*k] "add $16, %0 \n\t" "jle 1b \n\t" :"+r"(k) :"r"(output), "r"(output+n2), "r"(output+n), "r"(z+n8) :"memory" ); }


QemuConsole *graphic_console_init(graphic_hw_update_ptr update, graphic_hw_invalidate_ptr invalidate, graphic_hw_screen_dump_ptr screen_dump, graphic_hw_text_update_ptr text_update, void *opaque) { int width = 640; int height = 480; QemuConsole *s; DisplayState *ds; ds = get_alloc_displaystate(); trace_console_gfx_new(); s = new_console(ds, GRAPHIC_CONSOLE); s->hw_update = update; s->hw_invalidate = invalidate; s->hw_screen_dump = screen_dump; s->hw_text_update = text_update; s->hw = opaque; s->surface = qemu_create_displaysurface(width, height); return s; }


virtio_crypto_check_cryptodev_is_used(const Object *obj, const char *name, Object *val, Error **errp) { if (cryptodev_backend_is_used(CRYPTODEV_BACKEND(val))) { char *path = object_get_canonical_path_component(val); error_setg(errp, "can't use already used cryptodev backend: %s", path); g_free(path); } else { qdev_prop_allow_set_link_before_realize(obj, name, val, errp); } }


static void device_unparent(Object *obj) { DeviceState *dev = DEVICE(obj); if (dev->parent_bus != NULL) { bus_remove_child(dev->parent_bus, dev); } }


static always_inline int isnormal (float64 d) { CPU_DoubleU u; u.d = d; uint32_t exp = (u.ll >> 52) & 0x7FF; return ((0 < exp) && (exp < 0x7FF)); }


static void virtio_set_status(struct subchannel_id schid, unsigned long dev_addr) { unsigned char status = dev_addr; run_ccw(schid, CCW_CMD_WRITE_STATUS, &status, sizeof(status)); }


bool has_help_option(const char *param) { size_t buflen = strlen(param) + 1; char *buf = g_malloc(buflen); const char *p = param; bool result = false; while (*p) { p = get_opt_value(buf, buflen, p); if (*p) { p++; } if (is_help_option(buf)) { result = true; goto out; } } out: free(buf); return result; }


setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc) { int err = 0; int i; __put_user(exception_resume_pc(regs), &sc->sc_pc); regs->hflags &= ~MIPS_HFLAG_BMASK; __put_user(0, &sc->sc_regs[0]); for (i = 1; i < 32; ++i) { __put_user(regs->active_tc.gpr[i], &sc->sc_regs[i]); } __put_user(regs->active_tc.HI[0], &sc->sc_mdhi); __put_user(regs->active_tc.LO[0], &sc->sc_mdlo); /* Rather than checking for dsp existence, always copy. The storage would just be garbage otherwise. */ __put_user(regs->active_tc.HI[1], &sc->sc_hi1); __put_user(regs->active_tc.HI[2], &sc->sc_hi2); __put_user(regs->active_tc.HI[3], &sc->sc_hi3); __put_user(regs->active_tc.LO[1], &sc->sc_lo1); __put_user(regs->active_tc.LO[2], &sc->sc_lo2); __put_user(regs->active_tc.LO[3], &sc->sc_lo3); { uint32_t dsp = cpu_rddsp(0x3ff, regs); __put_user(dsp, &sc->sc_dsp); } __put_user(1, &sc->sc_used_math); for (i = 0; i < 32; ++i) { __put_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); } return err; }


restore_sigcontext(CPUX86State *env, struct target_sigcontext *sc, int *peax) { unsigned int err = 0; abi_ulong fpstate_addr; unsigned int tmpflags; cpu_x86_load_seg(env, R_GS, tswap16(sc->gs)); cpu_x86_load_seg(env, R_FS, tswap16(sc->fs)); cpu_x86_load_seg(env, R_ES, tswap16(sc->es)); cpu_x86_load_seg(env, R_DS, tswap16(sc->ds)); env->regs[R_EDI] = tswapl(sc->edi); env->regs[R_ESI] = tswapl(sc->esi); env->regs[R_EBP] = tswapl(sc->ebp); env->regs[R_ESP] = tswapl(sc->esp); env->regs[R_EBX] = tswapl(sc->ebx); env->regs[R_EDX] = tswapl(sc->edx); env->regs[R_ECX] = tswapl(sc->ecx); env->eip = tswapl(sc->eip); cpu_x86_load_seg(env, R_CS, lduw_p(&sc->cs) | 3); cpu_x86_load_seg(env, R_SS, lduw_p(&sc->ss) | 3); tmpflags = tswapl(sc->eflags); env->eflags = (env->eflags & ~0x40DD5) | (tmpflags & 0x40DD5); // regs->orig_eax = -1; /* disable syscall checks */ fpstate_addr = tswapl(sc->fpstate); if (fpstate_addr != 0) { if (!access_ok(VERIFY_READ, fpstate_addr, sizeof(struct target_fpstate))) goto badframe; cpu_x86_frstor(env, fpstate_addr, 1); } *peax = tswapl(sc->eax); return err; badframe: return 1; }


static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) { TCGv tmp; switch (op1) { #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) case 1: tmp = tcg_temp_new(TCG_TYPE_PTR); tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); PAS_OP(s) break; case 5: tmp = tcg_temp_new(TCG_TYPE_PTR); tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); PAS_OP(u) break; #undef gen_pas_helper #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) case 2: PAS_OP(q); break; case 3: PAS_OP(sh); break; case 6: PAS_OP(uq); break; case 7: PAS_OP(uh); break; #undef gen_pas_helper } }


static void bdrv_dirty_bitmap_truncate(BlockDriverState *bs) { BdrvDirtyBitmap *bitmap; uint64_t size = bdrv_nb_sectors(bs); QLIST_FOREACH(bitmap, &bs->dirty_bitmaps, list) { if (bdrv_dirty_bitmap_frozen(bitmap)) { continue; } hbitmap_truncate(bitmap->bitmap, size); bitmap->size = size; } }