LF_FUNC (h, luma, sse2) LF_IFUNC(h, luma_intra, sse2) LF_FUNC (v, luma, sse2) LF_IFUNC(v, luma_intra, sse2) /***********************************/ /* weighted prediction */ #define H264_WEIGHT(W, H, OPT) \ void ff_h264_weight_ ## W ## x ## H ## _ ## OPT(uint8_t *dst, \ int stride, int log2_denom, int weight, int offset); #define H264_BIWEIGHT(W, H, OPT) \ void ff_h264_biweight_ ## W ## x ## H ## _ ## OPT(uint8_t *dst, \ uint8_t *src, int stride, int log2_denom, int weightd, \ int weights, int offset); #define H264_BIWEIGHT_MMX(W,H) \ H264_WEIGHT (W, H, mmx2) \ H264_BIWEIGHT(W, H, mmx2) #define H264_BIWEIGHT_MMX_SSE(W,H) \ H264_BIWEIGHT_MMX(W, H) \ H264_WEIGHT (W, H, sse2) \ H264_BIWEIGHT (W, H, sse2) \ H264_BIWEIGHT (W, H, ssse3) H264_BIWEIGHT_MMX_SSE(16, 16) H264_BIWEIGHT_MMX_SSE(16, 8) H264_BIWEIGHT_MMX_SSE( 8, 16) H264_BIWEIGHT_MMX_SSE( 8, 8) H264_BIWEIGHT_MMX_SSE( 8, 4) H264_BIWEIGHT_MMX ( 4, 8) H264_BIWEIGHT_MMX ( 4, 4) H264_BIWEIGHT_MMX ( 4, 2) void ff_h264dsp_init_x86(H264DSPContext *c) { int mm_flags = av_get_cpu_flags(); if (mm_flags & AV_CPU_FLAG_MMX) { c->h264_idct_dc_add= c->h264_idct_add= ff_h264_idct_add_mmx; c->h264_idct8_dc_add= c->h264_idct8_add= ff_h264_idct8_add_mmx; c->h264_idct_add16 = ff_h264_idct_add16_mmx; c->h264_idct8_add4 = ff_h264_idct8_add4_mmx; c->h264_idct_add8 = ff_h264_idct_add8_mmx; c->h264_idct_add16intra= ff_h264_idct_add16intra_mmx; if (mm_flags & AV_CPU_FLAG_MMX2) { c->h264_idct_dc_add= ff_h264_idct_dc_add_mmx2; c->h264_idct8_dc_add= ff_h264_idct8_dc_add_mmx2; c->h264_idct_add16 = ff_h264_idct_add16_mmx2; c->h264_idct8_add4 = ff_h264_idct8_add4_mmx2; c->h264_idct_add8 = ff_h264_idct_add8_mmx2; c->h264_idct_add16intra= ff_h264_idct_add16intra_mmx2; c->h264_loop_filter_strength= h264_loop_filter_strength_mmx2; } if(mm_flags & AV_CPU_FLAG_SSE2){ c->h264_idct8_add = ff_h264_idct8_add_sse2; c->h264_idct8_add4= ff_h264_idct8_add4_sse2; } #if HAVE_YASM if (mm_flags & AV_CPU_FLAG_MMX2){ c->h264_v_loop_filter_chroma= ff_x264_deblock_v_chroma_mmxext; c->h264_h_loop_filter_chroma= ff_x264_deblock_h_chroma_mmxext; c->h264_v_loop_filter_chroma_intra= ff_x264_deblock_v_chroma_intra_mmxext; c->h264_h_loop_filter_chroma_intra= ff_x264_deblock_h_chroma_intra_mmxext; #if ARCH_X86_32 c->h264_v_loop_filter_luma= ff_x264_deblock_v_luma_mmxext; c->h264_h_loop_filter_luma= ff_x264_deblock_h_luma_mmxext; c->h264_v_loop_filter_luma_intra = ff_x264_deblock_v_luma_intra_mmxext; c->h264_h_loop_filter_luma_intra = ff_x264_deblock_h_luma_intra_mmxext; #endif c->weight_h264_pixels_tab[0]= ff_h264_weight_16x16_mmx2; c->weight_h264_pixels_tab[1]= ff_h264_weight_16x8_mmx2; c->weight_h264_pixels_tab[2]= ff_h264_weight_8x16_mmx2; c->weight_h264_pixels_tab[3]= ff_h264_weight_8x8_mmx2; c->weight_h264_pixels_tab[4]= ff_h264_weight_8x4_mmx2; c->weight_h264_pixels_tab[5]= ff_h264_weight_4x8_mmx2; c->weight_h264_pixels_tab[6]= ff_h264_weight_4x4_mmx2; c->weight_h264_pixels_tab[7]= ff_h264_weight_4x2_mmx2; c->biweight_h264_pixels_tab[0]= ff_h264_biweight_16x16_mmx2; c->biweight_h264_pixels_tab[1]= ff_h264_biweight_16x8_mmx2; c->biweight_h264_pixels_tab[2]= ff_h264_biweight_8x16_mmx2; c->biweight_h264_pixels_tab[3]= ff_h264_biweight_8x8_mmx2; c->biweight_h264_pixels_tab[4]= ff_h264_biweight_8x4_mmx2; c->biweight_h264_pixels_tab[5]= ff_h264_biweight_4x8_mmx2; c->biweight_h264_pixels_tab[6]= ff_h264_biweight_4x4_mmx2; c->biweight_h264_pixels_tab[7]= ff_h264_biweight_4x2_mmx2; if (mm_flags&AV_CPU_FLAG_SSE2) { c->weight_h264_pixels_tab[0]= ff_h264_weight_16x16_sse2; c->weight_h264_pixels_tab[1]= ff_h264_weight_16x8_sse2; c->weight_h264_pixels_tab[2]= ff_h264_weight_8x16_sse2; c->weight_h264_pixels_tab[3]= ff_h264_weight_8x8_sse2; c->weight_h264_pixels_tab[4]= ff_h264_weight_8x4_sse2; c->biweight_h264_pixels_tab[0]= ff_h264_biweight_16x16_sse2; c->biweight_h264_pixels_tab[1]= ff_h264_biweight_16x8_sse2; c->biweight_h264_pixels_tab[2]= ff_h264_biweight_8x16_sse2; c->biweight_h264_pixels_tab[3]= ff_h264_biweight_8x8_sse2; c->biweight_h264_pixels_tab[4]= ff_h264_biweight_8x4_sse2; #if ARCH_X86_64 || !defined(__ICC) || __ICC > 1110 c->h264_v_loop_filter_luma = ff_x264_deblock_v_luma_sse2; c->h264_h_loop_filter_luma = ff_x264_deblock_h_luma_sse2; c->h264_v_loop_filter_luma_intra = ff_x264_deblock_v_luma_intra_sse2; c->h264_h_loop_filter_luma_intra = ff_x264_deblock_h_luma_intra_sse2; #endif c->h264_idct_add16 = ff_h264_idct_add16_sse2; c->h264_idct_add8 = ff_h264_idct_add8_sse2; c->h264_idct_add16intra = ff_h264_idct_add16intra_sse2; } if (mm_flags&AV_CPU_FLAG_SSSE3) { c->biweight_h264_pixels_tab[0]= ff_h264_biweight_16x16_ssse3; c->biweight_h264_pixels_tab[1]= ff_h264_biweight_16x8_ssse3; c->biweight_h264_pixels_tab[2]= ff_h264_biweight_8x16_ssse3; c->biweight_h264_pixels_tab[3]= ff_h264_biweight_8x8_ssse3; c->biweight_h264_pixels_tab[4]= ff_h264_biweight_8x4_ssse3; } } #endif } }


static av_cold int libwebp_anim_encode_init(AVCodecContext *avctx) { int ret = ff_libwebp_encode_init_common(avctx); if (!ret) { LibWebPAnimContext *s = avctx->priv_data; WebPAnimEncoderOptions enc_options; WebPAnimEncoderOptionsInit(&enc_options); // TODO(urvang): Expose some options on command-line perhaps. s->enc = WebPAnimEncoderNew(avctx->width, avctx->height, &enc_options); if (!s->enc) return AVERROR(EINVAL); s->prev_frame_pts = -1; s->done = 0; } return ret; }


static int sls_flag_use_localtime_filename(AVFormatContext *oc, HLSContext *c, VariantStream *vs) { if (c->flags & HLS_SECOND_LEVEL_SEGMENT_INDEX) { char * filename = av_strdup(oc->filename); // %%d will be %d after strftime if (!filename) return AVERROR(ENOMEM); if (replace_int_data_in_filename(oc->filename, sizeof(oc->filename), #if FF_API_HLS_WRAP filename, 'd', c->wrap ? vs->sequence % c->wrap : vs->sequence) < 1) { #else filename, 'd', vs->sequence) < 1) { #endif av_log(c, AV_LOG_ERROR, "Invalid second level segment filename template '%s', " "you can try to remove second_level_segment_index flag\n", filename); av_free(filename); return AVERROR(EINVAL); } av_free(filename); } if (c->flags & (HLS_SECOND_LEVEL_SEGMENT_SIZE | HLS_SECOND_LEVEL_SEGMENT_DURATION)) { av_strlcpy(vs->current_segment_final_filename_fmt, oc->filename, sizeof(vs->current_segment_final_filename_fmt)); if (c->flags & HLS_SECOND_LEVEL_SEGMENT_SIZE) { char * filename = av_strdup(oc->filename); // %%s will be %s after strftime if (!filename) return AVERROR(ENOMEM); if (replace_int_data_in_filename(oc->filename, sizeof(oc->filename), filename, 's', 0) < 1) { av_log(c, AV_LOG_ERROR, "Invalid second level segment filename template '%s', " "you can try to remove second_level_segment_size flag\n", filename); av_free(filename); return AVERROR(EINVAL); } av_free(filename); } if (c->flags & HLS_SECOND_LEVEL_SEGMENT_DURATION) { char * filename = av_strdup(oc->filename); // %%t will be %t after strftime if (!filename) return AVERROR(ENOMEM); if (replace_int_data_in_filename(oc->filename, sizeof(oc->filename), filename, 't', 0) < 1) { av_log(c, AV_LOG_ERROR, "Invalid second level segment filename template '%s', " "you can try to remove second_level_segment_time flag\n", filename); av_free(filename); return AVERROR(EINVAL); } av_free(filename); } } return 0; }


static bool e1000_full_mac_needed(void *opaque) { E1000State *s = opaque; return s->compat_flags & E1000_FLAG_MAC; }


void qemu_bh_delete(QEMUBH *bh) { qemu_free(bh); }


static void net_socket_receive(void *opaque, const uint8_t *buf, size_t size) { NetSocketState *s = opaque; uint32_t len; len = htonl(size); send_all(s->fd, (const uint8_t *)&len, sizeof(len)); send_all(s->fd, buf, size); }


static void *rcu_read_stress_test(void *arg) { int i; int itercnt = 0; struct rcu_stress *p; int pc; long long n_reads_local = 0; volatile int garbage = 0; rcu_register_thread(); *(struct rcu_reader_data **)arg = &rcu_reader; while (goflag == GOFLAG_INIT) { g_usleep(1000); } while (goflag == GOFLAG_RUN) { rcu_read_lock(); p = atomic_rcu_read(&rcu_stress_current); if (p->mbtest == 0) { n_mberror++; } rcu_read_lock(); for (i = 0; i < 100; i++) { garbage++; } rcu_read_unlock(); pc = p->pipe_count; rcu_read_unlock(); if ((pc > RCU_STRESS_PIPE_LEN) || (pc < 0)) { pc = RCU_STRESS_PIPE_LEN; } atomic_inc(&rcu_stress_count[pc]); n_reads_local++; if ((++itercnt % 0x1000) == 0) { synchronize_rcu(); } } atomic_add(&n_reads, n_reads_local); rcu_unregister_thread(); return NULL; }


static void rtc_realizefn(DeviceState *dev, Error **errp) { ISADevice *isadev = ISA_DEVICE(dev); RTCState *s = MC146818_RTC(dev); int base = 0x70; s->cmos_data[RTC_REG_A] = 0x26; s->cmos_data[RTC_REG_B] = 0x02; s->cmos_data[RTC_REG_C] = 0x00; s->cmos_data[RTC_REG_D] = 0x80; /* This is for historical reasons. The default base year qdev property * was set to 2000 for most machine types before the century byte was * implemented. * * This if statement means that the century byte will be always 0 * (at least until 2079...) for base_year = 1980, but will be set * correctly for base_year = 2000. */ if (s->base_year == 2000) { s->base_year = 0; } rtc_set_date_from_host(isadev); #ifdef TARGET_I386 switch (s->lost_tick_policy) { case LOST_TICK_POLICY_SLEW: s->coalesced_timer = timer_new_ns(rtc_clock, rtc_coalesced_timer, s); break; case LOST_TICK_POLICY_DISCARD: break; default: error_setg(errp, "Invalid lost tick policy."); return; } #endif s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); check_update_timer(s); s->clock_reset_notifier.notify = rtc_notify_clock_reset; qemu_clock_register_reset_notifier(rtc_clock, &s->clock_reset_notifier); s->suspend_notifier.notify = rtc_notify_suspend; qemu_register_suspend_notifier(&s->suspend_notifier); memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); isa_register_ioport(isadev, &s->io, base); qdev_set_legacy_instance_id(dev, base, 3); qemu_register_reset(rtc_reset, s); object_property_add(OBJECT(s), "date", "struct tm", rtc_get_date, NULL, NULL, s, NULL); object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s), "date", NULL); }


static int decode_init(AVCodecContext *avctx) { HYuvContext *s = avctx->priv_data; int width, height; s->avctx= avctx; s->flags= avctx->flags; dsputil_init(&s->dsp, avctx); memset(s->vlc, 0, 3*sizeof(VLC)); width= s->width= avctx->width; height= s->height= avctx->height; avctx->coded_frame= &s->picture; s->bgr32=1; assert(width && height); //if(avctx->extradata) // printf("extradata:%X, extradata_size:%d\n", *(uint32_t*)avctx->extradata, avctx->extradata_size); if(avctx->extradata_size){ if((avctx->bits_per_sample&7) && avctx->bits_per_sample != 12) s->version=1; // do such files exist at all? else s->version=2; }else s->version=0; if(s->version==2){ int method; method= ((uint8_t*)avctx->extradata)[0]; s->decorrelate= method&64 ? 1 : 0; s->predictor= method&63; s->bitstream_bpp= ((uint8_t*)avctx->extradata)[1]; if(s->bitstream_bpp==0) s->bitstream_bpp= avctx->bits_per_sample&~7; s->context= ((uint8_t*)avctx->extradata)[2] & 0x40 ? 1 : 0; if(read_huffman_tables(s, ((uint8_t*)avctx->extradata)+4, avctx->extradata_size) < 0) return -1; }else{ switch(avctx->bits_per_sample&7){ case 1: s->predictor= LEFT; s->decorrelate= 0; break; case 2: s->predictor= LEFT; s->decorrelate= 1; break; case 3: s->predictor= PLANE; s->decorrelate= avctx->bits_per_sample >= 24; break; case 4: s->predictor= MEDIAN; s->decorrelate= 0; break; default: s->predictor= LEFT; //OLD s->decorrelate= 0; break; } s->bitstream_bpp= avctx->bits_per_sample & ~7; s->context= 0; if(read_old_huffman_tables(s) < 0) return -1; } if(((uint8_t*)avctx->extradata)[2] & 0x20) s->interlaced= ((uint8_t*)avctx->extradata)[2] & 0x10 ? 1 : 0; else s->interlaced= height > 288; switch(s->bitstream_bpp){ case 12: avctx->pix_fmt = PIX_FMT_YUV420P; break; case 16: if(s->yuy2){ avctx->pix_fmt = PIX_FMT_YUV422; }else{ avctx->pix_fmt = PIX_FMT_YUV422P; } break; case 24: case 32: if(s->bgr32){ avctx->pix_fmt = PIX_FMT_RGBA32; }else{ avctx->pix_fmt = PIX_FMT_BGR24; } break; default: assert(0); } // av_log(NULL, AV_LOG_DEBUG, "pred:%d bpp:%d hbpp:%d il:%d\n", s->predictor, s->bitstream_bpp, avctx->bits_per_sample, s->interlaced); return 0; }


static void palmte_init(ram_addr_t ram_size, int vga_ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { struct omap_mpu_state_s *cpu; int flash_size = 0x00800000; int sdram_size = palmte_binfo.ram_size; int io; static uint32_t cs0val = 0xffffffff; static uint32_t cs1val = 0x0000e1a0; static uint32_t cs2val = 0x0000e1a0; static uint32_t cs3val = 0xe1a0e1a0; ram_addr_t phys_flash; int rom_size, rom_loaded = 0; DisplayState *ds = get_displaystate(); if (ram_size < flash_size + sdram_size + OMAP15XX_SRAM_SIZE) { fprintf(stderr, "This architecture uses %i bytes of memory\n", flash_size + sdram_size + OMAP15XX_SRAM_SIZE); exit(1); } cpu = omap310_mpu_init(sdram_size, cpu_model); /* External Flash (EMIFS) */ cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM); io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val); cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, OMAP_CS0_SIZE - flash_size, io); io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val); cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val); cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); palmte_microwire_setup(cpu); qemu_add_kbd_event_handler(palmte_button_event, cpu); palmte_gpio_setup(cpu); /* Setup initial (reset) machine state */ if (nb_option_roms) { rom_size = get_image_size(option_rom[0]); if (rom_size > flash_size) { fprintf(stderr, "%s: ROM image too big (%x > %x)\n", __FUNCTION__, rom_size, flash_size); rom_size = 0; } if (rom_size > 0) { rom_size = load_image_targphys(option_rom[0], OMAP_CS0_BASE, flash_size); rom_loaded = 1; cpu->env->regs[15] = 0x00000000; } if (rom_size < 0) { fprintf(stderr, "%s: error loading '%s'\n", __FUNCTION__, option_rom[0]); } } if (!rom_loaded && !kernel_filename) { fprintf(stderr, "Kernel or ROM image must be specified\n"); exit(1); } /* Load the kernel. */ if (kernel_filename) { /* Start at bootloader. */ cpu->env->regs[15] = palmte_binfo.loader_start; palmte_binfo.kernel_filename = kernel_filename; palmte_binfo.kernel_cmdline = kernel_cmdline; palmte_binfo.initrd_filename = initrd_filename; arm_load_kernel(cpu->env, &palmte_binfo); } /* FIXME: We shouldn't really be doing this here. The LCD controller will set the size once configured, so this just sets an initial size until the guest activates the display. */ ds->surface = qemu_resize_displaysurface(ds, 320, 320); dpy_resize(ds); }


static void menelaus_save(QEMUFile *f, void *opaque) { MenelausState *s = (MenelausState *) opaque; qemu_put_be32(f, s->firstbyte); qemu_put_8s(f, &s->reg); qemu_put_8s(f, &s->vcore[0]); qemu_put_8s(f, &s->vcore[1]); qemu_put_8s(f, &s->vcore[2]); qemu_put_8s(f, &s->vcore[3]); qemu_put_8s(f, &s->vcore[4]); qemu_put_8s(f, &s->dcdc[0]); qemu_put_8s(f, &s->dcdc[1]); qemu_put_8s(f, &s->dcdc[2]); qemu_put_8s(f, &s->ldo[0]); qemu_put_8s(f, &s->ldo[1]); qemu_put_8s(f, &s->ldo[2]); qemu_put_8s(f, &s->ldo[3]); qemu_put_8s(f, &s->ldo[4]); qemu_put_8s(f, &s->ldo[5]); qemu_put_8s(f, &s->ldo[6]); qemu_put_8s(f, &s->ldo[7]); qemu_put_8s(f, &s->sleep[0]); qemu_put_8s(f, &s->sleep[1]); qemu_put_8s(f, &s->osc); qemu_put_8s(f, &s->detect); qemu_put_be16s(f, &s->mask); qemu_put_be16s(f, &s->status); qemu_put_8s(f, &s->dir); qemu_put_8s(f, &s->inputs); qemu_put_8s(f, &s->outputs); qemu_put_8s(f, &s->bbsms); qemu_put_8s(f, &s->pull[0]); qemu_put_8s(f, &s->pull[1]); qemu_put_8s(f, &s->pull[2]); qemu_put_8s(f, &s->pull[3]); qemu_put_8s(f, &s->mmc_ctrl[0]); qemu_put_8s(f, &s->mmc_ctrl[1]); qemu_put_8s(f, &s->mmc_ctrl[2]); qemu_put_8s(f, &s->mmc_debounce); qemu_put_8s(f, &s->rtc.ctrl); qemu_put_be16s(f, &s->rtc.comp); /* Should be <= 1000 */ qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock)); tm_put(f, &s->rtc.new); tm_put(f, &s->rtc.alm); qemu_put_byte(f, s->pwrbtn_state); i2c_slave_save(f, &s->i2c); }


static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); pcmc->get_hotplug_handler = mc->get_hotplug_handler; pcmc->pci_enabled = true; pcmc->has_acpi_build = true; pcmc->rsdp_in_ram = true; pcmc->smbios_defaults = true; pcmc->smbios_uuid_encoded = true; pcmc->gigabyte_align = true; pcmc->has_reserved_memory = true; pcmc->kvmclock_enabled = true; pcmc->enforce_aligned_dimm = true; /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported * to be used at the moment, 32K should be enough for a while. */ pcmc->acpi_data_size = 0x20000 + 0x8000; pcmc->save_tsc_khz = true; mc->get_hotplug_handler = pc_get_hotpug_handler; mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus; mc->default_boot_order = "cad"; mc->hot_add_cpu = pc_hot_add_cpu; mc->max_cpus = 255; mc->reset = pc_machine_reset; hc->pre_plug = pc_machine_device_pre_plug_cb; hc->plug = pc_machine_device_plug_cb; hc->post_plug = pc_machine_device_post_plug_cb; hc->unplug_request = pc_machine_device_unplug_request_cb; hc->unplug = pc_machine_device_unplug_cb; nc->nmi_monitor_handler = x86_nmi; object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", pc_machine_get_hotplug_memory_region_size, NULL, NULL, NULL, &error_abort); object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, NULL, NULL, &error_abort); object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", pc_machine_get_smm, pc_machine_set_smm, NULL, NULL, &error_abort); object_class_property_set_description(oc, PC_MACHINE_SMM, "Enable SMM (pc & q35)", &error_abort); object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", pc_machine_get_vmport, pc_machine_set_vmport, NULL, NULL, &error_abort); object_class_property_set_description(oc, PC_MACHINE_VMPORT, "Enable vmport (pc & q35)", &error_abort); object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); }


static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr, unsigned size) { return 0; }


int vfio_mmap_region(Object *obj, VFIORegion *region, MemoryRegion *mem, MemoryRegion *submem, void **map, size_t size, off_t offset, const char *name) { int ret = 0; VFIODevice *vbasedev = region->vbasedev; if (vbasedev->allow_mmap && size && region->flags & VFIO_REGION_INFO_FLAG_MMAP) { int prot = 0; if (region->flags & VFIO_REGION_INFO_FLAG_READ) { prot |= PROT_READ; } if (region->flags & VFIO_REGION_INFO_FLAG_WRITE) { prot |= PROT_WRITE; } *map = mmap(NULL, size, prot, MAP_SHARED, vbasedev->fd, region->fd_offset + offset); if (*map == MAP_FAILED) { *map = NULL; ret = -errno; goto empty_region; } memory_region_init_ram_ptr(submem, obj, name, size, *map); memory_region_set_skip_dump(submem); } else { empty_region: /* Create a zero sized sub-region to make cleanup easy. */ memory_region_init(submem, obj, name, 0); } memory_region_add_subregion(mem, offset, submem); return ret; }


read_insn_microblaze (bfd_vma memaddr, struct disassemble_info *info, struct op_code_struct **opr) { unsigned char ibytes[4]; int status; struct op_code_struct * op; unsigned long inst; status = info->read_memory_func (memaddr, ibytes, 4, info); if (status != 0) { info->memory_error_func (status, memaddr, info); return 0; } if (info->endian == BFD_ENDIAN_BIG) inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3]; else if (info->endian == BFD_ENDIAN_LITTLE) inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0]; else abort (); /* Just a linear search of the table. */ for (op = opcodes; op->name != 0; op ++) if (op->bit_sequence == (inst & op->opcode_mask)) break; *opr = op; return inst; }


bool bdrv_qiov_is_aligned(BlockDriverState *bs, QEMUIOVector *qiov) { int i; size_t alignment = bdrv_opt_mem_align(bs); for (i = 0; i < qiov->niov; i++) { if ((uintptr_t) qiov->iov[i].iov_base % alignment) { return false; } if (qiov->iov[i].iov_len % alignment) { return false; } } return true; }


iscsi_process_write(void *arg) { IscsiLun *iscsilun = arg; struct iscsi_context *iscsi = iscsilun->iscsi; aio_context_acquire(iscsilun->aio_context); iscsi_service(iscsi, POLLOUT); iscsi_set_events(iscsilun); aio_context_release(iscsilun->aio_context); }


static void vc1_decode_b_mb(VC1Context *v) { MpegEncContext *s = &v->s; GetBitContext *gb = &s->gb; int i, j; int mb_pos = s->mb_x + s->mb_y * s->mb_stride; int cbp = 0; /* cbp decoding stuff */ int mqdiff, mquant; /* MB quantization */ int ttmb = v->ttfrm; /* MB Transform type */ int mb_has_coeffs = 0; /* last_flag */ int index, index1; /* LUT indexes */ int val, sign; /* temp values */ int first_block = 1; int dst_idx, off; int skipped, direct; int dmv_x[2], dmv_y[2]; int bmvtype = BMV_TYPE_BACKWARD; mquant = v->pq; /* Loosy initialization */ s->mb_intra = 0; if (v->dmb_is_raw) direct = get_bits1(gb); else direct = v->direct_mb_plane[mb_pos]; if (v->skip_is_raw) skipped = get_bits1(gb); else skipped = v->s.mbskip_table[mb_pos]; dmv_x[0] = dmv_x[1] = dmv_y[0] = dmv_y[1] = 0; for(i = 0; i < 6; i++) { v->mb_type[0][s->block_index[i]] = 0; s->dc_val[0][s->block_index[i]] = 0; } s->current_picture.qscale_table[mb_pos] = 0; if (!direct) { if (!skipped) { GET_MVDATA(dmv_x[0], dmv_y[0]); dmv_x[1] = dmv_x[0]; dmv_y[1] = dmv_y[0]; } if(skipped || !s->mb_intra) { bmvtype = decode012(gb); switch(bmvtype) { case 0: bmvtype = (v->bfraction >= (B_FRACTION_DEN/2)) ? BMV_TYPE_BACKWARD : BMV_TYPE_FORWARD; break; case 1: bmvtype = (v->bfraction >= (B_FRACTION_DEN/2)) ? BMV_TYPE_FORWARD : BMV_TYPE_BACKWARD; break; case 2: bmvtype = BMV_TYPE_INTERPOLATED; dmv_x[0] = dmv_y[0] = 0; } } } for(i = 0; i < 6; i++) v->mb_type[0][s->block_index[i]] = s->mb_intra; if (skipped) { if(direct) bmvtype = BMV_TYPE_INTERPOLATED; vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); vc1_b_mc(v, dmv_x, dmv_y, direct, bmvtype); return; } if (direct) { cbp = get_vlc2(&v->s.gb, v->cbpcy_vlc->table, VC1_CBPCY_P_VLC_BITS, 2); GET_MQUANT(); s->mb_intra = 0; s->current_picture.qscale_table[mb_pos] = mquant; if(!v->ttmbf) ttmb = get_vlc2(gb, ff_vc1_ttmb_vlc[v->tt_index].table, VC1_TTMB_VLC_BITS, 2); dmv_x[0] = dmv_y[0] = dmv_x[1] = dmv_y[1] = 0; vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); vc1_b_mc(v, dmv_x, dmv_y, direct, bmvtype); } else { if(!mb_has_coeffs && !s->mb_intra) { /* no coded blocks - effectively skipped */ vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); vc1_b_mc(v, dmv_x, dmv_y, direct, bmvtype); return; } if(s->mb_intra && !mb_has_coeffs) { GET_MQUANT(); s->current_picture.qscale_table[mb_pos] = mquant; s->ac_pred = get_bits1(gb); cbp = 0; vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); } else { if(bmvtype == BMV_TYPE_INTERPOLATED) { GET_MVDATA(dmv_x[0], dmv_y[0]); if(!mb_has_coeffs) { /* interpolated skipped block */ vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); vc1_b_mc(v, dmv_x, dmv_y, direct, bmvtype); return; } } vc1_pred_b_mv(v, dmv_x, dmv_y, direct, bmvtype); if(!s->mb_intra) { vc1_b_mc(v, dmv_x, dmv_y, direct, bmvtype); } if(s->mb_intra) s->ac_pred = get_bits1(gb); cbp = get_vlc2(&v->s.gb, v->cbpcy_vlc->table, VC1_CBPCY_P_VLC_BITS, 2); GET_MQUANT(); s->current_picture.qscale_table[mb_pos] = mquant; if(!v->ttmbf && !s->mb_intra && mb_has_coeffs) ttmb = get_vlc2(gb, ff_vc1_ttmb_vlc[v->tt_index].table, VC1_TTMB_VLC_BITS, 2); } } dst_idx = 0; for (i=0; i<6; i++) { s->dc_val[0][s->block_index[i]] = 0; dst_idx += i >> 2; val = ((cbp >> (5 - i)) & 1); off = (i & 4) ? 0 : ((i & 1) * 8 + (i & 2) * 4 * s->linesize); v->mb_type[0][s->block_index[i]] = s->mb_intra; if(s->mb_intra) { /* check if prediction blocks A and C are available */ v->a_avail = v->c_avail = 0; if(i == 2 || i == 3 || !s->first_slice_line) v->a_avail = v->mb_type[0][s->block_index[i] - s->block_wrap[i]]; if(i == 1 || i == 3 || s->mb_x) v->c_avail = v->mb_type[0][s->block_index[i] - 1]; vc1_decode_intra_block(v, s->block[i], i, val, mquant, (i&4)?v->codingset2:v->codingset); if((i>3) && (s->flags & CODEC_FLAG_GRAY)) continue; v->vc1dsp.vc1_inv_trans_8x8(s->block[i]); if(v->rangeredfrm) for(j = 0; j < 64; j++) s->block[i][j] <<= 1; s->dsp.put_signed_pixels_clamped(s->block[i], s->dest[dst_idx] + off, i & 4 ? s->uvlinesize : s->linesize); } else if(val) { vc1_decode_p_block(v, s->block[i], i, mquant, ttmb, first_block, s->dest[dst_idx] + off, (i&4)?s->uvlinesize:s->linesize, (i&4) && (s->flags & CODEC_FLAG_GRAY), 0, 0, 0); if(!v->ttmbf && ttmb < 8) ttmb = -1; first_block = 0; } } }


static void openpic_update_irq(OpenPICState *opp, int n_IRQ) { IRQSource *src; bool active, was_active; int i; src = &opp->src[n_IRQ]; active = src->pending; if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { /* Interrupt source is disabled */ DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); active = false; } was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); /* * We don't have a similar check for already-active because * ctpr may have changed and we need to withdraw the interrupt. */ if (!active && !was_active) { DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); return; } if (active) { src->ivpr |= IVPR_ACTIVITY_MASK; } else { src->ivpr &= ~IVPR_ACTIVITY_MASK; } if (src->idr == 0) { /* No target */ DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); return; } if (src->idr == (1 << src->last_cpu)) { /* Only one CPU is allowed to receive this IRQ */ IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); } else if (!(src->ivpr & IVPR_MODE_MASK)) { /* Directed delivery mode */ for (i = 0; i < opp->nb_cpus; i++) { if (src->destmask & (1 << i)) { IRQ_local_pipe(opp, i, n_IRQ, active, was_active); } } } else { /* Distributed delivery mode */ for (i = src->last_cpu + 1; i != src->last_cpu; i++) { if (i == opp->nb_cpus) { i = 0; } if (src->destmask & (1 << i)) { IRQ_local_pipe(opp, i, n_IRQ, active, was_active); src->last_cpu = i; break; } } } }


void dpy_gfx_update_dirty(QemuConsole *con, MemoryRegion *address_space, hwaddr base, bool invalidate) { DisplaySurface *ds = qemu_console_surface(con); int width = surface_stride(ds); int height = surface_height(ds); hwaddr size = width * height; MemoryRegionSection mem_section; MemoryRegion *mem; ram_addr_t addr; int first, last, i; bool dirty; mem_section = memory_region_find(address_space, base, size); mem = mem_section.mr; if (int128_get64(mem_section.size) != size || !memory_region_is_ram(mem_section.mr)) { goto out; } assert(mem); memory_region_sync_dirty_bitmap(mem); addr = mem_section.offset_within_region; first = -1; last = -1; for (i = 0; i < height; i++, addr += width) { dirty = invalidate || memory_region_get_dirty(mem, addr, width, DIRTY_MEMORY_VGA); if (dirty) { if (first == -1) { first = i; } last = i; } if (first != -1 && !dirty) { assert(last != -1 && last >= first); dpy_gfx_update(con, 0, first, surface_width(ds), last - first + 1); first = -1; } } if (first != -1) { assert(last != -1 && last >= first); dpy_gfx_update(con, 0, first, surface_width(ds), last - first + 1); } memory_region_reset_dirty(mem, mem_section.offset_within_region, size, DIRTY_MEMORY_VGA); out: memory_region_unref(mem); }


static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) { Range *range = opaque; PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); int i; if (!(cmd & PCI_COMMAND_MEMORY)) { return; } if (pc->is_bridge) { pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); base = MAX(base, 0x1ULL << 32); if (limit >= base) { Range pref_range; pref_range.begin = base; pref_range.end = limit + 1; range_extend(range, &pref_range); } } for (i = 0; i < PCI_NUM_REGIONS; ++i) { PCIIORegion *r = &dev->io_regions[i]; Range region_range; if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO) || !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { continue; } region_range.begin = pci_bar_address(dev, i, r->type, r->size); region_range.end = region_range.begin + r->size; if (region_range.begin == PCI_BAR_UNMAPPED) { continue; } region_range.begin = MAX(region_range.begin, 0x1ULL << 32); if (region_range.end - 1 >= region_range.begin) { range_extend(range, &region_range); } } }


cryptodev_builtin_get_aes_algo(uint32_t key_len, Error **errp) { int algo; if (key_len == 128 / 8) { algo = QCRYPTO_CIPHER_ALG_AES_128; } else if (key_len == 192 / 8) { algo = QCRYPTO_CIPHER_ALG_AES_192; } else if (key_len == 256 / 8) { algo = QCRYPTO_CIPHER_ALG_AES_256; } else { error_setg(errp, "Unsupported key length :%u", key_len); return -1; } return algo; }


static int sd_snapshot_list(BlockDriverState *bs, QEMUSnapshotInfo **psn_tab) { BDRVSheepdogState *s = bs->opaque; SheepdogReq req; int fd, nr = 1024, ret, max = BITS_TO_LONGS(SD_NR_VDIS) * sizeof(long); QEMUSnapshotInfo *sn_tab = NULL; unsigned wlen, rlen; int found = 0; static SheepdogInode inode; unsigned long *vdi_inuse; unsigned int start_nr; uint64_t hval; uint32_t vid; vdi_inuse = g_malloc(max); fd = connect_to_sdog(s->addr, s->port); if (fd < 0) { ret = fd; goto out; } rlen = max; wlen = 0; memset(&req, 0, sizeof(req)); req.opcode = SD_OP_READ_VDIS; req.data_length = max; ret = do_req(fd, (SheepdogReq *)&req, vdi_inuse, &wlen, &rlen); closesocket(fd); if (ret) { goto out; } sn_tab = g_malloc0(nr * sizeof(*sn_tab)); /* calculate a vdi id with hash function */ hval = fnv_64a_buf(s->name, strlen(s->name), FNV1A_64_INIT); start_nr = hval & (SD_NR_VDIS - 1); fd = connect_to_sdog(s->addr, s->port); if (fd < 0) { error_report("failed to connect"); ret = fd; goto out; } for (vid = start_nr; found < nr; vid = (vid + 1) % SD_NR_VDIS) { if (!test_bit(vid, vdi_inuse)) { break; } /* we don't need to read entire object */ ret = read_object(fd, (char *)&inode, vid_to_vdi_oid(vid), 0, SD_INODE_SIZE - sizeof(inode.data_vdi_id), 0, s->cache_enabled); if (ret) { continue; } if (!strcmp(inode.name, s->name) && is_snapshot(&inode)) { sn_tab[found].date_sec = inode.snap_ctime >> 32; sn_tab[found].date_nsec = inode.snap_ctime & 0xffffffff; sn_tab[found].vm_state_size = inode.vm_state_size; sn_tab[found].vm_clock_nsec = inode.vm_clock_nsec; snprintf(sn_tab[found].id_str, sizeof(sn_tab[found].id_str), "%u", inode.snap_id); pstrcpy(sn_tab[found].name, MIN(sizeof(sn_tab[found].name), sizeof(inode.tag)), inode.tag); found++; } } closesocket(fd); out: *psn_tab = sn_tab; g_free(vdi_inuse); if (ret < 0) { return ret; } return found; }


static void versatile_init(MachineState *machine, int board_id) { ARMCPU *cpu; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev, *sysctl; SysBusDevice *busdev; DeviceState *pl041; PCIBus *pci_bus; NICInfo *nd; I2CBus *i2c; int n; int done_smc = 0; DriveInfo *dinfo; if (!machine->cpu_model) { machine->cpu_model = "arm926"; } cpu = cpu_arm_init(machine->cpu_model); if (!cpu) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } memory_region_init_ram(ram, NULL, "versatile.ram", machine->ram_size, &error_abort); vmstate_register_ram_global(ram); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ memory_region_add_subregion(sysmem, 0, ram); sysctl = qdev_create(NULL, "realview_sysctl"); qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); qdev_init_nofail(sysctl); sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); dev = sysbus_create_varargs("pl190", 0x10140000, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), NULL); for (n = 0; n < 32; n++) { pic[n] = qdev_get_gpio_in(dev, n); } dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); for (n = 0; n < 32; n++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); sic[n] = qdev_get_gpio_in(dev, n); } sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); dev = qdev_create(NULL, "versatile_pci"); busdev = SYS_BUS_DEVICE(dev); qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ sysbus_connect_irq(busdev, 0, sic[27]); sysbus_connect_irq(busdev, 1, sic[28]); sysbus_connect_irq(busdev, 2, sic[29]); sysbus_connect_irq(busdev, 3, sic[30]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); for(n = 0; n < nb_nics; n++) { nd = &nd_table[n]; if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { smc91c111_init(nd, 0x10010000, sic[25]); done_smc = 1; } else { pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); } } if (usb_enabled(false)) { pci_create_simple(pci_bus, -1, "pci-ohci"); } n = drive_get_max_bus(IF_SCSI); while (n >= 0) { pci_create_simple(pci_bus, -1, "lsi53c895a"); n--; } sysbus_create_simple("pl011", 0x101f1000, pic[12]); sysbus_create_simple("pl011", 0x101f2000, pic[13]); sysbus_create_simple("pl011", 0x101f3000, pic[14]); sysbus_create_simple("pl011", 0x10009000, sic[6]); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); sysbus_create_simple("sp804", 0x101e3000, pic[5]); sysbus_create_simple("pl061", 0x101e4000, pic[6]); sysbus_create_simple("pl061", 0x101e5000, pic[7]); sysbus_create_simple("pl061", 0x101e6000, pic[8]); sysbus_create_simple("pl061", 0x101e7000, pic[9]); /* The versatile/PB actually has a modified Color LCD controller that includes hardware cursor support from the PL111. */ dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); /* Wire up the mux control signals from the SYS_CLCD register */ qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); /* Add PL031 Real Time Clock. */ sysbus_create_simple("pl031", 0x101e8000, pic[10]); dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); i2c_create_slave(i2c, "ds1338", 0x68); /* Add PL041 AACI Interface to the LM4549 codec */ pl041 = qdev_create(NULL, "pl041"); qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); qdev_init_nofail(pl041); sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); /* Memory map for Versatile/PB: */ /* 0x10000000 System registers. */ /* 0x10001000 PCI controller config registers. */ /* 0x10002000 Serial bus interface. */ /* 0x10003000 Secondary interrupt controller. */ /* 0x10004000 AACI (audio). */ /* 0x10005000 MMCI0. */ /* 0x10006000 KMI0 (keyboard). */ /* 0x10007000 KMI1 (mouse). */ /* 0x10008000 Character LCD Interface. */ /* 0x10009000 UART3. */ /* 0x1000a000 Smart card 1. */ /* 0x1000b000 MMCI1. */ /* 0x10010000 Ethernet. */ /* 0x10020000 USB. */ /* 0x10100000 SSMC. */ /* 0x10110000 MPMC. */ /* 0x10120000 CLCD Controller. */ /* 0x10130000 DMA Controller. */ /* 0x10140000 Vectored interrupt controller. */ /* 0x101d0000 AHB Monitor Interface. */ /* 0x101e0000 System Controller. */ /* 0x101e1000 Watchdog Interface. */ /* 0x101e2000 Timer 0/1. */ /* 0x101e3000 Timer 2/3. */ /* 0x101e4000 GPIO port 0. */ /* 0x101e5000 GPIO port 1. */ /* 0x101e6000 GPIO port 2. */ /* 0x101e7000 GPIO port 3. */ /* 0x101e8000 RTC. */ /* 0x101f0000 Smart card 0. */ /* 0x101f1000 UART0. */ /* 0x101f2000 UART1. */ /* 0x101f3000 UART2. */ /* 0x101f4000 SSPI. */ /* 0x34000000 NOR Flash */ dinfo = drive_get(IF_PFLASH, 0, 0); if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", VERSATILE_FLASH_SIZE, dinfo ? blk_bs(blk_by_legacy_dinfo(dinfo)) : NULL, VERSATILE_FLASH_SECT_SIZE, VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { fprintf(stderr, "qemu: Error registering flash memory.\n"); } versatile_binfo.ram_size = machine->ram_size; versatile_binfo.kernel_filename = machine->kernel_filename; versatile_binfo.kernel_cmdline = machine->kernel_cmdline; versatile_binfo.initrd_filename = machine->initrd_filename; versatile_binfo.board_id = board_id; arm_load_kernel(cpu, &versatile_binfo); }


size_t qemu_file_set_rate_limit(QEMUFile *f, size_t new_rate) { /* any failed or completed migration keeps its state to allow probing of * migration data, but has no associated file anymore */ if (f && f->set_rate_limit) return f->set_rate_limit(f->opaque, new_rate); return 0; }


static uint64_t apb_config_readl (void *opaque, target_phys_addr_t addr, unsigned size) { APBState *s = opaque; uint32_t val; switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ val = 0; /* XXX: not implemented yet */ break; case 0x200 ... 0x20b: /* IOMMU */ val = s->iommu[(addr & 0xf) >> 2]; break; case 0x20c ... 0x3ff: /* IOMMU flush */ val = 0; break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { val = s->pci_irq_map[(addr & 0x3f) >> 3]; } else { val = 0; } break; case 0x1000 ... 0x1080: /* OBIO interrupt control */ if (addr & 4) { val = s->obio_irq_map[(addr & 0xff) >> 3]; } else { val = 0; } break; case 0x2000 ... 0x202f: /* PCI control */ val = s->pci_control[(addr & 0x3f) >> 2]; break; case 0xf020 ... 0xf027: /* Reset control */ if (addr & 4) { val = s->reset_control; } else { val = 0; } break; case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ case 0xf000 ... 0xf01f: /* FFB config, memory control */ /* we don't care */ default: val = 0; break; } APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val); return val; }


static int kvm_put_sregs(CPUState *env) { struct kvm_sregs sregs; memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); if (env->interrupt_injected >= 0) { sregs.interrupt_bitmap[env->interrupt_injected / 64] |= (uint64_t)1 << (env->interrupt_injected % 64); } if ((env->eflags & VM_MASK)) { set_v8086_seg(&sregs.cs, &env->segs[R_CS]); set_v8086_seg(&sregs.ds, &env->segs[R_DS]); set_v8086_seg(&sregs.es, &env->segs[R_ES]); set_v8086_seg(&sregs.fs, &env->segs[R_FS]); set_v8086_seg(&sregs.gs, &env->segs[R_GS]); set_v8086_seg(&sregs.ss, &env->segs[R_SS]); } else { set_seg(&sregs.cs, &env->segs[R_CS]); set_seg(&sregs.ds, &env->segs[R_DS]); set_seg(&sregs.es, &env->segs[R_ES]); set_seg(&sregs.fs, &env->segs[R_FS]); set_seg(&sregs.gs, &env->segs[R_GS]); set_seg(&sregs.ss, &env->segs[R_SS]); } set_seg(&sregs.tr, &env->tr); set_seg(&sregs.ldt, &env->ldt); sregs.idt.limit = env->idt.limit; sregs.idt.base = env->idt.base; sregs.gdt.limit = env->gdt.limit; sregs.gdt.base = env->gdt.base; sregs.cr0 = env->cr[0]; sregs.cr2 = env->cr[2]; sregs.cr3 = env->cr[3]; sregs.cr4 = env->cr[4]; sregs.cr8 = cpu_get_apic_tpr(env->apic_state); sregs.apic_base = cpu_get_apic_base(env->apic_state); sregs.efer = env->efer; return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); }


write_f(int argc, char **argv) { struct timeval t1, t2; int Cflag = 0, pflag = 0, qflag = 0; int c, cnt; char *buf; int64_t offset; int count; /* Some compilers get confused and warn if this is not initialized. */ int total = 0; int pattern = 0xcd; while ((c = getopt(argc, argv, "CpP:q")) != EOF) { switch (c) { case 'C': Cflag = 1; break; case 'p': pflag = 1; break; case 'P': pattern = atoi(optarg); break; case 'q': qflag = 1; break; default: return command_usage(&write_cmd); } } if (optind != argc - 2) return command_usage(&write_cmd); offset = cvtnum(argv[optind]); if (offset < 0) { printf("non-numeric length argument -- %s\n", argv[optind]); return 0; } optind++; count = cvtnum(argv[optind]); if (count < 0) { printf("non-numeric length argument -- %s\n", argv[optind]); return 0; } if (!pflag) { if (offset & 0x1ff) { printf("offset %lld is not sector aligned\n", (long long)offset); return 0; } if (count & 0x1ff) { printf("count %d is not sector aligned\n", count); return 0; } } buf = qemu_io_alloc(count, pattern); gettimeofday(&t1, NULL); if (pflag) cnt = do_pwrite(buf, offset, count, &total); else cnt = do_write(buf, offset, count, &total); gettimeofday(&t2, NULL); if (cnt < 0) { printf("write failed: %s\n", strerror(-cnt)); return 0; } if (qflag) return 0; /* Finally, report back -- -C gives a parsable format */ t2 = tsub(t2, t1); print_report("wrote", &t2, offset, count, total, cnt, Cflag); qemu_io_free(buf); return 0; }


static int cpu_post_load(void *opaque, int version_id) { PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; target_ulong msr; /* * If we're operating in compat mode, we should be ok as long as * the destination supports the same compatiblity mode. * * Otherwise, however, we require that the destination has exactly * the same CPU model as the source. */ #if defined(TARGET_PPC64) if (cpu->compat_pvr) { Error *local_err = NULL; ppc_set_compat(cpu, cpu->compat_pvr, &local_err); if (local_err) { error_report_err(local_err); error_free(local_err); return -1; } } else #endif { if (!pvr_match(cpu, env->spr[SPR_PVR])) { return -1; } } env->lr = env->spr[SPR_LR]; env->ctr = env->spr[SPR_CTR]; cpu_write_xer(env, env->spr[SPR_XER]); #if defined(TARGET_PPC64) env->cfar = env->spr[SPR_CFAR]; #endif env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; } for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; } if (!cpu->vhyp) { ppc_store_sdr1(env, env->spr[SPR_SDR1]); } /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ msr = env->msr; env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); hreg_compute_mem_idx(env); return 0; }


static inline void t_gen_mov_TN_preg(TCGv tn, int r) { if (r < 0 || r > 15) { fprintf(stderr, "wrong register read $p%d\n", r); } if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { tcg_gen_mov_tl(tn, tcg_const_tl(0)); } else if (r == PR_VR) { tcg_gen_mov_tl(tn, tcg_const_tl(32)); } else { tcg_gen_mov_tl(tn, cpu_PR[r]); } }


int coroutine_fn bdrv_is_allocated(BlockDriverState *bs, int64_t sector_num, int nb_sectors, int *pnum) { int64_t ret = bdrv_get_block_status(bs, sector_num, nb_sectors, pnum); if (ret < 0) { return ret; } return (ret & BDRV_BLOCK_ALLOCATED); }


static int rndis_query_response(USBNetState *s, rndis_query_msg_type *buf, unsigned int length) { rndis_query_cmplt_type *resp; /* oid_supported_list is the largest data reply */ uint8_t infobuf[sizeof(oid_supported_list)]; uint32_t bufoffs, buflen; int infobuflen; unsigned int resplen; bufoffs = le32_to_cpu(buf->InformationBufferOffset) + 8; buflen = le32_to_cpu(buf->InformationBufferLength); if (bufoffs + buflen > length) return USB_RET_STALL; infobuflen = ndis_query(s, le32_to_cpu(buf->OID), bufoffs + (uint8_t *) buf, buflen, infobuf, sizeof(infobuf)); resplen = sizeof(rndis_query_cmplt_type) + ((infobuflen < 0) ? 0 : infobuflen); resp = rndis_queue_response(s, resplen); if (!resp) return USB_RET_STALL; resp->MessageType = cpu_to_le32(RNDIS_QUERY_CMPLT); resp->RequestID = buf->RequestID; /* Still LE in msg buffer */ resp->MessageLength = cpu_to_le32(resplen); if (infobuflen < 0) { /* OID not supported */ resp->Status = cpu_to_le32(RNDIS_STATUS_NOT_SUPPORTED); resp->InformationBufferLength = cpu_to_le32(0); resp->InformationBufferOffset = cpu_to_le32(0); return 0; } resp->Status = cpu_to_le32(RNDIS_STATUS_SUCCESS); resp->InformationBufferOffset = cpu_to_le32(infobuflen ? sizeof(rndis_query_cmplt_type) - 8 : 0); resp->InformationBufferLength = cpu_to_le32(infobuflen); memcpy(resp + 1, infobuf, infobuflen); return 0; }


static int pollfds_fill(GArray *pollfds, fd_set *rfds, fd_set *wfds, fd_set *xfds) { int nfds = -1; int i; for (i = 0; i < pollfds->len; i++) { GPollFD *pfd = &g_array_index(pollfds, GPollFD, i); int fd = pfd->fd; int events = pfd->events; if (events & (G_IO_IN | G_IO_HUP | G_IO_ERR)) { FD_SET(fd, rfds); nfds = MAX(nfds, fd); } if (events & (G_IO_OUT | G_IO_ERR)) { FD_SET(fd, wfds); nfds = MAX(nfds, fd); } if (events & G_IO_PRI) { FD_SET(fd, xfds); nfds = MAX(nfds, fd); } } return nfds; }


static int matroska_parse_rm_audio(MatroskaDemuxContext *matroska, MatroskaTrack *track, AVStream *st, uint8_t *data, int size, uint64_t timecode, int64_t pos) { int a = st->codec->block_align; int sps = track->audio.sub_packet_size; int cfs = track->audio.coded_framesize; int h = track->audio.sub_packet_h; int y = track->audio.sub_packet_cnt; int w = track->audio.frame_size; int x; if (!track->audio.pkt_cnt) { if (track->audio.sub_packet_cnt == 0) track->audio.buf_timecode = timecode; if (st->codec->codec_id == AV_CODEC_ID_RA_288) { if (size < cfs * h / 2) { av_log(matroska->ctx, AV_LOG_ERROR, "Corrupt int4 RM-style audio packet size\n"); return AVERROR_INVALIDDATA; } for (x=0; x<h/2; x++) memcpy(track->audio.buf+x*2*w+y*cfs, data+x*cfs, cfs); } else if (st->codec->codec_id == AV_CODEC_ID_SIPR) { if (size < w) { av_log(matroska->ctx, AV_LOG_ERROR, "Corrupt sipr RM-style audio packet size\n"); return AVERROR_INVALIDDATA; } memcpy(track->audio.buf + y*w, data, w); } else { if (size < sps * w / sps) { av_log(matroska->ctx, AV_LOG_ERROR, "Corrupt generic RM-style audio packet size\n"); return AVERROR_INVALIDDATA; } for (x=0; x<w/sps; x++) memcpy(track->audio.buf+sps*(h*x+((h+1)/2)*(y&1)+(y>>1)), data+x*sps, sps); } if (++track->audio.sub_packet_cnt >= h) { if (st->codec->codec_id == AV_CODEC_ID_SIPR) ff_rm_reorder_sipr_data(track->audio.buf, h, w); track->audio.sub_packet_cnt = 0; track->audio.pkt_cnt = h*w / a; } } while (track->audio.pkt_cnt) { AVPacket *pkt = NULL; if (!(pkt = av_mallocz(sizeof(AVPacket))) || av_new_packet(pkt, a) < 0){ av_free(pkt); return AVERROR(ENOMEM); } memcpy(pkt->data, track->audio.buf + a * (h*w / a - track->audio.pkt_cnt--), a); pkt->pts = track->audio.buf_timecode; track->audio.buf_timecode = AV_NOPTS_VALUE; pkt->pos = pos; pkt->stream_index = st->index; dynarray_add(&matroska->packets,&matroska->num_packets,pkt); } return 0; }


void exit_program(int ret) { int i, j; for (i = 0; i < nb_filtergraphs; i++) { avfilter_graph_free(&filtergraphs[i]->graph); for (j = 0; j < filtergraphs[i]->nb_inputs; j++) av_freep(&filtergraphs[i]->inputs[j]); av_freep(&filtergraphs[i]->inputs); for (j = 0; j < filtergraphs[i]->nb_outputs; j++) av_freep(&filtergraphs[i]->outputs[j]); av_freep(&filtergraphs[i]->outputs); av_freep(&filtergraphs[i]); } av_freep(&filtergraphs); /* close files */ for (i = 0; i < nb_output_files; i++) { AVFormatContext *s = output_files[i]->ctx; if (!(s->oformat->flags & AVFMT_NOFILE) && s->pb) avio_close(s->pb); avformat_free_context(s); av_dict_free(&output_files[i]->opts); av_freep(&output_files[i]); } for (i = 0; i < nb_output_streams; i++) { AVBitStreamFilterContext *bsfc = output_streams[i]->bitstream_filters; while (bsfc) { AVBitStreamFilterContext *next = bsfc->next; av_bitstream_filter_close(bsfc); bsfc = next; } output_streams[i]->bitstream_filters = NULL; if (output_streams[i]->output_frame) { AVFrame *frame = output_streams[i]->output_frame; if (frame->extended_data != frame->data) av_freep(&frame->extended_data); av_freep(&frame); } av_freep(&output_streams[i]->avfilter); av_freep(&output_streams[i]->filtered_frame); av_freep(&output_streams[i]); } for (i = 0; i < nb_input_files; i++) { avformat_close_input(&input_files[i]->ctx); av_freep(&input_files[i]); } for (i = 0; i < nb_input_streams; i++) { av_freep(&input_streams[i]->decoded_frame); av_dict_free(&input_streams[i]->opts); free_buffer_pool(input_streams[i]); av_freep(&input_streams[i]->filters); av_freep(&input_streams[i]); } if (vstats_file) fclose(vstats_file); av_free(vstats_filename); av_freep(&input_streams); av_freep(&input_files); av_freep(&output_streams); av_freep(&output_files); uninit_opts(); av_free(audio_buf); allocated_audio_buf_size = 0; av_free(async_buf); allocated_async_buf_size = 0; avfilter_uninit(); avformat_network_deinit(); if (received_sigterm) { av_log(NULL, AV_LOG_INFO, "Received signal %d: terminating.\n", (int) received_sigterm); exit (255); } exit(ret); }


static int parse_playlist(HLSContext *c, const char *url, struct playlist *pls, AVIOContext *in) { int ret = 0, is_segment = 0, is_variant = 0; int64_t duration = 0; enum KeyType key_type = KEY_NONE; uint8_t iv[16] = ""; int has_iv = 0; char key[MAX_URL_SIZE] = ""; char line[MAX_URL_SIZE]; const char *ptr; int close_in = 0; int64_t seg_offset = 0; int64_t seg_size = -1; uint8_t *new_url = NULL; struct variant_info variant_info; char tmp_str[MAX_URL_SIZE]; struct segment *cur_init_section = NULL; if (!in && c->http_persistent && c->playlist_pb) { in = c->playlist_pb; ret = open_url_keepalive(c->ctx, &c->playlist_pb, url); if (ret == AVERROR_EXIT) { return ret; } else if (ret < 0) { av_log(c->ctx, AV_LOG_WARNING, "keepalive request failed for '%s', retrying with new connection: %s\n", url, av_err2str(ret)); in = NULL; } } if (!in) { #if 1 AVDictionary *opts = NULL; /* Some HLS servers don't like being sent the range header */ av_dict_set(&opts, "seekable", "0", 0); // broker prior HTTP options that should be consistent across requests av_dict_set(&opts, "user_agent", c->user_agent, 0); av_dict_set(&opts, "cookies", c->cookies, 0); av_dict_set(&opts, "headers", c->headers, 0); av_dict_set(&opts, "http_proxy", c->http_proxy, 0); if (c->http_persistent) av_dict_set(&opts, "multiple_requests", "1", 0); ret = c->ctx->io_open(c->ctx, &in, url, AVIO_FLAG_READ, &opts); av_dict_free(&opts); if (ret < 0) return ret; if (c->http_persistent) c->playlist_pb = in; else close_in = 1; #else ret = open_in(c, &in, url); if (ret < 0) return ret; close_in = 1; #endif } if (av_opt_get(in, "location", AV_OPT_SEARCH_CHILDREN, &new_url) >= 0) url = new_url; read_chomp_line(in, line, sizeof(line)); if (strcmp(line, "#EXTM3U")) { ret = AVERROR_INVALIDDATA; goto fail; } if (pls) { free_segment_list(pls); pls->finished = 0; pls->type = PLS_TYPE_UNSPECIFIED; } while (!avio_feof(in)) { read_chomp_line(in, line, sizeof(line)); if (av_strstart(line, "#EXT-X-STREAM-INF:", &ptr)) { is_variant = 1; memset(&variant_info, 0, sizeof(variant_info)); ff_parse_key_value(ptr, (ff_parse_key_val_cb) handle_variant_args, &variant_info); } else if (av_strstart(line, "#EXT-X-KEY:", &ptr)) { struct key_info info = {{0}}; ff_parse_key_value(ptr, (ff_parse_key_val_cb) handle_key_args, &info); key_type = KEY_NONE; has_iv = 0; if (!strcmp(info.method, "AES-128")) key_type = KEY_AES_128; if (!strcmp(info.method, "SAMPLE-AES")) key_type = KEY_SAMPLE_AES; if (!strncmp(info.iv, "0x", 2) || !strncmp(info.iv, "0X", 2)) { ff_hex_to_data(iv, info.iv + 2); has_iv = 1; } av_strlcpy(key, info.uri, sizeof(key)); } else if (av_strstart(line, "#EXT-X-MEDIA:", &ptr)) { struct rendition_info info = {{0}}; ff_parse_key_value(ptr, (ff_parse_key_val_cb) handle_rendition_args, &info); new_rendition(c, &info, url); } else if (av_strstart(line, "#EXT-X-TARGETDURATION:", &ptr)) { ret = ensure_playlist(c, &pls, url); if (ret < 0) goto fail; pls->target_duration = strtoll(ptr, NULL, 10) * AV_TIME_BASE; } else if (av_strstart(line, "#EXT-X-MEDIA-SEQUENCE:", &ptr)) { ret = ensure_playlist(c, &pls, url); if (ret < 0) goto fail; pls->start_seq_no = atoi(ptr); } else if (av_strstart(line, "#EXT-X-PLAYLIST-TYPE:", &ptr)) { ret = ensure_playlist(c, &pls, url); if (ret < 0) goto fail; if (!strcmp(ptr, "EVENT")) pls->type = PLS_TYPE_EVENT; else if (!strcmp(ptr, "VOD")) pls->type = PLS_TYPE_VOD; } else if (av_strstart(line, "#EXT-X-MAP:", &ptr)) { struct init_section_info info = {{0}}; ret = ensure_playlist(c, &pls, url); if (ret < 0) goto fail; ff_parse_key_value(ptr, (ff_parse_key_val_cb) handle_init_section_args, &info); cur_init_section = new_init_section(pls, &info, url); } else if (av_strstart(line, "#EXT-X-ENDLIST", &ptr)) { if (pls) pls->finished = 1; } else if (av_strstart(line, "#EXTINF:", &ptr)) { is_segment = 1; duration = atof(ptr) * AV_TIME_BASE; } else if (av_strstart(line, "#EXT-X-BYTERANGE:", &ptr)) { seg_size = strtoll(ptr, NULL, 10); ptr = strchr(ptr, '@'); if (ptr) seg_offset = strtoll(ptr+1, NULL, 10); } else if (av_strstart(line, "#", NULL)) { continue; } else if (line[0]) { if (is_variant) { if (!new_variant(c, &variant_info, line, url)) { ret = AVERROR(ENOMEM); goto fail; } is_variant = 0; } if (is_segment) { struct segment *seg; if (!pls) { if (!new_variant(c, 0, url, NULL)) { ret = AVERROR(ENOMEM); goto fail; } pls = c->playlists[c->n_playlists - 1]; } seg = av_malloc(sizeof(struct segment)); if (!seg) { ret = AVERROR(ENOMEM); goto fail; } seg->duration = duration; seg->key_type = key_type; if (has_iv) { memcpy(seg->iv, iv, sizeof(iv)); } else { int seq = pls->start_seq_no + pls->n_segments; memset(seg->iv, 0, sizeof(seg->iv)); AV_WB32(seg->iv + 12, seq); } if (key_type != KEY_NONE) { ff_make_absolute_url(tmp_str, sizeof(tmp_str), url, key); seg->key = av_strdup(tmp_str); if (!seg->key) { av_free(seg); ret = AVERROR(ENOMEM); goto fail; } } else { seg->key = NULL; } ff_make_absolute_url(tmp_str, sizeof(tmp_str), url, line); seg->url = av_strdup(tmp_str); if (!seg->url) { av_free(seg->key); av_free(seg); ret = AVERROR(ENOMEM); goto fail; } dynarray_add(&pls->segments, &pls->n_segments, seg); is_segment = 0; seg->size = seg_size; if (seg_size >= 0) { seg->url_offset = seg_offset; seg_offset += seg_size; seg_size = -1; } else { seg->url_offset = 0; seg_offset = 0; } seg->init_section = cur_init_section; } } } if (pls) pls->last_load_time = av_gettime_relative(); fail: av_free(new_url); if (close_in) ff_format_io_close(c->ctx, &in); return ret; }


static void RENAME(yuv2rgb555_1)(SwsContext *c, const uint16_t *buf0, const uint16_t *ubuf0, const uint16_t *ubuf1, const uint16_t *vbuf0, const uint16_t *vbuf1, const uint16_t *abuf0, uint8_t *dest, int dstW, int uvalpha, enum PixelFormat dstFormat, int flags, int y) { const uint16_t *buf1= buf0; //FIXME needed for RGB1/BGR1 if (uvalpha < 2048) { // note this is not correct (shifts chrominance by 0.5 pixels) but it is a bit faster __asm__ volatile( "mov %%"REG_b", "ESP_OFFSET"(%5) \n\t" "mov %4, %%"REG_b" \n\t" "push %%"REG_BP" \n\t" YSCALEYUV2RGB1(%%REGBP, %5) "pxor %%mm7, %%mm7 \n\t" /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */ #ifdef DITHER1XBPP "paddusb "BLUE_DITHER"(%5), %%mm2 \n\t" "paddusb "GREEN_DITHER"(%5), %%mm4 \n\t" "paddusb "RED_DITHER"(%5), %%mm5 \n\t" #endif WRITERGB15(%%REGb, 8280(%5), %%REGBP) "pop %%"REG_BP" \n\t" "mov "ESP_OFFSET"(%5), %%"REG_b" \n\t" :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest), "a" (&c->redDither) ); } else { __asm__ volatile( "mov %%"REG_b", "ESP_OFFSET"(%5) \n\t" "mov %4, %%"REG_b" \n\t" "push %%"REG_BP" \n\t" YSCALEYUV2RGB1b(%%REGBP, %5) "pxor %%mm7, %%mm7 \n\t" /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */ #ifdef DITHER1XBPP "paddusb "BLUE_DITHER"(%5), %%mm2 \n\t" "paddusb "GREEN_DITHER"(%5), %%mm4 \n\t" "paddusb "RED_DITHER"(%5), %%mm5 \n\t" #endif WRITERGB15(%%REGb, 8280(%5), %%REGBP) "pop %%"REG_BP" \n\t" "mov "ESP_OFFSET"(%5), %%"REG_b" \n\t" :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest), "a" (&c->redDither) ); } }


static int decode_slice(AVCodecContext *avctx, ProresThreadData *td) { ProresContext *ctx = avctx->priv_data; int mb_x_pos = td->x_pos; int mb_y_pos = td->y_pos; int pic_num = ctx->pic_num; int slice_num = td->slice_num; int mbs_per_slice = td->slice_width; const uint8_t *buf; uint8_t *y_data, *u_data, *v_data; AVFrame *pic = avctx->coded_frame; int i, sf, slice_width_factor; int slice_data_size, hdr_size, y_data_size, u_data_size, v_data_size; int y_linesize, u_linesize, v_linesize; buf = ctx->slice_data[slice_num].index; slice_data_size = ctx->slice_data[slice_num + 1].index - buf; slice_width_factor = av_log2(mbs_per_slice); y_data = pic->data[0]; u_data = pic->data[1]; v_data = pic->data[2]; y_linesize = pic->linesize[0]; u_linesize = pic->linesize[1]; v_linesize = pic->linesize[2]; if (pic->interlaced_frame) { if (!(pic_num ^ pic->top_field_first)) { y_data += y_linesize; u_data += u_linesize; v_data += v_linesize; } y_linesize <<= 1; u_linesize <<= 1; v_linesize <<= 1; } if (slice_data_size < 6) { av_log(avctx, AV_LOG_ERROR, "slice data too small\n"); return AVERROR_INVALIDDATA; } /* parse slice header */ hdr_size = buf[0] >> 3; y_data_size = AV_RB16(buf + 2); u_data_size = AV_RB16(buf + 4); v_data_size = slice_data_size - y_data_size - u_data_size - hdr_size; if (v_data_size < 0 || hdr_size < 6) { av_log(avctx, AV_LOG_ERROR, "invalid data size\n"); return AVERROR_INVALIDDATA; } sf = av_clip(buf[1], 1, 224); sf = sf > 128 ? (sf - 96) << 2 : sf; /* scale quantization matrixes according with slice's scale factor */ /* TODO: this can be SIMD-optimized alot */ if (ctx->qmat_changed || sf != ctx->prev_slice_sf) { ctx->prev_slice_sf = sf; for (i = 0; i < 64; i++) { ctx->qmat_luma_scaled[ctx->dsp.idct_permutation[i]] = ctx->qmat_luma[i] * sf; ctx->qmat_chroma_scaled[ctx->dsp.idct_permutation[i]] = ctx->qmat_chroma[i] * sf; } } /* decode luma plane */ decode_slice_plane(ctx, td, buf + hdr_size, y_data_size, (uint16_t*) (y_data + (mb_y_pos << 4) * y_linesize + (mb_x_pos << 5)), y_linesize, mbs_per_slice, 4, slice_width_factor + 2, ctx->qmat_luma_scaled); /* decode U chroma plane */ decode_slice_plane(ctx, td, buf + hdr_size + y_data_size, u_data_size, (uint16_t*) (u_data + (mb_y_pos << 4) * u_linesize + (mb_x_pos << ctx->mb_chroma_factor)), u_linesize, mbs_per_slice, ctx->num_chroma_blocks, slice_width_factor + ctx->chroma_factor - 1, ctx->qmat_chroma_scaled); /* decode V chroma plane */ decode_slice_plane(ctx, td, buf + hdr_size + y_data_size + u_data_size, v_data_size, (uint16_t*) (v_data + (mb_y_pos << 4) * v_linesize + (mb_x_pos << ctx->mb_chroma_factor)), v_linesize, mbs_per_slice, ctx->num_chroma_blocks, slice_width_factor + ctx->chroma_factor - 1, ctx->qmat_chroma_scaled); return 0; }


static av_cold int eightsvx_decode_close(AVCodecContext *avctx) { EightSvxContext *esc = avctx->priv_data; av_freep(&esc->samples); esc->samples_size = 0; esc->samples_idx = 0; return 0; }


static int scale_vaapi_query_formats(AVFilterContext *avctx) { enum AVPixelFormat pix_fmts[] = { AV_PIX_FMT_VAAPI, AV_PIX_FMT_NONE, }; ff_formats_ref(ff_make_format_list(pix_fmts), &avctx->inputs[0]->out_formats); ff_formats_ref(ff_make_format_list(pix_fmts), &avctx->outputs[0]->in_formats); return 0; }


static int decode_frame(FLACContext *s, int alloc_data_size) { int bs_code, sr_code, bps_code, i; int ch_mode, bps, blocksize, samplerate; GetBitContext *gb = &s->gb; /* frame sync code */ skip_bits(&s->gb, 16); /* block size and sample rate codes */ bs_code = get_bits(gb, 4); sr_code = get_bits(gb, 4); /* channels and decorrelation */ ch_mode = get_bits(gb, 4); if (ch_mode < FLAC_MAX_CHANNELS && s->channels == ch_mode+1) { ch_mode = FLAC_CHMODE_INDEPENDENT; } else if (ch_mode > FLAC_CHMODE_MID_SIDE || s->channels != 2) { av_log(s->avctx, AV_LOG_ERROR, "unsupported channel assignment %d (channels=%d)\n", ch_mode, s->channels); return -1; } /* bits per sample */ bps_code = get_bits(gb, 3); if (bps_code == 0) bps= s->bps; else if ((bps_code != 3) && (bps_code != 7)) bps = sample_size_table[bps_code]; else { av_log(s->avctx, AV_LOG_ERROR, "invalid sample size code (%d)\n", bps_code); return -1; } if (bps > 16) { s->avctx->sample_fmt = SAMPLE_FMT_S32; s->sample_shift = 32 - bps; s->is32 = 1; } else { s->avctx->sample_fmt = SAMPLE_FMT_S16; s->sample_shift = 16 - bps; s->is32 = 0; } s->bps = s->avctx->bits_per_raw_sample = bps; /* reserved bit */ if (get_bits1(gb)) { av_log(s->avctx, AV_LOG_ERROR, "broken stream, invalid padding\n"); return -1; } /* sample or frame count */ if (get_utf8(gb) < 0) { av_log(s->avctx, AV_LOG_ERROR, "utf8 fscked\n"); return -1; } /* blocksize */ if (bs_code == 0) { av_log(s->avctx, AV_LOG_ERROR, "reserved blocksize code: 0\n"); return -1; } else if (bs_code == 6) blocksize = get_bits(gb, 8)+1; else if (bs_code == 7) blocksize = get_bits(gb, 16)+1; else blocksize = ff_flac_blocksize_table[bs_code]; if (blocksize > s->max_blocksize) { av_log(s->avctx, AV_LOG_ERROR, "blocksize %d > %d\n", blocksize, s->max_blocksize); return -1; } if (blocksize * s->channels * (s->is32 ? 4 : 2) > alloc_data_size) return -1; /* sample rate */ if (sr_code == 0) samplerate= s->samplerate; else if (sr_code < 12) samplerate = ff_flac_sample_rate_table[sr_code]; else if (sr_code == 12) samplerate = get_bits(gb, 8) * 1000; else if (sr_code == 13) samplerate = get_bits(gb, 16); else if (sr_code == 14) samplerate = get_bits(gb, 16) * 10; else { av_log(s->avctx, AV_LOG_ERROR, "illegal sample rate code %d\n", sr_code); return -1; } /* header CRC-8 check */ skip_bits(gb, 8); if (av_crc(av_crc_get_table(AV_CRC_8_ATM), 0, gb->buffer, get_bits_count(gb)/8)) { av_log(s->avctx, AV_LOG_ERROR, "header crc mismatch\n"); return -1; } s->blocksize = blocksize; s->samplerate = samplerate; s->bps = bps; s->ch_mode = ch_mode; // dump_headers(s->avctx, (FLACStreaminfo *)s); /* subframes */ for (i = 0; i < s->channels; i++) { if (decode_subframe(s, i) < 0) return -1; } align_get_bits(gb); /* frame footer */ skip_bits(gb, 16); /* data crc */ return 0; }


static int ftp_getc(FTPContext *s) { int len; if (s->control_buf_ptr >= s->control_buf_end) { if (s->conn_control_block_flag) return AVERROR_EXIT; len = ffurl_read(s->conn_control, s->control_buffer, CONTROL_BUFFER_SIZE); if (len < 0) { return len; } else if (!len) { return -1; } else { s->control_buf_ptr = s->control_buffer; s->control_buf_end = s->control_buffer + len; } } return *s->control_buf_ptr++; }


static int filter_frame(AVFilterLink *inlink, AVFrame *in) { AVFilterContext *ctx = inlink->dst; HDCDContext *s = ctx->priv; AVFilterLink *outlink = ctx->outputs[0]; AVFrame *out; const int16_t *in_data; int32_t *out_data; int n, c; int detect, packets, pe_packets; out = ff_get_audio_buffer(outlink, in->nb_samples); if (!out) { av_frame_free(&in); return AVERROR(ENOMEM); } av_frame_copy_props(out, in); out->format = outlink->format; in_data = (int16_t*)in->data[0]; out_data = (int32_t*)out->data[0]; for (n = 0; n < in->nb_samples * in->channels; n++) { out_data[n] = in_data[n]; } detect = 0; packets = 0; pe_packets = 0; s->det_errors = 0; for (c = 0; c < inlink->channels; c++) { hdcd_state_t *state = &s->state[c]; hdcd_process(s, state, out_data + c, in->nb_samples, out->channels); if (state->sustain) detect++; packets += state->code_counterA + state->code_counterB; pe_packets += state->count_peak_extend; s->uses_transient_filter |= !!state->count_transient_filter; s->max_gain_adjustment = FFMIN(s->max_gain_adjustment, GAINTOFLOAT(state->max_gain)); s->det_errors += state->code_counterA_almost + state->code_counterB_checkfails + state->code_counterC_unmatched; } if (pe_packets) { /* if every valid packet has used PE, call it permanent */ if (packets == pe_packets) s->peak_extend = HDCD_PE_PERMANENT; else s->peak_extend = HDCD_PE_INTERMITTENT; } else { s->peak_extend = HDCD_PE_NEVER; } /* HDCD is detected if a valid packet is active in all (both) * channels at the same time. */ if (detect == inlink->channels) s->hdcd_detected = 1; s->sample_count += in->nb_samples * in->channels; av_frame_free(&in); return ff_filter_frame(outlink, out); }


static TPMVersion tpm_passthrough_get_tpm_version(TPMBackend *tb) { return TPM_VERSION_1_2; }


static int pci_ich9_ahci_init(PCIDevice *dev) { struct AHCIPCIState *d; d = DO_UPCAST(struct AHCIPCIState, card, dev); pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR); pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA); pci_config_set_revision(d->card.config, 0x02); pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1); d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ pci_config_set_interrupt_pin(d->card.config, 1); /* XXX Software should program this register */ d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ qemu_register_reset(ahci_reset, d); /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ pci_register_bar_simple(&d->card, 5, 0x1000, 0, d->ahci.mem); msi_init(dev, 0x50, 1, true, false); ahci_init(&d->ahci, &dev->qdev, 6); d->ahci.irq = d->card.irq[0]; return 0; }


static void ppc_core99_init(QEMUMachineInitArgs *args) { ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; const char *initrd_filename = args->initrd_filename; const char *boot_device = args->boot_device; PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; MemoryRegion *unin_memory = g_new(MemoryRegion, 1); int linux_boot, i; MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); hwaddr kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem; MemoryRegion *escc_bar = g_new(MemoryRegion, 1); MemoryRegion *ide_mem[3]; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; int machine_arch; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) #ifdef TARGET_PPC64 cpu_model = "970fx"; #else cpu_model = "G4"; #endif for (i = 0; i < smp_cpus; i++) { cpu = cpu_ppc_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } env = &cpu->env; /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(ppc_core99_reset, cpu); } /* allocate RAM */ memory_region_init_ram(ram, "ppc_core99.ram", ram_size); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); /* allocate and load BIOS */ memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE); vmstate_register_ram_global(bios); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000); memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: hw_error("Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99_U3; } else { pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99; } /* init basic PC hardware */ pci_vga_init(pci_bus); escc_mem = escc_init(0, pic[0x25], pic[0x24], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); dbdma = DBDMA_init(&dbdma_mem); /* We only emulate 2 out of 3 IDE controllers for now */ ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]); ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]); cuda_init(&cuda_mem, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem, dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar); if (usb_enabled(machine_arch == ARCH_MAC99_U3)) { pci_create_simple(pci_bus, -1, "pci-ohci"); /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ if (machine_arch == ARCH_MAC99_U3) { usbdevice_create("keyboard"); usbdevice_create("mouse"); } } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(0x2000, 1); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }


static void test_visitor_out_enum(TestOutputVisitorData *data, const void *unused) { QObject *obj; EnumOne i; for (i = 0; i < ENUM_ONE__MAX; i++) { visit_type_EnumOne(data->ov, "unused", &i, &error_abort); obj = visitor_get(data); g_assert(qobject_type(obj) == QTYPE_QSTRING); g_assert_cmpstr(qstring_get_str(qobject_to_qstring(obj)), ==, EnumOne_lookup[i]); visitor_reset(data); } }


static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) { PCIAC97LinkState *d = opaque; AC97LinkState *s = &d->ac97; AC97BusMasterRegs *r = NULL; uint32_t index = addr - s->base[1]; switch (index) { case PI_BDBAR: case PO_BDBAR: case MC_BDBAR: r = &s->bm_regs[GET_BM (index)]; r->bdbar = val & ~3; dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n", GET_BM (index), val, r->bdbar); break; case GLOB_CNT: if (val & GC_WR) warm_reset (s); if (val & GC_CR) cold_reset (s); if (!(val & (GC_WR | GC_CR))) s->glob_cnt = val & GC_VALID_MASK; dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt); break; case GLOB_STA: s->glob_sta &= ~(val & GS_WCLEAR_MASK); s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta); break; default: dolog ("U nabm writel %#x <- %#x\n", addr, val); break; } }


PCIDevice *pci_get_function_0(PCIDevice *pci_dev) { if(pcie_has_upstream_port(pci_dev)) { /* With an upstream PCIe port, we only support 1 device at slot 0 */ return pci_dev->bus->devices[0]; } else { /* Other bus types might support multiple devices at slots 0-31 */ return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; } }


static CharDriverState *qemu_chr_open_stdio(ChardevStdio *opts) { CharDriverState *chr; WinStdioCharState *stdio; DWORD dwMode; int is_console = 0; chr = g_malloc0(sizeof(CharDriverState)); stdio = g_malloc0(sizeof(WinStdioCharState)); stdio->hStdIn = GetStdHandle(STD_INPUT_HANDLE); if (stdio->hStdIn == INVALID_HANDLE_VALUE) { fprintf(stderr, "cannot open stdio: invalid handle\n"); exit(1); } is_console = GetConsoleMode(stdio->hStdIn, &dwMode) != 0; chr->opaque = stdio; chr->chr_write = win_stdio_write; chr->chr_close = win_stdio_close; if (is_console) { if (qemu_add_wait_object(stdio->hStdIn, win_stdio_wait_func, chr)) { fprintf(stderr, "qemu_add_wait_object: failed\n"); } } else { DWORD dwId; stdio->hInputReadyEvent = CreateEvent(NULL, FALSE, FALSE, NULL); stdio->hInputDoneEvent = CreateEvent(NULL, FALSE, FALSE, NULL); stdio->hInputThread = CreateThread(NULL, 0, win_stdio_thread, chr, 0, &dwId); if (stdio->hInputThread == INVALID_HANDLE_VALUE || stdio->hInputReadyEvent == INVALID_HANDLE_VALUE || stdio->hInputDoneEvent == INVALID_HANDLE_VALUE) { fprintf(stderr, "cannot create stdio thread or event\n"); exit(1); } if (qemu_add_wait_object(stdio->hInputReadyEvent, win_stdio_thread_wait_func, chr)) { fprintf(stderr, "qemu_add_wait_object: failed\n"); } } dwMode |= ENABLE_LINE_INPUT; if (is_console) { /* set the terminal in raw mode */ /* ENABLE_QUICK_EDIT_MODE | ENABLE_EXTENDED_FLAGS */ dwMode |= ENABLE_PROCESSED_INPUT; } SetConsoleMode(stdio->hStdIn, dwMode); chr->chr_set_echo = qemu_chr_set_echo_win_stdio; qemu_chr_fe_set_echo(chr, false); return chr; }


static uint64_t spapr_io_read(void *opaque, hwaddr addr, unsigned size) { switch (size) { case 1: return cpu_inb(addr); case 2: return cpu_inw(addr); case 4: return cpu_inl(addr); } assert(0); }


av_cold void ff_sws_init_input_funcs(SwsContext *c) { enum AVPixelFormat srcFormat = c->srcFormat; c->chrToYV12 = NULL; switch (srcFormat) { case AV_PIX_FMT_YUYV422: c->chrToYV12 = yuy2ToUV_c; break; case AV_PIX_FMT_YVYU422: c->chrToYV12 = yvy2ToUV_c; break; case AV_PIX_FMT_UYVY422: c->chrToYV12 = uyvyToUV_c; break; case AV_PIX_FMT_NV12: c->chrToYV12 = nv12ToUV_c; break; case AV_PIX_FMT_NV21: c->chrToYV12 = nv21ToUV_c; break; case AV_PIX_FMT_RGB8: case AV_PIX_FMT_BGR8: case AV_PIX_FMT_PAL8: case AV_PIX_FMT_BGR4_BYTE: case AV_PIX_FMT_RGB4_BYTE: c->chrToYV12 = palToUV_c; break; case AV_PIX_FMT_GBRP9LE: c->readChrPlanar = planar_rgb9le_to_uv; break; case AV_PIX_FMT_GBRP10LE: c->readChrPlanar = planar_rgb10le_to_uv; break; case AV_PIX_FMT_GBRAP16LE: case AV_PIX_FMT_GBRP16LE: c->readChrPlanar = planar_rgb16le_to_uv; break; case AV_PIX_FMT_GBRP9BE: c->readChrPlanar = planar_rgb9be_to_uv; break; case AV_PIX_FMT_GBRP10BE: c->readChrPlanar = planar_rgb10be_to_uv; break; case AV_PIX_FMT_GBRAP16BE: case AV_PIX_FMT_GBRP16BE: c->readChrPlanar = planar_rgb16be_to_uv; break; case AV_PIX_FMT_GBRAP: case AV_PIX_FMT_GBRP: c->readChrPlanar = planar_rgb_to_uv; break; #if HAVE_BIGENDIAN case AV_PIX_FMT_YUV444P9LE: case AV_PIX_FMT_YUV422P9LE: case AV_PIX_FMT_YUV420P9LE: case AV_PIX_FMT_YUV422P10LE: case AV_PIX_FMT_YUV444P10LE: case AV_PIX_FMT_YUV420P10LE: case AV_PIX_FMT_YUV420P16LE: case AV_PIX_FMT_YUV422P16LE: case AV_PIX_FMT_YUV444P16LE: case AV_PIX_FMT_YUVA444P9LE: case AV_PIX_FMT_YUVA422P9LE: case AV_PIX_FMT_YUVA420P9LE: case AV_PIX_FMT_YUVA422P10LE: case AV_PIX_FMT_YUVA444P10LE: case AV_PIX_FMT_YUVA420P10LE: case AV_PIX_FMT_YUVA420P16LE: case AV_PIX_FMT_YUVA422P16LE: case AV_PIX_FMT_YUVA444P16LE: c->chrToYV12 = bswap16UV_c; break; #else case AV_PIX_FMT_YUV444P9BE: case AV_PIX_FMT_YUV422P9BE: case AV_PIX_FMT_YUV420P9BE: case AV_PIX_FMT_YUV444P10BE: case AV_PIX_FMT_YUV422P10BE: case AV_PIX_FMT_YUV420P10BE: case AV_PIX_FMT_YUV420P16BE: case AV_PIX_FMT_YUV422P16BE: case AV_PIX_FMT_YUV444P16BE: case AV_PIX_FMT_YUVA444P9BE: case AV_PIX_FMT_YUVA422P9BE: case AV_PIX_FMT_YUVA420P9BE: case AV_PIX_FMT_YUVA422P10BE: case AV_PIX_FMT_YUVA444P10BE: case AV_PIX_FMT_YUVA420P10BE: case AV_PIX_FMT_YUVA420P16BE: case AV_PIX_FMT_YUVA422P16BE: case AV_PIX_FMT_YUVA444P16BE: c->chrToYV12 = bswap16UV_c; break; #endif case AV_PIX_FMT_P010LE: c->chrToYV12 = p010LEToUV_c; break; case AV_PIX_FMT_P010BE: c->chrToYV12 = p010BEToUV_c; break; } if (c->chrSrcHSubSample) { switch (srcFormat) { case AV_PIX_FMT_RGB48BE: c->chrToYV12 = rgb48BEToUV_half_c; break; case AV_PIX_FMT_RGB48LE: c->chrToYV12 = rgb48LEToUV_half_c; break; case AV_PIX_FMT_BGR48BE: c->chrToYV12 = bgr48BEToUV_half_c; break; case AV_PIX_FMT_BGR48LE: c->chrToYV12 = bgr48LEToUV_half_c; break; case AV_PIX_FMT_RGB32: c->chrToYV12 = bgr32ToUV_half_c; break; case AV_PIX_FMT_RGB32_1: c->chrToYV12 = bgr321ToUV_half_c; break; case AV_PIX_FMT_BGR24: c->chrToYV12 = bgr24ToUV_half_c; break; case AV_PIX_FMT_BGR565LE: c->chrToYV12 = bgr16leToUV_half_c; break; case AV_PIX_FMT_BGR565BE: c->chrToYV12 = bgr16beToUV_half_c; break; case AV_PIX_FMT_BGR555LE: c->chrToYV12 = bgr15leToUV_half_c; break; case AV_PIX_FMT_BGR555BE: c->chrToYV12 = bgr15beToUV_half_c; break; case AV_PIX_FMT_BGR444LE: c->chrToYV12 = bgr12leToUV_half_c; break; case AV_PIX_FMT_BGR444BE: c->chrToYV12 = bgr12beToUV_half_c; break; case AV_PIX_FMT_BGR32: c->chrToYV12 = rgb32ToUV_half_c; break; case AV_PIX_FMT_BGR32_1: c->chrToYV12 = rgb321ToUV_half_c; break; case AV_PIX_FMT_RGB24: c->chrToYV12 = rgb24ToUV_half_c; break; case AV_PIX_FMT_RGB565LE: c->chrToYV12 = rgb16leToUV_half_c; break; case AV_PIX_FMT_RGB565BE: c->chrToYV12 = rgb16beToUV_half_c; break; case AV_PIX_FMT_RGB555LE: c->chrToYV12 = rgb15leToUV_half_c; break; case AV_PIX_FMT_RGB555BE: c->chrToYV12 = rgb15beToUV_half_c; break; case AV_PIX_FMT_RGB444LE: c->chrToYV12 = rgb12leToUV_half_c; break; case AV_PIX_FMT_RGB444BE: c->chrToYV12 = rgb12beToUV_half_c; break; } } else { switch (srcFormat) { case AV_PIX_FMT_RGB48BE: c->chrToYV12 = rgb48BEToUV_c; break; case AV_PIX_FMT_RGB48LE: c->chrToYV12 = rgb48LEToUV_c; break; case AV_PIX_FMT_BGR48BE: c->chrToYV12 = bgr48BEToUV_c; break; case AV_PIX_FMT_BGR48LE: c->chrToYV12 = bgr48LEToUV_c; break; case AV_PIX_FMT_RGB32: c->chrToYV12 = bgr32ToUV_c; break; case AV_PIX_FMT_RGB32_1: c->chrToYV12 = bgr321ToUV_c; break; case AV_PIX_FMT_BGR24: c->chrToYV12 = bgr24ToUV_c; break; case AV_PIX_FMT_BGR565LE: c->chrToYV12 = bgr16leToUV_c; break; case AV_PIX_FMT_BGR565BE: c->chrToYV12 = bgr16beToUV_c; break; case AV_PIX_FMT_BGR555LE: c->chrToYV12 = bgr15leToUV_c; break; case AV_PIX_FMT_BGR555BE: c->chrToYV12 = bgr15beToUV_c; break; case AV_PIX_FMT_BGR444LE: c->chrToYV12 = bgr12leToUV_c; break; case AV_PIX_FMT_BGR444BE: c->chrToYV12 = bgr12beToUV_c; break; case AV_PIX_FMT_BGR32: c->chrToYV12 = rgb32ToUV_c; break; case AV_PIX_FMT_BGR32_1: c->chrToYV12 = rgb321ToUV_c; break; case AV_PIX_FMT_RGB24: c->chrToYV12 = rgb24ToUV_c; break; case AV_PIX_FMT_RGB565LE: c->chrToYV12 = rgb16leToUV_c; break; case AV_PIX_FMT_RGB565BE: c->chrToYV12 = rgb16beToUV_c; break; case AV_PIX_FMT_RGB555LE: c->chrToYV12 = rgb15leToUV_c; break; case AV_PIX_FMT_RGB555BE: c->chrToYV12 = rgb15beToUV_c; break; case AV_PIX_FMT_RGB444LE: c->chrToYV12 = rgb12leToUV_c; break; case AV_PIX_FMT_RGB444BE: c->chrToYV12 = rgb12beToUV_c; break; } } c->lumToYV12 = NULL; c->alpToYV12 = NULL; switch (srcFormat) { case AV_PIX_FMT_GBRP9LE: c->readLumPlanar = planar_rgb9le_to_y; break; case AV_PIX_FMT_GBRP10LE: c->readLumPlanar = planar_rgb10le_to_y; break; case AV_PIX_FMT_GBRAP16LE: case AV_PIX_FMT_GBRP16LE: c->readLumPlanar = planar_rgb16le_to_y; break; case AV_PIX_FMT_GBRP9BE: c->readLumPlanar = planar_rgb9be_to_y; break; case AV_PIX_FMT_GBRP10BE: c->readLumPlanar = planar_rgb10be_to_y; break; case AV_PIX_FMT_GBRAP16BE: case AV_PIX_FMT_GBRP16BE: c->readLumPlanar = planar_rgb16be_to_y; break; case AV_PIX_FMT_GBRAP: c->readAlpPlanar = planar_rgb_to_a; case AV_PIX_FMT_GBRP: c->readLumPlanar = planar_rgb_to_y; break; #if HAVE_BIGENDIAN case AV_PIX_FMT_YUV444P9LE: case AV_PIX_FMT_YUV422P9LE: case AV_PIX_FMT_YUV420P9LE: case AV_PIX_FMT_YUV444P10LE: case AV_PIX_FMT_YUV422P10LE: case AV_PIX_FMT_YUV420P10LE: case AV_PIX_FMT_YUV420P16LE: case AV_PIX_FMT_YUV422P16LE: case AV_PIX_FMT_YUV444P16LE: case AV_PIX_FMT_GRAY16LE: c->lumToYV12 = bswap16Y_c; break; case AV_PIX_FMT_YUVA444P9LE: case AV_PIX_FMT_YUVA422P9LE: case AV_PIX_FMT_YUVA420P9LE: case AV_PIX_FMT_YUVA444P10LE: case AV_PIX_FMT_YUVA422P10LE: case AV_PIX_FMT_YUVA420P10LE: case AV_PIX_FMT_YUVA420P16LE: case AV_PIX_FMT_YUVA422P16LE: case AV_PIX_FMT_YUVA444P16LE: c->lumToYV12 = bswap16Y_c; c->alpToYV12 = bswap16Y_c; break; #else case AV_PIX_FMT_YUV444P9BE: case AV_PIX_FMT_YUV422P9BE: case AV_PIX_FMT_YUV420P9BE: case AV_PIX_FMT_YUV444P10BE: case AV_PIX_FMT_YUV422P10BE: case AV_PIX_FMT_YUV420P10BE: case AV_PIX_FMT_YUV420P16BE: case AV_PIX_FMT_YUV422P16BE: case AV_PIX_FMT_YUV444P16BE: case AV_PIX_FMT_GRAY16BE: c->lumToYV12 = bswap16Y_c; break; case AV_PIX_FMT_YUVA444P9BE: case AV_PIX_FMT_YUVA422P9BE: case AV_PIX_FMT_YUVA420P9BE: case AV_PIX_FMT_YUVA444P10BE: case AV_PIX_FMT_YUVA422P10BE: case AV_PIX_FMT_YUVA420P10BE: case AV_PIX_FMT_YUVA420P16BE: case AV_PIX_FMT_YUVA422P16BE: case AV_PIX_FMT_YUVA444P16BE: c->lumToYV12 = bswap16Y_c; c->alpToYV12 = bswap16Y_c; break; #endif case AV_PIX_FMT_YA16LE: c->lumToYV12 = read_ya16le_gray_c; c->alpToYV12 = read_ya16le_alpha_c; break; case AV_PIX_FMT_YA16BE: c->lumToYV12 = read_ya16be_gray_c; c->alpToYV12 = read_ya16be_alpha_c; break; case AV_PIX_FMT_YUYV422: case AV_PIX_FMT_YVYU422: case AV_PIX_FMT_YA8: c->lumToYV12 = yuy2ToY_c; break; case AV_PIX_FMT_UYVY422: c->lumToYV12 = uyvyToY_c; break; case AV_PIX_FMT_BGR24: c->lumToYV12 = bgr24ToY_c; break; case AV_PIX_FMT_BGR565LE: c->lumToYV12 = bgr16leToY_c; break; case AV_PIX_FMT_BGR565BE: c->lumToYV12 = bgr16beToY_c; break; case AV_PIX_FMT_BGR555LE: c->lumToYV12 = bgr15leToY_c; break; case AV_PIX_FMT_BGR555BE: c->lumToYV12 = bgr15beToY_c; break; case AV_PIX_FMT_BGR444LE: c->lumToYV12 = bgr12leToY_c; break; case AV_PIX_FMT_BGR444BE: c->lumToYV12 = bgr12beToY_c; break; case AV_PIX_FMT_RGB24: c->lumToYV12 = rgb24ToY_c; break; case AV_PIX_FMT_RGB565LE: c->lumToYV12 = rgb16leToY_c; break; case AV_PIX_FMT_RGB565BE: c->lumToYV12 = rgb16beToY_c; break; case AV_PIX_FMT_RGB555LE: c->lumToYV12 = rgb15leToY_c; break; case AV_PIX_FMT_RGB555BE: c->lumToYV12 = rgb15beToY_c; break; case AV_PIX_FMT_RGB444LE: c->lumToYV12 = rgb12leToY_c; break; case AV_PIX_FMT_RGB444BE: c->lumToYV12 = rgb12beToY_c; break; case AV_PIX_FMT_RGB8: case AV_PIX_FMT_BGR8: case AV_PIX_FMT_PAL8: case AV_PIX_FMT_BGR4_BYTE: case AV_PIX_FMT_RGB4_BYTE: c->lumToYV12 = palToY_c; break; case AV_PIX_FMT_MONOBLACK: c->lumToYV12 = monoblack2Y_c; break; case AV_PIX_FMT_MONOWHITE: c->lumToYV12 = monowhite2Y_c; break; case AV_PIX_FMT_RGB32: c->lumToYV12 = bgr32ToY_c; break; case AV_PIX_FMT_RGB32_1: c->lumToYV12 = bgr321ToY_c; break; case AV_PIX_FMT_BGR32: c->lumToYV12 = rgb32ToY_c; break; case AV_PIX_FMT_BGR32_1: c->lumToYV12 = rgb321ToY_c; break; case AV_PIX_FMT_RGB48BE: c->lumToYV12 = rgb48BEToY_c; break; case AV_PIX_FMT_RGB48LE: c->lumToYV12 = rgb48LEToY_c; break; case AV_PIX_FMT_BGR48BE: c->lumToYV12 = bgr48BEToY_c; break; case AV_PIX_FMT_BGR48LE: c->lumToYV12 = bgr48LEToY_c; break; case AV_PIX_FMT_P010LE: c->lumToYV12 = p010LEToY_c; break; case AV_PIX_FMT_P010BE: c->lumToYV12 = p010BEToY_c; break; } if (c->alpPixBuf) { switch (srcFormat) { case AV_PIX_FMT_BGRA: case AV_PIX_FMT_RGBA: c->alpToYV12 = rgbaToA_c; break; case AV_PIX_FMT_ABGR: case AV_PIX_FMT_ARGB: c->alpToYV12 = abgrToA_c; break; case AV_PIX_FMT_YA8: c->alpToYV12 = uyvyToY_c; break; } } }


int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi) { BlockDriver *drv = bs->drv; if (!drv) return -ENOMEDIUM; if (!drv->bdrv_get_info) return -ENOTSUP; memset(bdi, 0, sizeof(*bdi)); return drv->bdrv_get_info(bs, bdi); }


static int loadvm_postcopy_handle_advise(MigrationIncomingState *mis) { PostcopyState ps = postcopy_state_set(POSTCOPY_INCOMING_ADVISE); uint64_t remote_pagesize_summary, local_pagesize_summary, remote_tps; trace_loadvm_postcopy_handle_advise(); if (ps != POSTCOPY_INCOMING_NONE) { error_report("CMD_POSTCOPY_ADVISE in wrong postcopy state (%d)", ps); return -1; } if (!migrate_postcopy_ram()) { return 0; } if (!postcopy_ram_supported_by_host()) { postcopy_state_set(POSTCOPY_INCOMING_NONE); return -1; } remote_pagesize_summary = qemu_get_be64(mis->from_src_file); local_pagesize_summary = ram_pagesize_summary(); if (remote_pagesize_summary != local_pagesize_summary) { /* * This detects two potential causes of mismatch: * a) A mismatch in host page sizes * Some combinations of mismatch are probably possible but it gets * a bit more complicated. In particular we need to place whole * host pages on the dest at once, and we need to ensure that we * handle dirtying to make sure we never end up sending part of * a hostpage on it's own. * b) The use of different huge page sizes on source/destination * a more fine grain test is performed during RAM block migration * but this test here causes a nice early clear failure, and * also fails when passed to an older qemu that doesn't * do huge pages. */ error_report("Postcopy needs matching RAM page sizes (s=%" PRIx64 " d=%" PRIx64 ")", remote_pagesize_summary, local_pagesize_summary); return -1; } remote_tps = qemu_get_be64(mis->from_src_file); if (remote_tps != qemu_target_page_size()) { /* * Again, some differences could be dealt with, but for now keep it * simple. */ error_report("Postcopy needs matching target page sizes (s=%d d=%zd)", (int)remote_tps, qemu_target_page_size()); return -1; } if (ram_postcopy_incoming_init(mis)) { return -1; } postcopy_state_set(POSTCOPY_INCOMING_ADVISE); return 0; }


coroutine_fn iscsi_co_discard(BlockDriverState *bs, int64_t sector_num, int nb_sectors) { IscsiLun *iscsilun = bs->opaque; struct IscsiTask iTask; struct unmap_list list; uint32_t nb_blocks; uint32_t max_unmap; if (!is_request_lun_aligned(sector_num, nb_sectors, iscsilun)) { return -EINVAL; } if (!iscsilun->lbp.lbpu) { /* UNMAP is not supported by the target */ return 0; } list.lba = sector_qemu2lun(sector_num, iscsilun); nb_blocks = sector_qemu2lun(nb_sectors, iscsilun); max_unmap = iscsilun->bl.max_unmap; if (max_unmap == 0xffffffff) { max_unmap = ISCSI_MAX_UNMAP; } while (nb_blocks > 0) { iscsi_co_init_iscsitask(iscsilun, &iTask); list.num = nb_blocks; if (list.num > max_unmap) { list.num = max_unmap; } retry: if (iscsi_unmap_task(iscsilun->iscsi, iscsilun->lun, 0, 0, &list, 1, iscsi_co_generic_cb, &iTask) == NULL) { return -EIO; } while (!iTask.complete) { iscsi_set_events(iscsilun); qemu_coroutine_yield(); } if (iTask.task != NULL) { scsi_free_scsi_task(iTask.task); iTask.task = NULL; } if (iTask.do_retry) { goto retry; } if (iTask.status == SCSI_STATUS_CHECK_CONDITION) { /* the target might fail with a check condition if it is not happy with the alignment of the UNMAP request we silently fail in this case */ return 0; } if (iTask.status != SCSI_STATUS_GOOD) { return -EIO; } list.lba += list.num; nb_blocks -= list.num; } return 0; }


ssize_t qemu_sendv_packet(VLANClientState *sender, const struct iovec *iov, int iovcnt) { VLANState *vlan = sender->vlan; VLANClientState *vc; VLANPacket *packet; ssize_t max_len = 0; int i; if (sender->link_down) return calc_iov_length(iov, iovcnt); if (vlan->delivering) { max_len = calc_iov_length(iov, iovcnt); packet = qemu_malloc(sizeof(VLANPacket) + max_len); packet->next = vlan->send_queue; packet->sender = sender; packet->size = 0; for (i = 0; i < iovcnt; i++) { size_t len = iov[i].iov_len; memcpy(packet->data + packet->size, iov[i].iov_base, len); packet->size += len; } vlan->send_queue = packet; } else { vlan->delivering = 1; for (vc = vlan->first_client; vc != NULL; vc = vc->next) { ssize_t len = 0; if (vc == sender) { continue; } if (vc->link_down) { len = calc_iov_length(iov, iovcnt); } else if (vc->receive_iov) { len = vc->receive_iov(vc->opaque, iov, iovcnt); } else if (vc->receive) { len = vc_sendv_compat(vc, iov, iovcnt); } max_len = MAX(max_len, len); } while ((packet = vlan->send_queue) != NULL) { vlan->send_queue = packet->next; qemu_deliver_packet(packet->sender, packet->data, packet->size); qemu_free(packet); } vlan->delivering = 0; } return max_len; }


uint64_t float64_to_uint64 (float64 a STATUS_PARAM) { int64_t v; v = int64_to_float64(INT64_MIN STATUS_VAR); v = float64_to_int64((a + v) STATUS_VAR); return v - INT64_MIN; }


static void xics_realize(DeviceState *dev, Error **errp) { XICSState *icp = XICS(dev); ICSState *ics = icp->ics; Error *error = NULL; int i; if (!icp->nr_servers) { error_setg(errp, "Number of servers needs to be greater 0"); return; } /* Registration of global state belongs into realize */ spapr_rtas_register("ibm,set-xive", rtas_set_xive); spapr_rtas_register("ibm,get-xive", rtas_get_xive); spapr_rtas_register("ibm,int-off", rtas_int_off); spapr_rtas_register("ibm,int-on", rtas_int_on); spapr_register_hypercall(H_CPPR, h_cppr); spapr_register_hypercall(H_IPI, h_ipi); spapr_register_hypercall(H_XIRR, h_xirr); spapr_register_hypercall(H_EOI, h_eoi); ics->nr_irqs = icp->nr_irqs; ics->offset = XICS_IRQ_BASE; ics->icp = icp; object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); if (error) { error_propagate(errp, error); return; } icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); for (i = 0; i < icp->nr_servers; i++) { char buffer[32]; object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); snprintf(buffer, sizeof(buffer), "icp[%d]", i); object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), NULL); object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); if (error) { error_propagate(errp, error); return; } } }


static void common_init(MpegEncContext * s) { static int inited=0; switch(s->msmpeg4_version){ case 1: case 2: s->y_dc_scale_table= s->c_dc_scale_table= ff_mpeg1_dc_scale_table; break; case 3: if(s->workaround_bugs){ s->y_dc_scale_table= old_ff_y_dc_scale_table; s->c_dc_scale_table= old_ff_c_dc_scale_table; } else{ s->y_dc_scale_table= ff_mpeg4_y_dc_scale_table; s->c_dc_scale_table= ff_mpeg4_c_dc_scale_table; } break; case 4: case 5: s->y_dc_scale_table= wmv1_y_dc_scale_table; s->c_dc_scale_table= wmv1_c_dc_scale_table; break; #if defined(CONFIG_WMV3_DECODER)||defined(CONFIG_VC1_DECODER) case 6: s->y_dc_scale_table= wmv3_dc_scale_table; s->c_dc_scale_table= wmv3_dc_scale_table; break; #endif } if(s->msmpeg4_version>=4){ ff_init_scantable(s->dsp.idct_permutation, &s->intra_scantable , wmv1_scantable[1]); ff_init_scantable(s->dsp.idct_permutation, &s->intra_h_scantable, wmv1_scantable[2]); ff_init_scantable(s->dsp.idct_permutation, &s->intra_v_scantable, wmv1_scantable[3]); ff_init_scantable(s->dsp.idct_permutation, &s->inter_scantable , wmv1_scantable[0]); } //Note the default tables are set in common_init in mpegvideo.c if(!inited){ inited=1; init_h263_dc_for_msmpeg4(); } }


static void get_bit(Object *obj, Visitor *v, void *opaque, const char *name, Error **errp) { DeviceState *dev = DEVICE(obj); Property *prop = opaque; uint32_t *p = qdev_get_prop_ptr(dev, prop); bool value = (*p & qdev_get_prop_mask(prop)) != 0; visit_type_bool(v, &value, name, errp); }


static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr) { VirtIODevice *vdev = proxy->vdev; uint32_t ret = 0xFFFFFFFF; switch (addr) { case VIRTIO_PCI_HOST_FEATURES: ret = vdev->get_features(vdev); ret |= vdev->binding->get_features(proxy); break; case VIRTIO_PCI_GUEST_FEATURES: ret = vdev->guest_features; break; case VIRTIO_PCI_QUEUE_PFN: ret = virtio_queue_get_addr(vdev, vdev->queue_sel) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT; break; case VIRTIO_PCI_QUEUE_NUM: ret = virtio_queue_get_num(vdev, vdev->queue_sel); break; case VIRTIO_PCI_QUEUE_SEL: ret = vdev->queue_sel; break; case VIRTIO_PCI_STATUS: ret = vdev->status; break; case VIRTIO_PCI_ISR: /* reading from the ISR also clears it. */ ret = vdev->isr; vdev->isr = 0; qemu_set_irq(proxy->pci_dev.irq[0], 0); break; case VIRTIO_MSI_CONFIG_VECTOR: ret = vdev->config_vector; break; case VIRTIO_MSI_QUEUE_VECTOR: ret = virtio_queue_vector(vdev, vdev->queue_sel); break; default: break; } return ret; }


static uint64_t onenand_read(void *opaque, hwaddr addr, unsigned size) { OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; switch (offset) { case 0x0000 ... 0xc000: return lduw_le_p(s->boot[0] + addr); case 0xf000: /* Manufacturer ID */ return s->id.man; case 0xf001: /* Device ID */ return s->id.dev; case 0xf002: /* Version ID */ return s->id.ver; /* TODO: get the following values from a real chip! */ case 0xf003: /* Data Buffer size */ return 1 << PAGE_SHIFT; case 0xf004: /* Boot Buffer size */ return 0x200; case 0xf005: /* Amount of buffers */ return 1 | (2 << 8); case 0xf006: /* Technology */ return 0; case 0xf100 ... 0xf107: /* Start addresses */ return s->addr[offset - 0xf100]; case 0xf200: /* Start buffer */ return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); case 0xf220: /* Command */ return s->command; case 0xf221: /* System Configuration 1 */ return s->config[0] & 0xffe0; case 0xf222: /* System Configuration 2 */ return s->config[1]; case 0xf240: /* Controller Status */ return s->status; case 0xf241: /* Interrupt */ return s->intstatus; case 0xf24c: /* Unlock Start Block Address */ return s->unladdr[0]; case 0xf24d: /* Unlock End Block Address */ return s->unladdr[1]; case 0xf24e: /* Write Protection Status */ return s->wpstatus; case 0xff00: /* ECC Status */ return 0x00; case 0xff01: /* ECC Result of main area data */ case 0xff02: /* ECC Result of spare area data */ case 0xff03: /* ECC Result of main area data */ case 0xff04: /* ECC Result of spare area data */ hw_error("%s: imeplement ECC\n", __FUNCTION__); return 0x0000; } fprintf(stderr, "%s: unknown OneNAND register %x\n", __FUNCTION__, offset); return 0; }


static int handle_copied(BlockDriverState *bs, uint64_t guest_offset, uint64_t *host_offset, uint64_t *bytes, QCowL2Meta **m) { BDRVQcow2State *s = bs->opaque; int l2_index; uint64_t cluster_offset; uint64_t *l2_table; unsigned int nb_clusters; unsigned int keep_clusters; int ret; trace_qcow2_handle_copied(qemu_coroutine_self(), guest_offset, *host_offset, *bytes); assert(*host_offset == 0 || offset_into_cluster(s, guest_offset) == offset_into_cluster(s, *host_offset)); /* * Calculate the number of clusters to look for. We stop at L2 table * boundaries to keep things simple. */ nb_clusters = size_to_clusters(s, offset_into_cluster(s, guest_offset) + *bytes); l2_index = offset_to_l2_index(s, guest_offset); nb_clusters = MIN(nb_clusters, s->l2_size - l2_index); /* Find L2 entry for the first involved cluster */ ret = get_cluster_table(bs, guest_offset, &l2_table, &l2_index); if (ret < 0) { return ret; } cluster_offset = be64_to_cpu(l2_table[l2_index]); /* Check how many clusters are already allocated and don't need COW */ if (qcow2_get_cluster_type(cluster_offset) == QCOW2_CLUSTER_NORMAL && (cluster_offset & QCOW_OFLAG_COPIED)) { /* If a specific host_offset is required, check it */ bool offset_matches = (cluster_offset & L2E_OFFSET_MASK) == *host_offset; if (offset_into_cluster(s, cluster_offset & L2E_OFFSET_MASK)) { qcow2_signal_corruption(bs, true, -1, -1, "Data cluster offset " "%#llx unaligned (guest offset: %#" PRIx64 ")", cluster_offset & L2E_OFFSET_MASK, guest_offset); ret = -EIO; goto out; } if (*host_offset != 0 && !offset_matches) { *bytes = 0; ret = 0; goto out; } /* We keep all QCOW_OFLAG_COPIED clusters */ keep_clusters = count_contiguous_clusters(nb_clusters, s->cluster_size, &l2_table[l2_index], QCOW_OFLAG_COPIED | QCOW_OFLAG_ZERO); assert(keep_clusters <= nb_clusters); *bytes = MIN(*bytes, keep_clusters * s->cluster_size - offset_into_cluster(s, guest_offset)); ret = 1; } else { ret = 0; } /* Cleanup */ out: qcow2_cache_put(bs, s->l2_table_cache, (void **) &l2_table); /* Only return a host offset if we actually made progress. Otherwise we * would make requirements for handle_alloc() that it can't fulfill */ if (ret > 0) { *host_offset = (cluster_offset & L2E_OFFSET_MASK) + offset_into_cluster(s, guest_offset); } return ret; }