static ssize_t gem_receive(VLANClientState *nc, const uint8_t *buf, size_t size) { unsigned desc[2]; target_phys_addr_t packet_desc_addr, last_desc_addr; GemState *s; unsigned rxbufsize, bytes_to_copy; unsigned rxbuf_offset; uint8_t rxbuf[2048]; uint8_t *rxbuf_ptr; s = DO_UPCAST(NICState, nc, nc)->opaque; /* Do nothing if receive is not enabled. */ if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { return -1; } /* Is this destination MAC address "for us" ? */ if (gem_mac_address_filter(s, buf) == GEM_RX_REJECT) { return -1; } /* Discard packets with receive length error enabled ? */ if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { unsigned type_len; /* Fish the ethertype / length field out of the RX packet */ type_len = buf[12] << 8 | buf[13]; /* It is a length field, not an ethertype */ if (type_len < 0x600) { if (size < type_len) { /* discard */ return -1; } } } /* * Determine configured receive buffer offset (probably 0) */ rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> GEM_NWCFG_BUFF_OFST_S; /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. */ rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; bytes_to_copy = size; /* Strip of FCS field ? (usually yes) */ if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { rxbuf_ptr = (void *)buf; } else { unsigned crc_val; int crc_offset; /* The application wants the FCS field, which QEMU does not provide. * We must try and caclculate one. */ memcpy(rxbuf, buf, size); memset(rxbuf + size, 0, sizeof(rxbuf - size)); rxbuf_ptr = rxbuf; crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); if (size < 60) { crc_offset = 60; } else { crc_offset = size; } memcpy(rxbuf + crc_offset, &crc_val, sizeof(crc_val)); bytes_to_copy += 4; size += 4; } /* Pad to minimum length */ if (size < 64) { size = 64; } DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); packet_desc_addr = s->rx_desc_addr; while (1) { DB_PRINT("read descriptor 0x%x\n", packet_desc_addr); /* read current descriptor */ cpu_physical_memory_read(packet_desc_addr, (uint8_t *)&desc[0], sizeof(desc)); /* Descriptor owned by software ? */ if (rx_desc_get_ownership(desc) == 1) { DB_PRINT("descriptor 0x%x owned by sw.\n", packet_desc_addr); s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; /* Handle interrupt consequences */ gem_update_int_status(s); return -1; } DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), rx_desc_get_buffer(desc)); /* * Let's have QEMU lend a helping hand. */ if (rx_desc_get_buffer(desc) == 0) { DB_PRINT("Invalid RX buffer (NULL) for descriptor 0x%x\n", packet_desc_addr); break; } /* Copy packet data to emulated DMA buffer */ cpu_physical_memory_write(rx_desc_get_buffer(desc) + rxbuf_offset, rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); if (bytes_to_copy == 0) { break; } /* Next descriptor */ if (rx_desc_get_wrap(desc)) { packet_desc_addr = s->regs[GEM_RXQBASE]; } else { packet_desc_addr += 8; } } DB_PRINT("set length: %ld, EOF on descriptor 0x%x\n", size, (unsigned)packet_desc_addr); /* Update last descriptor with EOF and total length */ rx_desc_set_eof(desc); rx_desc_set_length(desc, size); cpu_physical_memory_write(packet_desc_addr, (uint8_t *)&desc[0], sizeof(desc)); /* Advance RX packet descriptor Q */ last_desc_addr = packet_desc_addr; packet_desc_addr = s->rx_desc_addr; s->rx_desc_addr = last_desc_addr; if (rx_desc_get_wrap(desc)) { s->rx_desc_addr = s->regs[GEM_RXQBASE]; } else { s->rx_desc_addr += 8; } DB_PRINT("set SOF, OWN on descriptor 0x%08x\n", packet_desc_addr); /* Count it */ gem_receive_updatestats(s, buf, size); /* Update first descriptor (which could also be the last) */ /* read descriptor */ cpu_physical_memory_read(packet_desc_addr, (uint8_t *)&desc[0], sizeof(desc)); rx_desc_set_sof(desc); rx_desc_set_ownership(desc); cpu_physical_memory_write(packet_desc_addr, (uint8_t *)&desc[0], sizeof(desc)); s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; /* Handle interrupt consequences */ gem_update_int_status(s); return size; }


static int mov_parse_stsd_data(MOVContext *c, AVIOContext *pb, AVStream *st, MOVStreamContext *sc, int size) { if (st->codec->codec_tag == MKTAG('t','m','c','d')) { st->codec->extradata_size = size; st->codec->extradata = av_malloc(size + FF_INPUT_BUFFER_PADDING_SIZE); if (!st->codec->extradata) return AVERROR(ENOMEM); avio_read(pb, st->codec->extradata, size); } else { /* other codec type, just skip (rtp, mp4s ...) */ avio_skip(pb, size); } return 0; }


int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg) { struct kvm_irq_routing_entry kroute; if (!kvm_irqchip_in_kernel()) { return -ENOSYS; } kroute.gsi = virq; kroute.type = KVM_IRQ_ROUTING_MSI; kroute.flags = 0; kroute.u.msi.address_lo = (uint32_t)msg.address; kroute.u.msi.address_hi = msg.address >> 32; kroute.u.msi.data = le32_to_cpu(msg.data); return kvm_update_routing_entry(s, &kroute); }


static void rv34_gen_vlc(const uint8_t *bits, int size, VLC *vlc, const uint8_t *insyms, const int num) { int i; int counts[17] = {0}, codes[17]; uint16_t cw[size], syms[size]; uint8_t bits2[size]; int maxbits = 0, realsize = 0; for(i = 0; i < size; i++){ if(bits[i]){ bits2[realsize] = bits[i]; syms[realsize] = insyms ? insyms[i] : i; realsize++; maxbits = FFMAX(maxbits, bits[i]); counts[bits[i]]++; } } codes[0] = 0; for(i = 0; i < 16; i++) codes[i+1] = (codes[i] + counts[i]) << 1; for(i = 0; i < realsize; i++) cw[i] = codes[bits2[i]]++; vlc->table = &table_data[table_offs[num]]; vlc->table_allocated = table_offs[num + 1] - table_offs[num]; init_vlc_sparse(vlc, FFMIN(maxbits, 9), realsize, bits2, 1, 1, cw, 2, 2, syms, 2, 2, INIT_VLC_USE_NEW_STATIC); }


static int proxy_lremovexattr(FsContext *ctx, V9fsPath *fs_path, const char *name) { int retval; V9fsString xname; v9fs_string_init(&xname); v9fs_string_sprintf(&xname, "%s", name); retval = v9fs_request(ctx->private, T_LREMOVEXATTR, NULL, "ss", fs_path, &xname); v9fs_string_free(&xname); if (retval < 0) { errno = -retval; } return retval; }


static int get_blocksize(BlockDriverState *bdrv) { uint8_t cmd[10]; uint8_t buf[8]; uint8_t sensebuf[8]; sg_io_hdr_t io_header; int ret; memset(cmd, 0, sizeof(cmd)); memset(buf, 0, sizeof(buf)); cmd[0] = READ_CAPACITY_10; memset(&io_header, 0, sizeof(io_header)); io_header.interface_id = 'S'; io_header.dxfer_direction = SG_DXFER_FROM_DEV; io_header.dxfer_len = sizeof(buf); io_header.dxferp = buf; io_header.cmdp = cmd; io_header.cmd_len = sizeof(cmd); io_header.mx_sb_len = sizeof(sensebuf); io_header.sbp = sensebuf; io_header.timeout = 6000; /* XXX */ ret = bdrv_ioctl(bdrv, SG_IO, &io_header); if (ret < 0) return -1; return (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; }


ssize_t nbd_receive_reply(int csock, struct nbd_reply *reply) { uint8_t buf[NBD_REPLY_SIZE]; uint32_t magic; if (read_sync(csock, buf, sizeof(buf)) != sizeof(buf)) { LOG("read failed"); errno = EINVAL; return -1; } /* Reply [ 0 .. 3] magic (NBD_REPLY_MAGIC) [ 4 .. 7] error (0 == no error) [ 7 .. 15] handle */ magic = be32_to_cpup((uint32_t*)buf); reply->error = be32_to_cpup((uint32_t*)(buf + 4)); reply->handle = be64_to_cpup((uint64_t*)(buf + 8)); TRACE("Got reply: " "{ magic = 0x%x, .error = %d, handle = %" PRIu64" }", magic, reply->error, reply->handle); if (magic != NBD_REPLY_MAGIC) { LOG("invalid magic (got 0x%x)", magic); errno = EINVAL; return -1; } return 0; }


static void usb_mouse_class_initfn(ObjectClass *klass, void *data) { USBDeviceClass *uc = USB_DEVICE_CLASS(klass); uc->init = usb_mouse_initfn; uc->product_desc = "QEMU USB Mouse"; uc->usb_desc = &desc_mouse; uc->handle_packet = usb_generic_handle_packet; uc->handle_reset = usb_hid_handle_reset; uc->handle_control = usb_hid_handle_control; uc->handle_data = usb_hid_handle_data; uc->handle_destroy = usb_hid_handle_destroy; }


static void test_validate_fail_struct_nested(TestInputVisitorData *data, const void *unused) { UserDefNested *udp = NULL; Error *err = NULL; Visitor *v; v = validate_test_init(data, "{ 'string0': 'string0', 'dict1': { 'string1': 'string1', 'dict2': { 'userdef1': { 'integer': 42, 'string': 'string', 'extra': [42, 23, {'foo':'bar'}] }, 'string2': 'string2'}}}"); visit_type_UserDefNested(v, &udp, NULL, &err); g_assert(err); qapi_free_UserDefNested(udp); }


static int expand_zero_clusters_in_l1(BlockDriverState *bs, uint64_t *l1_table, int l1_size, int64_t *visited_l1_entries, int64_t l1_entries, BlockDriverAmendStatusCB *status_cb) { BDRVQcowState *s = bs->opaque; bool is_active_l1 = (l1_table == s->l1_table); uint64_t *l2_table = NULL; int ret; int i, j; if (!is_active_l1) { /* inactive L2 tables require a buffer to be stored in when loading * them from disk */ l2_table = qemu_try_blockalign(bs->file, s->cluster_size); if (l2_table == NULL) { return -ENOMEM; } } for (i = 0; i < l1_size; i++) { uint64_t l2_offset = l1_table[i] & L1E_OFFSET_MASK; bool l2_dirty = false; uint64_t l2_refcount; if (!l2_offset) { /* unallocated */ (*visited_l1_entries)++; if (status_cb) { status_cb(bs, *visited_l1_entries, l1_entries); } continue; } if (offset_into_cluster(s, l2_offset)) { qcow2_signal_corruption(bs, true, -1, -1, "L2 table offset %#" PRIx64 " unaligned (L1 index: %#x)", l2_offset, i); ret = -EIO; goto fail; } if (is_active_l1) { /* get active L2 tables from cache */ ret = qcow2_cache_get(bs, s->l2_table_cache, l2_offset, (void **)&l2_table); } else { /* load inactive L2 tables from disk */ ret = bdrv_read(bs->file, l2_offset / BDRV_SECTOR_SIZE, (void *)l2_table, s->cluster_sectors); } if (ret < 0) { goto fail; } ret = qcow2_get_refcount(bs, l2_offset >> s->cluster_bits, &l2_refcount); if (ret < 0) { goto fail; } for (j = 0; j < s->l2_size; j++) { uint64_t l2_entry = be64_to_cpu(l2_table[j]); int64_t offset = l2_entry & L2E_OFFSET_MASK; int cluster_type = qcow2_get_cluster_type(l2_entry); bool preallocated = offset != 0; if (cluster_type != QCOW2_CLUSTER_ZERO) { continue; } if (!preallocated) { if (!bs->backing_hd) { /* not backed; therefore we can simply deallocate the * cluster */ l2_table[j] = 0; l2_dirty = true; continue; } offset = qcow2_alloc_clusters(bs, s->cluster_size); if (offset < 0) { ret = offset; goto fail; } if (l2_refcount > 1) { /* For shared L2 tables, set the refcount accordingly (it is * already 1 and needs to be l2_refcount) */ ret = qcow2_update_cluster_refcount(bs, offset >> s->cluster_bits, refcount_diff(1, l2_refcount), false, QCOW2_DISCARD_OTHER); if (ret < 0) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_OTHER); goto fail; } } } if (offset_into_cluster(s, offset)) { qcow2_signal_corruption(bs, true, -1, -1, "Data cluster offset " "%#" PRIx64 " unaligned (L2 offset: %#" PRIx64 ", L2 index: %#x)", offset, l2_offset, j); if (!preallocated) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_ALWAYS); } ret = -EIO; goto fail; } ret = qcow2_pre_write_overlap_check(bs, 0, offset, s->cluster_size); if (ret < 0) { if (!preallocated) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_ALWAYS); } goto fail; } ret = bdrv_write_zeroes(bs->file, offset / BDRV_SECTOR_SIZE, s->cluster_sectors, 0); if (ret < 0) { if (!preallocated) { qcow2_free_clusters(bs, offset, s->cluster_size, QCOW2_DISCARD_ALWAYS); } goto fail; } if (l2_refcount == 1) { l2_table[j] = cpu_to_be64(offset | QCOW_OFLAG_COPIED); } else { l2_table[j] = cpu_to_be64(offset); } l2_dirty = true; } if (is_active_l1) { if (l2_dirty) { qcow2_cache_entry_mark_dirty(bs, s->l2_table_cache, l2_table); qcow2_cache_depends_on_flush(s->l2_table_cache); } ret = qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); if (ret < 0) { l2_table = NULL; goto fail; } } else { if (l2_dirty) { ret = qcow2_pre_write_overlap_check(bs, QCOW2_OL_INACTIVE_L2 | QCOW2_OL_ACTIVE_L2, l2_offset, s->cluster_size); if (ret < 0) { goto fail; } ret = bdrv_write(bs->file, l2_offset / BDRV_SECTOR_SIZE, (void *)l2_table, s->cluster_sectors); if (ret < 0) { goto fail; } } } (*visited_l1_entries)++; if (status_cb) { status_cb(bs, *visited_l1_entries, l1_entries); } } ret = 0; fail: if (l2_table) { if (!is_active_l1) { qemu_vfree(l2_table); } else { if (ret < 0) { qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); } else { ret = qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table); } } } return ret; }


static int request_frame(AVFilterLink *outlink) { AVFilterContext *ctx = outlink->src; TrimContext *s = ctx->priv; int ret; s->got_output = 0; while (!s->got_output) { if (s->eof) return AVERROR_EOF; ret = ff_request_frame(ctx->inputs[0]); if (ret < 0) return ret; } return 0; }


int ff_ivi_decode_frame(AVCodecContext *avctx, void *data, int *got_frame, AVPacket *avpkt) { IVI45DecContext *ctx = avctx->priv_data; const uint8_t *buf = avpkt->data; AVFrame *frame = data; int buf_size = avpkt->size; int result, p, b; init_get_bits(&ctx->gb, buf, buf_size * 8); ctx->frame_data = buf; ctx->frame_size = buf_size; result = ctx->decode_pic_hdr(ctx, avctx); if (result) { av_log(avctx, AV_LOG_ERROR, "Error while decoding picture header: %d\n", result); return result; } if (ctx->gop_invalid) return AVERROR_INVALIDDATA; if (avctx->codec_id == AV_CODEC_ID_INDEO4 && ctx->frame_type == IVI4_FRAMETYPE_NULL_LAST) { if (ctx->got_p_frame) { av_frame_move_ref(data, ctx->p_frame); *got_frame = 1; ctx->got_p_frame = 0; } else { *got_frame = 0; } return buf_size; } if (ctx->gop_flags & IVI5_IS_PROTECTED) { avpriv_report_missing_feature(avctx, "Password-protected clip!\n"); return AVERROR_PATCHWELCOME; } if (!ctx->planes[0].bands) { av_log(avctx, AV_LOG_ERROR, "Color planes not initialized yet\n"); return AVERROR_INVALIDDATA; } ctx->switch_buffers(ctx); //{ START_TIMER; if (ctx->is_nonnull_frame(ctx)) { for (p = 0; p < 3; p++) { for (b = 0; b < ctx->planes[p].num_bands; b++) { result = decode_band(ctx, &ctx->planes[p].bands[b], avctx); if (result < 0) { av_log(avctx, AV_LOG_ERROR, "Error while decoding band: %d, plane: %d\n", b, p); return result; } } } } else { if (ctx->is_scalable) return AVERROR_INVALIDDATA; for (p = 0; p < 3; p++) { if (!ctx->planes[p].bands[0].buf) return AVERROR_INVALIDDATA; } } //STOP_TIMER("decode_planes"); } result = ff_set_dimensions(avctx, ctx->planes[0].width, ctx->planes[0].height); if (result < 0) return result; if ((result = ff_get_buffer(avctx, frame, 0)) < 0) { av_log(avctx, AV_LOG_ERROR, "get_buffer() failed\n"); return result; } if (ctx->is_scalable) { if (avctx->codec_id == AV_CODEC_ID_INDEO4) ff_ivi_recompose_haar(&ctx->planes[0], frame->data[0], frame->linesize[0]); else ff_ivi_recompose53 (&ctx->planes[0], frame->data[0], frame->linesize[0]); } else { ivi_output_plane(&ctx->planes[0], frame->data[0], frame->linesize[0]); } ivi_output_plane(&ctx->planes[2], frame->data[1], frame->linesize[1]); ivi_output_plane(&ctx->planes[1], frame->data[2], frame->linesize[2]); *got_frame = 1; /* If the bidirectional mode is enabled, next I and the following P * frame will be sent together. Unfortunately the approach below seems * to be the only way to handle the B-frames mode. * That's exactly the same Intel decoders do. */ if (avctx->codec_id == AV_CODEC_ID_INDEO4 && ctx->frame_type == IVI4_FRAMETYPE_INTRA) { int left; while (get_bits(&ctx->gb, 8)); // skip version string left = get_bits_count(&ctx->gb) & 0x18; skip_bits_long(&ctx->gb, 64 - left); if (get_bits_left(&ctx->gb) > 18 && show_bits_long(&ctx->gb, 21) == 0xBFFF8) { // syncheader + inter type AVPacket pkt; pkt.data = avpkt->data + (get_bits_count(&ctx->gb) >> 3); pkt.size = get_bits_left(&ctx->gb) >> 3; ff_ivi_decode_frame(avctx, ctx->p_frame, &ctx->got_p_frame, &pkt); } } return buf_size; }


static void tcg_out_brcond32(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, int label_index, int small) { tcg_out_cmp(s, arg1, arg2, const_arg2, 0); tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small); }


void qemu_chr_free(CharDriverState *chr) { if (chr->chr_close) { chr->chr_close(chr); } g_free(chr->filename); g_free(chr->label); qemu_opts_del(chr->opts); g_free(chr); }


void replay_shutdown_request(void) { if (replay_mode == REPLAY_MODE_RECORD) { replay_mutex_lock(); replay_put_event(EVENT_SHUTDOWN); replay_mutex_unlock(); } }


target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env, MemoryRegionSection *section, target_ulong vaddr, target_phys_addr_t paddr, int prot, target_ulong *address) { target_phys_addr_t iotlb; CPUWatchpoint *wp; if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) + memory_region_section_addr(section, paddr); if (!section->readonly) { iotlb |= phys_section_notdirty; } else { iotlb |= phys_section_rom; } } else { /* IO handlers are currently passed a physical address. It would be nice to pass an offset from the base address of that region. This would avoid having to special case RAM, and avoid full address decoding in every device. We can't use the high bits of pd for this because IO_MEM_ROMD uses these as a ram address. */ iotlb = section - phys_sections; iotlb += memory_region_section_addr(section, paddr); } /* Make accesses to pages with watchpoints go via the watchpoint trap routines. */ QTAILQ_FOREACH(wp, &env->watchpoints, entry) { if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { /* Avoid trapping reads of pages with a write breakpoint. */ if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { iotlb = phys_section_watch + paddr; *address |= TLB_MMIO; break; } } } return iotlb; }


static int vpx_decode(AVCodecContext *avctx, void *data, int *got_frame, AVPacket *avpkt) { VPxContext *ctx = avctx->priv_data; AVFrame *picture = data; const void *iter = NULL; const void *iter_alpha = NULL; struct vpx_image *img, *img_alpha; int ret; uint8_t *side_data = NULL; int side_data_size = 0; ret = decode_frame(avctx, &ctx->decoder, avpkt->data, avpkt->size); if (ret) return ret; side_data = av_packet_get_side_data(avpkt, AV_PKT_DATA_MATROSKA_BLOCKADDITIONAL, &side_data_size); if (side_data_size > 1) { const uint64_t additional_id = AV_RB64(side_data); side_data += 8; side_data_size -= 8; if (additional_id == 1) { // 1 stands for alpha channel data. if (!ctx->has_alpha_channel) { ctx->has_alpha_channel = 1; ret = vpx_init(avctx, #if CONFIG_LIBVPX_VP8_DECODER && CONFIG_LIBVPX_VP9_DECODER (avctx->codec_id == AV_CODEC_ID_VP8) ? &vpx_codec_vp8_dx_algo : &vpx_codec_vp9_dx_algo, #elif CONFIG_LIBVPX_VP8_DECODER &vpx_codec_vp8_dx_algo, #else &vpx_codec_vp9_dx_algo, #endif 1); if (ret) return ret; ret = decode_frame(avctx, &ctx->decoder_alpha, side_data, side_data_size); if (ret) return ret; if ((img = vpx_codec_get_frame(&ctx->decoder, &iter)) && (!ctx->has_alpha_channel || (img_alpha = vpx_codec_get_frame(&ctx->decoder_alpha, &iter_alpha)))) { uint8_t *planes[4]; int linesizes[4]; if ((ret = set_pix_fmt(avctx, img, ctx->has_alpha_channel)) < 0) { #ifdef VPX_IMG_FMT_HIGHBITDEPTH av_log(avctx, AV_LOG_ERROR, "Unsupported output colorspace (%d) / bit_depth (%d)\n", img->fmt, img->bit_depth); #else av_log(avctx, AV_LOG_ERROR, "Unsupported output colorspace (%d) / bit_depth (%d)\n", img->fmt, 8); #endif return ret; if ((int) img->d_w != avctx->width || (int) img->d_h != avctx->height) { av_log(avctx, AV_LOG_INFO, "dimension change! %dx%d -> %dx%d\n", avctx->width, avctx->height, img->d_w, img->d_h); ret = ff_set_dimensions(avctx, img->d_w, img->d_h); if (ret < 0) return ret; if ((ret = ff_get_buffer(avctx, picture, 0)) < 0) return ret; planes[0] = img->planes[VPX_PLANE_Y]; planes[1] = img->planes[VPX_PLANE_U]; planes[2] = img->planes[VPX_PLANE_V]; planes[3] = ctx->has_alpha_channel ? img_alpha->planes[VPX_PLANE_Y] : NULL; linesizes[0] = img->stride[VPX_PLANE_Y]; linesizes[1] = img->stride[VPX_PLANE_U]; linesizes[2] = img->stride[VPX_PLANE_V]; linesizes[3] = ctx->has_alpha_channel ? img_alpha->stride[VPX_PLANE_Y] : 0; av_image_copy(picture->data, picture->linesize, (const uint8_t**)planes, linesizes, avctx->pix_fmt, img->d_w, img->d_h); *got_frame = 1; return avpkt->size;


static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg, bool in_prologue) { intptr_t tb_diff; tcg_target_long tmp; int shift; tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { arg = (int32_t)arg; } /* Load 16-bit immediates with one insn. */ if (tcg_out_movi_one(s, ret, arg)) { return; } /* Load addresses within the TB with one insn. */ tb_diff = arg - (intptr_t)s->code_gen_ptr; if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); return; } /* Load 32-bit immediates with two insns. Note that we've already eliminated bare ADDIS, so we know both insns are required. */ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); tcg_out32(s, ORI | SAI(ret, ret, arg)); return; } if (arg == (uint32_t)arg && !(arg & 0x8000)) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); return; } /* Load masked 16-bit value. */ if (arg > 0 && (arg & 0x8000)) { tmp = arg | 0x7fff; if ((tmp & (tmp + 1)) == 0) { int mb = clz64(tmp + 1) + 1; tcg_out32(s, ADDI | TAI(ret, 0, arg)); tcg_out_rld(s, RLDICL, ret, ret, 0, mb); return; } } /* Load common masks with 2 insns. */ shift = ctz64(arg); tmp = arg >> shift; if (tmp == (int16_t)tmp) { tcg_out32(s, ADDI | TAI(ret, 0, tmp)); tcg_out_shli64(s, ret, ret, shift); return; } shift = clz64(arg); if (tcg_out_movi_one(s, ret, arg << shift)) { tcg_out_shri64(s, ret, ret, shift); return; } /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); return; } /* Use the constant pool, if possible. */ if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } tmp = arg >> 31 >> 1; tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); if (tmp) { tcg_out_shli64(s, ret, ret, 32); } if (arg & 0xffff0000) { tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); } if (arg & 0xffff) { tcg_out32(s, ORI | SAI(ret, ret, arg)); } }


static int mpjpeg_read_probe(AVProbeData *p) { AVIOContext *pb; char line[128] = { 0 }; int ret = 0; pb = avio_alloc_context(p->buf, p->buf_size, 0, NULL, NULL, NULL, NULL); if (!pb) return AVERROR(ENOMEM); if (p->buf_size < 2 || p->buf[0] != '-' || p->buf[1] != '-') return 0; while (!pb->eof_reached) { ret = get_line(pb, line, sizeof(line)); if (ret < 0) break; ret = check_content_type(line); if (!ret) { ret = AVPROBE_SCORE_MAX; break; } } av_free(pb); return ret; }


static int flic_read_header(AVFormatContext *s) { FlicDemuxContext *flic = s->priv_data; AVIOContext *pb = s->pb; unsigned char header[FLIC_HEADER_SIZE]; AVStream *st, *ast; int speed; int magic_number; unsigned char preamble[FLIC_PREAMBLE_SIZE]; flic->frame_number = 0; /* load the whole header and pull out the width and height */ if (avio_read(pb, header, FLIC_HEADER_SIZE) != FLIC_HEADER_SIZE) return AVERROR(EIO); magic_number = AV_RL16(&header[4]); speed = AV_RL32(&header[0x10]); if (speed == 0) speed = FLIC_DEFAULT_SPEED; /* initialize the decoder streams */ st = avformat_new_stream(s, NULL); if (!st) return AVERROR(ENOMEM); flic->video_stream_index = st->index; st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = AV_CODEC_ID_FLIC; st->codec->codec_tag = 0; /* no fourcc */ st->codec->width = AV_RL16(&header[0x08]); st->codec->height = AV_RL16(&header[0x0A]); if (!st->codec->width || !st->codec->height) { /* Ugly hack needed for the following sample: */ /* http://samples.mplayerhq.hu/fli-flc/fli-bugs/specular.flc */ av_log(s, AV_LOG_WARNING, "File with no specified width/height. Trying 640x480.\n"); st->codec->width = 640; st->codec->height = 480; } /* send over the whole 128-byte FLIC header */ st->codec->extradata_size = FLIC_HEADER_SIZE; st->codec->extradata = av_malloc(FLIC_HEADER_SIZE); memcpy(st->codec->extradata, header, FLIC_HEADER_SIZE); /* peek at the preamble to detect TFTD videos - they seem to always start with an audio chunk */ if (avio_read(pb, preamble, FLIC_PREAMBLE_SIZE) != FLIC_PREAMBLE_SIZE) { av_log(s, AV_LOG_ERROR, "Failed to peek at preamble\n"); return AVERROR(EIO); } avio_seek(pb, -FLIC_PREAMBLE_SIZE, SEEK_CUR); /* Time to figure out the framerate: * If the first preamble's magic number is 0xAAAA then this file is from * X-COM: Terror from the Deep. If on the other hand there is a FLIC chunk * magic number at offset 0x10 assume this file is from Magic Carpet instead. * If neither of the above is true then this is a normal FLIC file. */ if (AV_RL16(&preamble[4]) == FLIC_TFTD_CHUNK_AUDIO) { /* TFTD videos have an extra 22050 Hz 8-bit mono audio stream */ ast = avformat_new_stream(s, NULL); if (!ast) return AVERROR(ENOMEM); flic->audio_stream_index = ast->index; /* all audio frames are the same size, so use the size of the first chunk for block_align */ ast->codec->block_align = AV_RL32(&preamble[0]); ast->codec->codec_type = AVMEDIA_TYPE_AUDIO; ast->codec->codec_id = AV_CODEC_ID_PCM_U8; ast->codec->codec_tag = 0; ast->codec->sample_rate = FLIC_TFTD_SAMPLE_RATE; ast->codec->channels = 1; ast->codec->bit_rate = st->codec->sample_rate * 8; ast->codec->bits_per_coded_sample = 8; ast->codec->channel_layout = AV_CH_LAYOUT_MONO; ast->codec->extradata_size = 0; /* Since the header information is incorrect we have to figure out the * framerate using block_align and the fact that the audio is 22050 Hz. * We usually have two cases: 2205 -> 10 fps and 1470 -> 15 fps */ avpriv_set_pts_info(st, 64, ast->codec->block_align, FLIC_TFTD_SAMPLE_RATE); avpriv_set_pts_info(ast, 64, 1, FLIC_TFTD_SAMPLE_RATE); } else if (AV_RL16(&header[0x10]) == FLIC_CHUNK_MAGIC_1) { avpriv_set_pts_info(st, 64, FLIC_MC_SPEED, 70); /* rewind the stream since the first chunk is at offset 12 */ avio_seek(pb, 12, SEEK_SET); /* send over abbreviated FLIC header chunk */ av_free(st->codec->extradata); st->codec->extradata_size = 12; st->codec->extradata = av_malloc(12); memcpy(st->codec->extradata, header, 12); } else if (magic_number == FLIC_FILE_MAGIC_1) { avpriv_set_pts_info(st, 64, speed, 70); } else if ((magic_number == FLIC_FILE_MAGIC_2) || (magic_number == FLIC_FILE_MAGIC_3)) { avpriv_set_pts_info(st, 64, speed, 1000); } else { av_log(s, AV_LOG_ERROR, "Invalid or unsupported magic chunk in file\n"); return AVERROR_INVALIDDATA; } return 0; }


ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename) { ds1225y_t *s; int mem_index1, mem_index2; s = qemu_mallocz(sizeof(ds1225y_t)); if (!s) return NULL; s->mem_base = mem_base; s->capacity = 0x2000; /* Fixed for ds1225y chip: 8K */ s->filename = filename; /* Read/write memory */ mem_index1 = cpu_register_io_memory(0, nvram_read, nvram_write, s); cpu_register_physical_memory(mem_base, s->capacity, mem_index1); /* Read-only memory */ mem_index2 = cpu_register_io_memory(0, nvram_read, nvram_none, s); cpu_register_physical_memory(mem_base + s->capacity, s->capacity, mem_index2); return s; }


static void sdp_parse_line(AVFormatContext *s, SDPParseState *s1, int letter, const char *buf) { RTSPState *rt = s->priv_data; char buf1[64], st_type[64]; const char *p; enum AVMediaType codec_type; int payload_type; AVStream *st; RTSPStream *rtsp_st; RTSPSource *rtsp_src; struct sockaddr_storage sdp_ip; int ttl; av_dlog(s, "sdp: %c='%s'\n", letter, buf); p = buf; if (s1->skip_media && letter != 'm') return; switch (letter) { case 'c': get_word(buf1, sizeof(buf1), &p); if (strcmp(buf1, "IN") != 0) return; get_word(buf1, sizeof(buf1), &p); if (strcmp(buf1, "IP4") && strcmp(buf1, "IP6")) return; get_word_sep(buf1, sizeof(buf1), "/", &p); if (get_sockaddr(buf1, &sdp_ip)) return; ttl = 16; if (*p == '/') { p++; get_word_sep(buf1, sizeof(buf1), "/", &p); ttl = atoi(buf1); } if (s->nb_streams == 0) { s1->default_ip = sdp_ip; s1->default_ttl = ttl; } else { rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; rtsp_st->sdp_ip = sdp_ip; rtsp_st->sdp_ttl = ttl; } break; case 's': av_dict_set(&s->metadata, "title", p, 0); break; case 'i': if (s->nb_streams == 0) { av_dict_set(&s->metadata, "comment", p, 0); break; } break; case 'm': /* new stream */ s1->skip_media = 0; s1->seen_fmtp = 0; s1->seen_rtpmap = 0; codec_type = AVMEDIA_TYPE_UNKNOWN; get_word(st_type, sizeof(st_type), &p); if (!strcmp(st_type, "audio")) { codec_type = AVMEDIA_TYPE_AUDIO; } else if (!strcmp(st_type, "video")) { codec_type = AVMEDIA_TYPE_VIDEO; } else if (!strcmp(st_type, "application")) { codec_type = AVMEDIA_TYPE_DATA; } if (codec_type == AVMEDIA_TYPE_UNKNOWN || !(rt->media_type_mask & (1 << codec_type))) { s1->skip_media = 1; return; } rtsp_st = av_mallocz(sizeof(RTSPStream)); if (!rtsp_st) return; rtsp_st->stream_index = -1; dynarray_add(&rt->rtsp_streams, &rt->nb_rtsp_streams, rtsp_st); rtsp_st->sdp_ip = s1->default_ip; rtsp_st->sdp_ttl = s1->default_ttl; copy_default_source_addrs(s1->default_include_source_addrs, s1->nb_default_include_source_addrs, &rtsp_st->include_source_addrs, &rtsp_st->nb_include_source_addrs); copy_default_source_addrs(s1->default_exclude_source_addrs, s1->nb_default_exclude_source_addrs, &rtsp_st->exclude_source_addrs, &rtsp_st->nb_exclude_source_addrs); get_word(buf1, sizeof(buf1), &p); /* port */ rtsp_st->sdp_port = atoi(buf1); get_word(buf1, sizeof(buf1), &p); /* protocol */ if (!strcmp(buf1, "udp")) rt->transport = RTSP_TRANSPORT_RAW; else if (strstr(buf1, "/AVPF") || strstr(buf1, "/SAVPF")) rtsp_st->feedback = 1; /* XXX: handle list of formats */ get_word(buf1, sizeof(buf1), &p); /* format list */ rtsp_st->sdp_payload_type = atoi(buf1); if (!strcmp(ff_rtp_enc_name(rtsp_st->sdp_payload_type), "MP2T")) { /* no corresponding stream */ if (rt->transport == RTSP_TRANSPORT_RAW) { if (!rt->ts && CONFIG_RTPDEC) rt->ts = ff_mpegts_parse_open(s); } else { RTPDynamicProtocolHandler *handler; handler = ff_rtp_handler_find_by_id( rtsp_st->sdp_payload_type, AVMEDIA_TYPE_DATA); init_rtp_handler(handler, rtsp_st, NULL); if (handler && handler->init) handler->init(s, -1, rtsp_st->dynamic_protocol_context); } } else if (rt->server_type == RTSP_SERVER_WMS && codec_type == AVMEDIA_TYPE_DATA) { /* RTX stream, a stream that carries all the other actual * audio/video streams. Don't expose this to the callers. */ } else { st = avformat_new_stream(s, NULL); if (!st) return; st->id = rt->nb_rtsp_streams - 1; rtsp_st->stream_index = st->index; st->codec->codec_type = codec_type; if (rtsp_st->sdp_payload_type < RTP_PT_PRIVATE) { RTPDynamicProtocolHandler *handler; /* if standard payload type, we can find the codec right now */ ff_rtp_get_codec_info(st->codec, rtsp_st->sdp_payload_type); if (st->codec->codec_type == AVMEDIA_TYPE_AUDIO && st->codec->sample_rate > 0) avpriv_set_pts_info(st, 32, 1, st->codec->sample_rate); /* Even static payload types may need a custom depacketizer */ handler = ff_rtp_handler_find_by_id( rtsp_st->sdp_payload_type, st->codec->codec_type); init_rtp_handler(handler, rtsp_st, st->codec); if (handler && handler->init) handler->init(s, st->index, rtsp_st->dynamic_protocol_context); } } /* put a default control url */ av_strlcpy(rtsp_st->control_url, rt->control_uri, sizeof(rtsp_st->control_url)); break; case 'a': if (av_strstart(p, "control:", &p)) { if (s->nb_streams == 0) { if (!strncmp(p, "rtsp://", 7)) av_strlcpy(rt->control_uri, p, sizeof(rt->control_uri)); } else { char proto[32]; /* get the control url */ rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; /* XXX: may need to add full url resolution */ av_url_split(proto, sizeof(proto), NULL, 0, NULL, 0, NULL, NULL, 0, p); if (proto[0] == '\0') { /* relative control URL */ if (rtsp_st->control_url[strlen(rtsp_st->control_url)-1]!='/') av_strlcat(rtsp_st->control_url, "/", sizeof(rtsp_st->control_url)); av_strlcat(rtsp_st->control_url, p, sizeof(rtsp_st->control_url)); } else av_strlcpy(rtsp_st->control_url, p, sizeof(rtsp_st->control_url)); } } else if (av_strstart(p, "rtpmap:", &p) && s->nb_streams > 0) { /* NOTE: rtpmap is only supported AFTER the 'm=' tag */ get_word(buf1, sizeof(buf1), &p); payload_type = atoi(buf1); rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; if (rtsp_st->stream_index >= 0) { st = s->streams[rtsp_st->stream_index]; sdp_parse_rtpmap(s, st, rtsp_st, payload_type, p); } s1->seen_rtpmap = 1; if (s1->seen_fmtp) { parse_fmtp(s, rt, payload_type, s1->delayed_fmtp); } } else if (av_strstart(p, "fmtp:", &p) || av_strstart(p, "framesize:", &p)) { // let dynamic protocol handlers have a stab at the line. get_word(buf1, sizeof(buf1), &p); payload_type = atoi(buf1); if (s1->seen_rtpmap) { parse_fmtp(s, rt, payload_type, buf); } else { s1->seen_fmtp = 1; av_strlcpy(s1->delayed_fmtp, buf, sizeof(s1->delayed_fmtp)); } } else if (av_strstart(p, "range:", &p)) { int64_t start, end; // this is so that seeking on a streamed file can work. rtsp_parse_range_npt(p, &start, &end); s->start_time = start; /* AV_NOPTS_VALUE means live broadcast (and can't seek) */ s->duration = (end == AV_NOPTS_VALUE) ? AV_NOPTS_VALUE : end - start; } else if (av_strstart(p, "IsRealDataType:integer;",&p)) { if (atoi(p) == 1) rt->transport = RTSP_TRANSPORT_RDT; } else if (av_strstart(p, "SampleRate:integer;", &p) && s->nb_streams > 0) { st = s->streams[s->nb_streams - 1]; st->codec->sample_rate = atoi(p); } else if (av_strstart(p, "crypto:", &p) && s->nb_streams > 0) { // RFC 4568 rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; get_word(buf1, sizeof(buf1), &p); // ignore tag get_word(rtsp_st->crypto_suite, sizeof(rtsp_st->crypto_suite), &p); p += strspn(p, SPACE_CHARS); if (av_strstart(p, "inline:", &p)) get_word(rtsp_st->crypto_params, sizeof(rtsp_st->crypto_params), &p); } else if (av_strstart(p, "source-filter:", &p)) { int exclude = 0; get_word(buf1, sizeof(buf1), &p); if (strcmp(buf1, "incl") && strcmp(buf1, "excl")) return; exclude = !strcmp(buf1, "excl"); get_word(buf1, sizeof(buf1), &p); if (strcmp(buf1, "IN") != 0) return; get_word(buf1, sizeof(buf1), &p); if (strcmp(buf1, "IP4") && strcmp(buf1, "IP6") && strcmp(buf1, "*")) return; // not checking that the destination address actually matches or is wildcard get_word(buf1, sizeof(buf1), &p); while (*p != '\0') { rtsp_src = av_mallocz(sizeof(*rtsp_src)); if (!rtsp_src) return; get_word(rtsp_src->addr, sizeof(rtsp_src->addr), &p); if (exclude) { if (s->nb_streams == 0) { dynarray_add(&s1->default_exclude_source_addrs, &s1->nb_default_exclude_source_addrs, rtsp_src); } else { rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; dynarray_add(&rtsp_st->exclude_source_addrs, &rtsp_st->nb_exclude_source_addrs, rtsp_src); } } else { if (s->nb_streams == 0) { dynarray_add(&s1->default_include_source_addrs, &s1->nb_default_include_source_addrs, rtsp_src); } else { rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; dynarray_add(&rtsp_st->include_source_addrs, &rtsp_st->nb_include_source_addrs, rtsp_src); } } } } else { if (rt->server_type == RTSP_SERVER_WMS) ff_wms_parse_sdp_a_line(s, p); if (s->nb_streams > 0) { rtsp_st = rt->rtsp_streams[rt->nb_rtsp_streams - 1]; if (rt->server_type == RTSP_SERVER_REAL) ff_real_parse_sdp_a_line(s, rtsp_st->stream_index, p); if (rtsp_st->dynamic_handler && rtsp_st->dynamic_handler->parse_sdp_a_line) rtsp_st->dynamic_handler->parse_sdp_a_line(s, rtsp_st->stream_index, rtsp_st->dynamic_protocol_context, buf); } } break; } }


av_cold void ff_mlpdsp_init(MLPDSPContext *c) { c->mlp_filter_channel = mlp_filter_channel; if (ARCH_X86) ff_mlpdsp_init_x86(c); }


int coroutine_fn qemu_co_sendv(int sockfd, struct iovec *iov, int len, int iov_offset) { int total = 0; int ret; while (len) { ret = qemu_sendv(sockfd, iov, len, iov_offset + total); if (ret < 0) { if (errno == EAGAIN) { qemu_coroutine_yield(); continue; } if (total == 0) { total = -1; } break; } total += ret, len -= ret; } return total; }


static PullupField *make_field_queue(PullupContext *s, int len) { PullupField *head, *f; f = head = av_mallocz(sizeof(*head)); if (!f) return NULL; if (alloc_metrics(s, f) < 0) { av_free(f); return NULL; } for (; len > 0; len--) { f->next = av_mallocz(sizeof(*f->next)); if (!f->next) { free_field_queue(head, &f); return NULL; } f->next->prev = f; f = f->next; if (alloc_metrics(s, f) < 0) { free_field_queue(head, &f); return NULL; } } f->next = head; head->prev = f; return head; }


static void lan9118_writel(void *opaque, target_phys_addr_t offset, uint32_t val) { lan9118_state *s = (lan9118_state *)opaque; offset &= 0xff; //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); if (offset >= 0x20 && offset < 0x40) { /* TX FIFO */ tx_fifo_push(s, val); return; } switch (offset) { case CSR_IRQ_CFG: /* TODO: Implement interrupt deassertion intervals. */ s->irq_cfg = (s->irq_cfg & IRQ_INT) | (val & IRQ_EN); break; case CSR_INT_STS: s->int_sts &= ~val; break; case CSR_INT_EN: s->int_en = val & ~RESERVED_INT; s->int_sts |= val & SW_INT; break; case CSR_FIFO_INT: DPRINTF("FIFO INT levels %08x\n", val); s->fifo_int = val; break; case CSR_RX_CFG: if (val & 0x8000) { /* RX_DUMP */ s->rx_fifo_used = 0; s->rx_status_fifo_used = 0; s->rx_packet_size_tail = s->rx_packet_size_head; s->rx_packet_size[s->rx_packet_size_head] = 0; } s->rx_cfg = val & 0xcfff1ff0; break; case CSR_TX_CFG: if (val & 0x8000) { s->tx_status_fifo_used = 0; } if (val & 0x4000) { s->txp->state = TX_IDLE; s->txp->fifo_used = 0; s->txp->cmd_a = 0xffffffff; } s->tx_cfg = val & 6; break; case CSR_HW_CFG: if (val & 1) { /* SRST */ lan9118_reset(&s->busdev.qdev); } else { s->hw_cfg = val & 0x003f300; } break; case CSR_RX_DP_CTRL: if (val & 0x80000000) { /* Skip forward to next packet. */ s->rxp_pad = 0; s->rxp_offset = 0; if (s->rxp_size == 0) { /* Pop a word to start the next packet. */ rx_fifo_pop(s); s->rxp_pad = 0; s->rxp_offset = 0; } s->rx_fifo_head += s->rxp_size; if (s->rx_fifo_head >= s->rx_fifo_size) { s->rx_fifo_head -= s->rx_fifo_size; } } break; case CSR_PMT_CTRL: if (val & 0x400) { phy_reset(s); } s->pmt_ctrl &= ~0x34e; s->pmt_ctrl |= (val & 0x34e); break; case CSR_GPIO_CFG: /* Probably just enabling LEDs. */ s->gpio_cfg = val & 0x7777071f; break; case CSR_GPT_CFG: if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { if (val & GPT_TIMER_EN) { ptimer_set_count(s->timer, val & 0xffff); ptimer_run(s->timer, 0); } else { ptimer_stop(s->timer); ptimer_set_count(s->timer, 0xffff); } } s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff); break; case CSR_WORD_SWAP: /* Ignored because we're in 32-bit mode. */ s->word_swap = val; break; case CSR_MAC_CSR_CMD: s->mac_cmd = val & 0x4000000f; if (val & 0x80000000) { if (val & 0x40000000) { s->mac_data = do_mac_read(s, val & 0xf); DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); } else { DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); do_mac_write(s, val & 0xf, s->mac_data); } } break; case CSR_MAC_CSR_DATA: s->mac_data = val; break; case CSR_AFC_CFG: s->afc_cfg = val & 0x00ffffff; break; case CSR_E2P_CMD: lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0xff); break; case CSR_E2P_DATA: s->e2p_data = val & 0xff; break; default: hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val); break; } lan9118_update(s); }


static av_cold int fdk_aac_decode_init(AVCodecContext *avctx) { FDKAACDecContext *s = avctx->priv_data; AAC_DECODER_ERROR err; int ret; s->handle = aacDecoder_Open(avctx->extradata_size ? TT_MP4_RAW : TT_MP4_ADTS, 1); if (!s->handle) { av_log(avctx, AV_LOG_ERROR, "Error opening decoder\n"); return AVERROR_UNKNOWN; } if (avctx->extradata_size) { if ((err = aacDecoder_ConfigRaw(s->handle, &avctx->extradata, &avctx->extradata_size)) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set extradata\n"); return AVERROR_INVALIDDATA; } } if ((err = aacDecoder_SetParam(s->handle, AAC_CONCEAL_METHOD, s->conceal_method)) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set error concealment method\n"); return AVERROR_UNKNOWN; } if (avctx->request_channel_layout > 0 && avctx->request_channel_layout != AV_CH_LAYOUT_NATIVE) { int downmix_channels = -1; switch (avctx->request_channel_layout) { case AV_CH_LAYOUT_STEREO: case AV_CH_LAYOUT_STEREO_DOWNMIX: downmix_channels = 2; break; case AV_CH_LAYOUT_MONO: downmix_channels = 1; break; default: av_log(avctx, AV_LOG_WARNING, "Invalid request_channel_layout\n"); break; } if (downmix_channels != -1) { if (aacDecoder_SetParam(s->handle, AAC_PCM_MAX_OUTPUT_CHANNELS, downmix_channels) != AAC_DEC_OK) { av_log(avctx, AV_LOG_WARNING, "Unable to set output channels in the decoder\n"); } else { s->anc_buffer = av_malloc(DMX_ANC_BUFFSIZE); if (!s->anc_buffer) { av_log(avctx, AV_LOG_ERROR, "Unable to allocate ancillary buffer for the decoder\n"); ret = AVERROR(ENOMEM); goto fail; } if (aacDecoder_AncDataInit(s->handle, s->anc_buffer, DMX_ANC_BUFFSIZE)) { av_log(avctx, AV_LOG_ERROR, "Unable to register downmix ancillary buffer in the decoder\n"); ret = AVERROR_UNKNOWN; goto fail; } } } } if (s->drc_boost != -1) { if (aacDecoder_SetParam(s->handle, AAC_DRC_BOOST_FACTOR, s->drc_boost) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set DRC boost factor in the decoder\n"); return AVERROR_UNKNOWN; } } if (s->drc_cut != -1) { if (aacDecoder_SetParam(s->handle, AAC_DRC_ATTENUATION_FACTOR, s->drc_cut) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set DRC attenuation factor in the decoder\n"); return AVERROR_UNKNOWN; } } if (s->drc_level != -1) { if (aacDecoder_SetParam(s->handle, AAC_DRC_REFERENCE_LEVEL, s->drc_level) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set DRC reference level in the decoder\n"); return AVERROR_UNKNOWN; } } if (s->drc_heavy != -1) { if (aacDecoder_SetParam(s->handle, AAC_DRC_HEAVY_COMPRESSION, s->drc_heavy) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set DRC heavy compression in the decoder\n"); return AVERROR_UNKNOWN; } } #ifdef AACDECODER_LIB_VL0 if (aacDecoder_SetParam(s->handle, AAC_PCM_LIMITER_ENABLE, s->level_limit) != AAC_DEC_OK) { av_log(avctx, AV_LOG_ERROR, "Unable to set in signal level limiting in the decoder\n"); return AVERROR_UNKNOWN; } #endif avctx->sample_fmt = AV_SAMPLE_FMT_S16; s->decoder_buffer_size = DECODER_BUFFSIZE * DECODER_MAX_CHANNELS; s->decoder_buffer = av_malloc(s->decoder_buffer_size); if (!s->decoder_buffer) { ret = AVERROR(ENOMEM); goto fail; } return 0; fail: fdk_aac_decode_close(avctx); return ret; }


int ff_hevc_decode_extradata(const uint8_t *data, int size, HEVCParamSets *ps, int *is_nalff, int *nal_length_size, int err_recognition, void *logctx) { int ret = 0; GetByteContext gb; bytestream2_init(&gb, data, size); if (size > 3 && (data[0] || data[1] || data[2] > 1)) { /* It seems the extradata is encoded as hvcC format. * Temporarily, we support configurationVersion==0 until 14496-15 3rd * is finalized. When finalized, configurationVersion will be 1 and we * can recognize hvcC by checking if avctx->extradata[0]==1 or not. */ int i, j, num_arrays, nal_len_size; *is_nalff = 1; bytestream2_skip(&gb, 21); nal_len_size = (bytestream2_get_byte(&gb) & 3) + 1; num_arrays = bytestream2_get_byte(&gb); /* nal units in the hvcC always have length coded with 2 bytes, * so put a fake nal_length_size = 2 while parsing them */ *nal_length_size = 2; /* Decode nal units from hvcC. */ for (i = 0; i < num_arrays; i++) { int type = bytestream2_get_byte(&gb) & 0x3f; int cnt = bytestream2_get_be16(&gb); for (j = 0; j < cnt; j++) { // +2 for the nal size field int nalsize = bytestream2_peek_be16(&gb) + 2; if (bytestream2_get_bytes_left(&gb) < nalsize) { av_log(logctx, AV_LOG_ERROR, "Invalid NAL unit size in extradata.\n"); return AVERROR_INVALIDDATA; } ret = hevc_decode_nal_units(gb.buffer, nalsize, ps, *is_nalff, *nal_length_size, logctx); if (ret < 0) { av_log(logctx, AV_LOG_ERROR, "Decoding nal unit %d %d from hvcC failed\n", type, i); return ret; } bytestream2_skip(&gb, nalsize); } } /* Now store right nal length size, that will be used to parse * all other nals */ *nal_length_size = nal_len_size; } else { *is_nalff = 0; ret = hevc_decode_nal_units(data, size, ps, *is_nalff, *nal_length_size, logctx); if (ret < 0) return ret; } return ret; }


static void frame_thread_free(AVCodecContext *avctx, int thread_count) { FrameThreadContext *fctx = avctx->thread_opaque; AVCodec *codec = avctx->codec; int i; park_frame_worker_threads(fctx, thread_count); if (fctx->prev_thread && fctx->prev_thread != fctx->threads) update_context_from_thread(fctx->threads->avctx, fctx->prev_thread->avctx, 0); fctx->die = 1; for (i = 0; i < thread_count; i++) { PerThreadContext *p = &fctx->threads[i]; pthread_mutex_lock(&p->mutex); pthread_cond_signal(&p->input_cond); pthread_mutex_unlock(&p->mutex); pthread_join(p->thread, NULL); if (codec->close) codec->close(p->avctx); avctx->codec = NULL; release_delayed_buffers(p); } for (i = 0; i < thread_count; i++) { PerThreadContext *p = &fctx->threads[i]; avcodec_default_free_buffers(p->avctx); pthread_mutex_destroy(&p->mutex); pthread_mutex_destroy(&p->progress_mutex); pthread_cond_destroy(&p->input_cond); pthread_cond_destroy(&p->progress_cond); pthread_cond_destroy(&p->output_cond); av_freep(&p->avpkt.data); if (i) av_freep(&p->avctx->priv_data); av_freep(&p->avctx); } av_freep(&fctx->threads); pthread_mutex_destroy(&fctx->buffer_mutex); av_freep(&avctx->thread_opaque); avctx->has_b_frames -= avctx->thread_count - 1; }


int qio_dns_resolver_lookup_sync(QIODNSResolver *resolver, SocketAddress *addr, size_t *naddrs, SocketAddress ***addrs, Error **errp) { switch (addr->type) { case SOCKET_ADDRESS_KIND_INET: return qio_dns_resolver_lookup_sync_inet(resolver, addr, naddrs, addrs, errp); case SOCKET_ADDRESS_KIND_UNIX: case SOCKET_ADDRESS_KIND_VSOCK: case SOCKET_ADDRESS_KIND_FD: return qio_dns_resolver_lookup_sync_nop(resolver, addr, naddrs, addrs, errp); default: abort(); } }


int fw_cfg_add_file(FWCfgState *s, const char *dir, const char *filename, uint8_t *data, uint32_t len) { const char *basename; int index; if (!s->files) { int dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * FW_CFG_FILE_SLOTS; s->files = qemu_mallocz(dsize); fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, (uint8_t*)s->files, dsize); } index = be32_to_cpu(s->files->count); if (index == FW_CFG_FILE_SLOTS) { fprintf(stderr, "fw_cfg: out of file slots\n"); return 0; } fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len); basename = strrchr(filename, '/'); if (basename) { basename++; } else { basename = filename; } if (dir) { snprintf(s->files->f[index].name, sizeof(s->files->f[index].name), "%s/%s", dir, basename); } else { snprintf(s->files->f[index].name, sizeof(s->files->f[index].name), "%s", basename); } s->files->f[index].size = cpu_to_be32(len); s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); FW_CFG_DPRINTF("%s: #%d: %s (%d bytes)\n", __FUNCTION__, index, s->files->f[index].name, len); s->files->count = cpu_to_be32(index+1); return 1; }


static void mov_text_text_cb(void *priv, const char *text, int len) { MovTextContext *s = priv; av_strlcpy(s->ptr, text, FFMIN(s->end - s->ptr, len + 1)); s->ptr += len; }


void qmp_balloon(int64_t value, Error **errp) { if (kvm_enabled() && !kvm_has_sync_mmu()) { error_set(errp, QERR_KVM_MISSING_CAP, "synchronous MMU", "balloon"); return; } if (value <= 0) { error_set(errp, QERR_INVALID_PARAMETER_VALUE, "target", "a size"); return; } if (qemu_balloon(value) == 0) { error_set(errp, QERR_DEVICE_NOT_ACTIVE, "balloon"); } }


struct GuestFileSeek *qmp_guest_file_seek(int64_t handle, int64_t offset, int64_t whence, Error **errp) { GuestFileHandle *gfh = guest_file_handle_find(handle, errp); GuestFileSeek *seek_data = NULL; FILE *fh; int ret; if (!gfh) { return NULL; } fh = gfh->fh; ret = fseek(fh, offset, whence); if (ret == -1) { error_setg_errno(errp, errno, "failed to seek file"); if (errno == ESPIPE) { /* file is non-seekable, stdio shouldn't be buffering anyways */ gfh->state = RW_STATE_NEW; } } else { seek_data = g_new0(GuestFileSeek, 1); seek_data->position = ftell(fh); seek_data->eof = feof(fh); gfh->state = RW_STATE_NEW; } clearerr(fh); return seek_data; }


static bool virtio_device_endian_needed(void *opaque) { VirtIODevice *vdev = opaque; assert(vdev->device_endian != VIRTIO_DEVICE_ENDIAN_UNKNOWN); if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1)) { return vdev->device_endian != virtio_default_endian(); } /* Devices conforming to VIRTIO 1.0 or later are always LE. */ return vdev->device_endian != VIRTIO_DEVICE_ENDIAN_LITTLE; }


static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) { UHCIAsync *async; int len = 0, max_len; uint8_t pid; /* Is active ? */ if (!(td->ctrl & TD_CTRL_ACTIVE)) return 1; async = uhci_async_find_td(s, addr, td->token); if (async) { /* Already submitted */ async->valid = 32; if (!async->done) return 1; uhci_async_unlink(s, async); goto done; } /* Allocate new packet */ async = uhci_async_alloc(s); if (!async) return 1; async->valid = 10; async->td = addr; async->token = td->token; max_len = ((td->token >> 21) + 1) & 0x7ff; pid = td->token & 0xff; async->packet.pid = pid; async->packet.devaddr = (td->token >> 8) & 0x7f; async->packet.devep = (td->token >> 15) & 0xf; async->packet.data = async->buffer; async->packet.len = max_len; async->packet.complete_cb = uhci_async_complete; async->packet.complete_opaque = s; switch(pid) { case USB_TOKEN_OUT: case USB_TOKEN_SETUP: cpu_physical_memory_read(td->buffer, async->buffer, max_len); len = uhci_broadcast_packet(s, &async->packet); if (len >= 0) len = max_len; break; case USB_TOKEN_IN: len = uhci_broadcast_packet(s, &async->packet); break; default: /* invalid pid : frame interrupted */ uhci_async_free(s, async); s->status |= UHCI_STS_HCPERR; uhci_update_irq(s); return -1; } if (len == USB_RET_ASYNC) { uhci_async_link(s, async); return 2; } async->packet.len = len; done: len = uhci_complete_td(s, td, async, int_mask); uhci_async_free(s, async); return len; }


static void omap_pwt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 1) { omap_badwidth_write8(opaque, addr, value); return; } switch (offset) { case 0x00: /* FRC */ s->frc = value & 0x3f; break; case 0x04: /* VRC */ if ((value ^ s->vrc) & 1) { if (value & 1) printf("%s: %iHz buzz on\n", __FUNCTION__, (int) /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ ((omap_clk_getrate(s->clk) >> 3) / /* Pre-multiplexer divider */ ((s->gcr & 2) ? 1 : 154) / /* Octave multiplexer */ (2 << (value & 3)) * /* 101/107 divider */ ((value & (1 << 2)) ? 101 : 107) * /* 49/55 divider */ ((value & (1 << 3)) ? 49 : 55) * /* 50/63 divider */ ((value & (1 << 4)) ? 50 : 63) * /* 80/127 divider */ ((value & (1 << 5)) ? 80 : 127) / (107 * 55 * 63 * 127))); else printf("%s: silence!\n", __FUNCTION__); } s->vrc = value & 0x7f; break; case 0x08: /* GCR */ s->gcr = value & 3; break; default: OMAP_BAD_REG(addr); return; } }


START_TEST(unterminated_array_comma) { QObject *obj = qobject_from_json("[32,"); fail_unless(obj == NULL); }


uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index) { uint64_t token = 0; hwaddr pte_offset; pte_offset = pte_index * HASH_PTE_SIZE_64; if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) { /* * HTAB is controlled by KVM. Fetch the PTEG into a new buffer. */ token = kvmppc_hash64_read_pteg(cpu, pte_index); } else if (cpu->env.external_htab) { /* * HTAB is controlled by QEMU. Just point to the internally * accessible PTEG. */ token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset; } else if (cpu->env.htab_base) { token = cpu->env.htab_base + pte_offset; } return token; }


static inline void gen_neon_negl(TCGv var, int size) { switch (size) { case 0: gen_helper_neon_negl_u16(var, var); break; case 1: gen_helper_neon_negl_u32(var, var); break; case 2: gen_helper_neon_negl_u64(var, var); break; default: abort(); } }


void curses_display_init(DisplayState *ds, int full_screen) { #ifndef _WIN32 if (!isatty(1)) { fprintf(stderr, "We need a terminal output\n"); exit(1); } #endif curses_setup(); curses_keyboard_setup(); atexit(curses_atexit); #ifndef _WIN32 signal(SIGINT, SIG_DFL); signal(SIGQUIT, SIG_DFL); #if defined(SIGWINCH) && defined(KEY_RESIZE) /* some curses implementations provide a handler, but we * want to be sure this is handled regardless of the library */ signal(SIGWINCH, curses_winch_handler); #endif #endif ds->data = (void *) screen; ds->linesize = 0; ds->depth = 0; ds->width = 640; ds->height = 400; ds->dpy_update = curses_update; ds->dpy_resize = curses_resize; ds->dpy_refresh = curses_refresh; ds->dpy_text_cursor = curses_cursor_position; invalidate = 1; /* Standard VGA initial text mode dimensions */ curses_resize(ds, 80, 25); }


void qio_channel_socket_dgram_async(QIOChannelSocket *ioc, SocketAddress *localAddr, SocketAddress *remoteAddr, QIOTaskFunc callback, gpointer opaque, GDestroyNotify destroy) { QIOTask *task = qio_task_new( OBJECT(ioc), callback, opaque, destroy); struct QIOChannelSocketDGramWorkerData *data = g_new0( struct QIOChannelSocketDGramWorkerData, 1); data->localAddr = QAPI_CLONE(SocketAddress, localAddr); data->remoteAddr = QAPI_CLONE(SocketAddress, remoteAddr); trace_qio_channel_socket_dgram_async(ioc, localAddr, remoteAddr); qio_task_run_in_thread(task, qio_channel_socket_dgram_worker, data, qio_channel_socket_dgram_worker_free); }


static av_cold int libx265_encode_init(AVCodecContext *avctx) { libx265Context *ctx = avctx->priv_data; ctx->api = x265_api_get(av_pix_fmt_desc_get(avctx->pix_fmt)->comp[0].depth_minus1 + 1); if (!ctx->api) ctx->api = x265_api_get(0); if (avctx->strict_std_compliance > FF_COMPLIANCE_EXPERIMENTAL && !av_pix_fmt_desc_get(avctx->pix_fmt)->log2_chroma_w) { av_log(avctx, AV_LOG_ERROR, "4:2:2 and 4:4:4 support is not fully defined for HEVC yet. " "Set -strict experimental to encode anyway.\n"); return AVERROR(ENOSYS); } avctx->coded_frame = av_frame_alloc(); if (!avctx->coded_frame) { av_log(avctx, AV_LOG_ERROR, "Could not allocate frame.\n"); return AVERROR(ENOMEM); } ctx->params = ctx->api->param_alloc(); if (!ctx->params) { av_log(avctx, AV_LOG_ERROR, "Could not allocate x265 param structure.\n"); return AVERROR(ENOMEM); } if (ctx->api->param_default_preset(ctx->params, ctx->preset, ctx->tune) < 0) { int i; av_log(avctx, AV_LOG_ERROR, "Error setting preset/tune %s/%s.\n", ctx->preset, ctx->tune); av_log(avctx, AV_LOG_INFO, "Possible presets:"); for (i = 0; x265_preset_names[i]; i++) av_log(avctx, AV_LOG_INFO, " %s", x265_preset_names[i]); av_log(avctx, AV_LOG_INFO, "\n"); av_log(avctx, AV_LOG_INFO, "Possible tunes:"); for (i = 0; x265_tune_names[i]; i++) av_log(avctx, AV_LOG_INFO, " %s", x265_tune_names[i]); av_log(avctx, AV_LOG_INFO, "\n"); return AVERROR(EINVAL); } ctx->params->frameNumThreads = avctx->thread_count; ctx->params->fpsNum = avctx->time_base.den; ctx->params->fpsDenom = avctx->time_base.num * avctx->ticks_per_frame; ctx->params->sourceWidth = avctx->width; ctx->params->sourceHeight = avctx->height; ctx->params->bEnablePsnr = !!(avctx->flags & CODEC_FLAG_PSNR); if ((avctx->color_primaries <= AVCOL_PRI_BT2020 && avctx->color_primaries != AVCOL_PRI_UNSPECIFIED) || (avctx->color_trc <= AVCOL_TRC_BT2020_12 && avctx->color_trc != AVCOL_TRC_UNSPECIFIED) || (avctx->colorspace <= AVCOL_SPC_BT2020_CL && avctx->colorspace != AVCOL_SPC_UNSPECIFIED)) { ctx->params->vui.bEnableVideoSignalTypePresentFlag = 1; ctx->params->vui.bEnableColorDescriptionPresentFlag = 1; // x265 validates the parameters internally ctx->params->vui.colorPrimaries = avctx->color_primaries; ctx->params->vui.transferCharacteristics = avctx->color_trc; ctx->params->vui.matrixCoeffs = avctx->colorspace; } if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0) { char sar[12]; int sar_num, sar_den; av_reduce(&sar_num, &sar_den, avctx->sample_aspect_ratio.num, avctx->sample_aspect_ratio.den, 65535); snprintf(sar, sizeof(sar), "%d:%d", sar_num, sar_den); if (ctx->api->param_parse(ctx->params, "sar", sar) == X265_PARAM_BAD_VALUE) { av_log(avctx, AV_LOG_ERROR, "Invalid SAR: %d:%d.\n", sar_num, sar_den); return AVERROR_INVALIDDATA; } } switch (avctx->pix_fmt) { case AV_PIX_FMT_YUV420P: case AV_PIX_FMT_YUV420P10: ctx->params->internalCsp = X265_CSP_I420; break; case AV_PIX_FMT_YUV422P: case AV_PIX_FMT_YUV422P10: ctx->params->internalCsp = X265_CSP_I422; break; case AV_PIX_FMT_YUV444P: case AV_PIX_FMT_YUV444P10: ctx->params->internalCsp = X265_CSP_I444; break; } if (ctx->crf >= 0) { char crf[6]; snprintf(crf, sizeof(crf), "%2.2f", ctx->crf); if (ctx->api->param_parse(ctx->params, "crf", crf) == X265_PARAM_BAD_VALUE) { av_log(avctx, AV_LOG_ERROR, "Invalid crf: %2.2f.\n", ctx->crf); return AVERROR(EINVAL); } } else if (avctx->bit_rate > 0) { ctx->params->rc.bitrate = avctx->bit_rate / 1000; ctx->params->rc.rateControlMode = X265_RC_ABR; } if (!(avctx->flags & CODEC_FLAG_GLOBAL_HEADER)) ctx->params->bRepeatHeaders = 1; if (ctx->x265_opts) { AVDictionary *dict = NULL; AVDictionaryEntry *en = NULL; if (!av_dict_parse_string(&dict, ctx->x265_opts, "=", ":", 0)) { while ((en = av_dict_get(dict, "", en, AV_DICT_IGNORE_SUFFIX))) { int parse_ret = ctx->api->param_parse(ctx->params, en->key, en->value); switch (parse_ret) { case X265_PARAM_BAD_NAME: av_log(avctx, AV_LOG_WARNING, "Unknown option: %s.\n", en->key); break; case X265_PARAM_BAD_VALUE: av_log(avctx, AV_LOG_WARNING, "Invalid value for %s: %s.\n", en->key, en->value); break; default: break; } } av_dict_free(&dict); } } ctx->encoder = ctx->api->encoder_open(ctx->params); if (!ctx->encoder) { av_log(avctx, AV_LOG_ERROR, "Cannot open libx265 encoder.\n"); libx265_encode_close(avctx); return AVERROR_INVALIDDATA; } if (avctx->flags & CODEC_FLAG_GLOBAL_HEADER) { x265_nal *nal; int nnal; avctx->extradata_size = ctx->api->encoder_headers(ctx->encoder, &nal, &nnal); if (avctx->extradata_size <= 0) { av_log(avctx, AV_LOG_ERROR, "Cannot encode headers.\n"); libx265_encode_close(avctx); return AVERROR_INVALIDDATA; } avctx->extradata = av_malloc(avctx->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE); if (!avctx->extradata) { av_log(avctx, AV_LOG_ERROR, "Cannot allocate HEVC header of size %d.\n", avctx->extradata_size); libx265_encode_close(avctx); return AVERROR(ENOMEM); } memcpy(avctx->extradata, nal[0].payload, avctx->extradata_size); } return 0; }


static uint32_t set_allocation_state(sPAPRDRConnector *drc, sPAPRDRAllocationState state) { sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); trace_spapr_drc_set_allocation_state(get_index(drc), state); if (state == SPAPR_DR_ALLOCATION_STATE_USABLE) { /* if there's no resource/device associated with the DRC, there's * no way for us to put it in an allocation state consistent with * being 'USABLE'. PAPR 2.7, 13.5.3.4 documents that this should * result in an RTAS return code of -3 / "no such indicator" */ if (!drc->dev) { return RTAS_OUT_NO_SUCH_INDICATOR; } if (drc->awaiting_release && drc->awaiting_allocation) { /* kernel is acknowledging a previous hotplug event * while we are already removing it. * it's safe to ignore awaiting_allocation here since we know the * situation is predicated on the guest either already having done * so (boot-time hotplug), or never being able to acquire in the * first place (hotplug followed by immediate unplug). */ drc->awaiting_allocation_skippable = true; return RTAS_OUT_NO_SUCH_INDICATOR; } } if (drc->type != SPAPR_DR_CONNECTOR_TYPE_PCI) { drc->allocation_state = state; if (drc->awaiting_release && drc->allocation_state == SPAPR_DR_ALLOCATION_STATE_UNUSABLE) { trace_spapr_drc_set_allocation_state_finalizing(get_index(drc)); drck->detach(drc, DEVICE(drc->dev), drc->detach_cb, drc->detach_cb_opaque, NULL); } else if (drc->allocation_state == SPAPR_DR_ALLOCATION_STATE_USABLE) { drc->awaiting_allocation = false; } } return RTAS_OUT_SUCCESS; }


static void vfio_pci_reset_handler(void *opaque) { VFIOGroup *group; VFIOPCIDevice *vdev; QLIST_FOREACH(group, &group_list, next) { QLIST_FOREACH(vdev, &group->device_list, next) { if (!vdev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { vdev->needs_reset = true; } } } QLIST_FOREACH(group, &group_list, next) { QLIST_FOREACH(vdev, &group->device_list, next) { if (vdev->needs_reset) { vfio_pci_hot_reset_multi(vdev); } } } }


static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); mc->init = machvirt_init; /* Start max_cpus at the maximum QEMU supports. We'll further restrict * it later in machvirt_init, where we have more information about the * configuration of the particular instance. */ mc->max_cpus = MAX_CPUMASK_BITS; mc->has_dynamic_sysbus = true; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; mc->pci_allow_0_address = true; }


static void xtensa_lx60_init(MachineState *machine) { static const LxBoardDesc lx60_board = { .flash_base = 0xf8000000, .flash_size = 0x00400000, .flash_sector_size = 0x10000, .sram_size = 0x20000, }; lx_init(&lx60_board, machine); }


int udp_output2(struct socket *so, struct mbuf *m, struct sockaddr_in *saddr, struct sockaddr_in *daddr, int iptos) { register struct udpiphdr *ui; int error = 0; DEBUG_CALL("udp_output"); DEBUG_ARG("so = %p", so); DEBUG_ARG("m = %p", m); DEBUG_ARG("saddr = %lx", (long)saddr->sin_addr.s_addr); DEBUG_ARG("daddr = %lx", (long)daddr->sin_addr.s_addr); /* * Adjust for header */ m->m_data -= sizeof(struct udpiphdr); m->m_len += sizeof(struct udpiphdr); /* * Fill in mbuf with extended UDP header * and addresses and length put into network format. */ ui = mtod(m, struct udpiphdr *); memset(&ui->ui_i.ih_mbuf, 0 , sizeof(struct mbuf_ptr)); ui->ui_x1 = 0; ui->ui_pr = IPPROTO_UDP; ui->ui_len = htons(m->m_len - sizeof(struct ip)); /* XXXXX Check for from-one-location sockets, or from-any-location sockets */ ui->ui_src = saddr->sin_addr; ui->ui_dst = daddr->sin_addr; ui->ui_sport = saddr->sin_port; ui->ui_dport = daddr->sin_port; ui->ui_ulen = ui->ui_len; /* * Stuff checksum and output datagram. */ ui->ui_sum = 0; if ((ui->ui_sum = cksum(m, m->m_len)) == 0) ui->ui_sum = 0xffff; ((struct ip *)ui)->ip_len = m->m_len; ((struct ip *)ui)->ip_ttl = IPDEFTTL; ((struct ip *)ui)->ip_tos = iptos; error = ip_output(so, m); return (error); }


static void sigp_initial_cpu_reset(CPUState *cs, run_on_cpu_data arg) { S390CPU *cpu = S390_CPU(cs); S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); SigpInfo *si = arg.host_ptr; cpu_synchronize_state(cs); scc->initial_cpu_reset(cs); cpu_synchronize_post_reset(cs); si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; }


void cris_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) { unsigned int i; (*cpu_fprintf)(f, "Available CPUs:\n"); for (i = 0; i < ARRAY_SIZE(cris_cores); i++) { (*cpu_fprintf)(f, " %s\n", cris_cores[i].name); } }


void GCC_FMT_ATTR(2, 3) virtio_error(VirtIODevice *vdev, const char *fmt, ...) { va_list ap; va_start(ap, fmt); error_vreport(fmt, ap); va_end(ap); vdev->broken = true; if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) { virtio_set_status(vdev, vdev->status | VIRTIO_CONFIG_S_NEEDS_RESET); virtio_notify_config(vdev); } }


const char *avcodec_configuration(void) { return FFMPEG_CONFIGURATION; }


av_cold void ff_ps_ctx_init(PSContext *ps) { ipdopd_reset(ps->ipd_hist, ps->opd_hist); }


void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) { if (row >= 5 || row < 0) hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); if (down) s->buttons[row] |= 1 << col; else s->buttons[row] &= ~(1 << col); omap_mpuio_kbd_update(s); }


int ff_put_wav_header(AVIOContext *pb, AVCodecContext *enc) { int bps, blkalign, bytespersec; int hdrsize = 18; int waveformatextensible; uint8_t temp[256]; uint8_t *riff_extradata= temp; uint8_t *riff_extradata_start= temp; if(!enc->codec_tag || enc->codec_tag > 0xffff) return -1; waveformatextensible = (enc->channels > 2 && enc->channel_layout) || enc->sample_rate > 48000 || av_get_bits_per_sample(enc->codec_id) > 16; if (waveformatextensible) { avio_wl16(pb, 0xfffe); } else { avio_wl16(pb, enc->codec_tag); } avio_wl16(pb, enc->channels); avio_wl32(pb, enc->sample_rate); if (enc->codec_id == CODEC_ID_MP2 || enc->codec_id == CODEC_ID_MP3 || enc->codec_id == CODEC_ID_GSM_MS) { bps = 0; } else if (enc->codec_id == CODEC_ID_ADPCM_G726) { bps = 4; } else { if (!(bps = av_get_bits_per_sample(enc->codec_id))) bps = 16; // default to 16 } if(bps != enc->bits_per_coded_sample && enc->bits_per_coded_sample){ av_log(enc, AV_LOG_WARNING, "requested bits_per_coded_sample (%d) and actually stored (%d) differ\n", enc->bits_per_coded_sample, bps); } if (enc->codec_id == CODEC_ID_MP2 || enc->codec_id == CODEC_ID_MP3) { blkalign = enc->frame_size; //this is wrong, but it seems many demuxers do not work if this is set correctly //blkalign = 144 * enc->bit_rate/enc->sample_rate; } else if (enc->codec_id == CODEC_ID_AC3) { blkalign = 3840; //maximum bytes per frame } else if (enc->codec_id == CODEC_ID_ADPCM_G726) { // blkalign = 1; } else if (enc->block_align != 0) { /* specified by the codec */ blkalign = enc->block_align; } else blkalign = enc->channels*bps >> 3; if (enc->codec_id == CODEC_ID_PCM_U8 || enc->codec_id == CODEC_ID_PCM_S24LE || enc->codec_id == CODEC_ID_PCM_S32LE || enc->codec_id == CODEC_ID_PCM_F32LE || enc->codec_id == CODEC_ID_PCM_F64LE || enc->codec_id == CODEC_ID_PCM_S16LE) { bytespersec = enc->sample_rate * blkalign; } else { bytespersec = enc->bit_rate / 8; } avio_wl32(pb, bytespersec); /* bytes per second */ avio_wl16(pb, blkalign); /* block align */ avio_wl16(pb, bps); /* bits per sample */ if (enc->codec_id == CODEC_ID_MP3) { hdrsize += 12; bytestream_put_le16(&riff_extradata, 1); /* wID */ bytestream_put_le32(&riff_extradata, 2); /* fdwFlags */ bytestream_put_le16(&riff_extradata, 1152); /* nBlockSize */ bytestream_put_le16(&riff_extradata, 1); /* nFramesPerBlock */ bytestream_put_le16(&riff_extradata, 1393); /* nCodecDelay */ } else if (enc->codec_id == CODEC_ID_MP2) { hdrsize += 22; bytestream_put_le16(&riff_extradata, 2); /* fwHeadLayer */ bytestream_put_le32(&riff_extradata, enc->bit_rate); /* dwHeadBitrate */ bytestream_put_le16(&riff_extradata, enc->channels == 2 ? 1 : 8); /* fwHeadMode */ bytestream_put_le16(&riff_extradata, 0); /* fwHeadModeExt */ bytestream_put_le16(&riff_extradata, 1); /* wHeadEmphasis */ bytestream_put_le16(&riff_extradata, 16); /* fwHeadFlags */ bytestream_put_le32(&riff_extradata, 0); /* dwPTSLow */ bytestream_put_le32(&riff_extradata, 0); /* dwPTSHigh */ } else if (enc->codec_id == CODEC_ID_GSM_MS || enc->codec_id == CODEC_ID_ADPCM_IMA_WAV) { hdrsize += 2; bytestream_put_le16(&riff_extradata, enc->frame_size); /* wSamplesPerBlock */ } else if(enc->extradata_size){ riff_extradata_start= enc->extradata; riff_extradata= enc->extradata + enc->extradata_size; hdrsize += enc->extradata_size; } else if (!waveformatextensible){ hdrsize -= 2; } if(waveformatextensible) { /* write WAVEFORMATEXTENSIBLE extensions */ hdrsize += 22; avio_wl16(pb, riff_extradata - riff_extradata_start + 22); /* 22 is WAVEFORMATEXTENSIBLE size */ avio_wl16(pb, enc->bits_per_coded_sample); /* ValidBitsPerSample || SamplesPerBlock || Reserved */ avio_wl32(pb, enc->channel_layout); /* dwChannelMask */ avio_wl32(pb, enc->codec_tag); /* GUID + next 3 */ avio_wl32(pb, 0x00100000); avio_wl32(pb, 0xAA000080); avio_wl32(pb, 0x719B3800); } else if(riff_extradata - riff_extradata_start) { avio_wl16(pb, riff_extradata - riff_extradata_start); } avio_write(pb, riff_extradata_start, riff_extradata - riff_extradata_start); if(hdrsize&1){ hdrsize++; avio_w8(pb, 0); } return hdrsize; }


static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) { CPUState *cpu = current_cpu; CPUClass *cc = CPU_GET_CLASS(cpu); CPUArchState *env = cpu->env_ptr; target_ulong pc, cs_base; target_ulong vaddr; CPUWatchpoint *wp; uint32_t cpu_flags; assert(tcg_enabled()); if (cpu->watchpoint_hit) { /* We re-entered the check after replacing the TB. Now raise * the debug interrupt so that is will trigger after the * current instruction. */ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); return; } vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (cpu_watchpoint_address_matches(wp, vaddr, len) && (wp->flags & flags)) { if (flags == BP_MEM_READ) { wp->flags |= BP_WATCHPOINT_HIT_READ; } else { wp->flags |= BP_WATCHPOINT_HIT_WRITE; } wp->hitaddr = vaddr; wp->hitattrs = attrs; if (!cpu->watchpoint_hit) { if (wp->flags & BP_CPU && !cc->debug_check_watchpoint(cpu, wp)) { wp->flags &= ~BP_WATCHPOINT_HIT; continue; } cpu->watchpoint_hit = wp; /* Both tb_lock and iothread_mutex will be reset when * cpu_loop_exit or cpu_loop_exit_noexc longjmp * back into the cpu_exec main loop. */ tb_lock(); tb_check_watchpoint(cpu); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cflags()); cpu_loop_exit_noexc(cpu); } } } else { wp->flags &= ~BP_WATCHPOINT_HIT; } } }


dbdma_control_write(DBDMA_channel *ch) { uint16_t mask, value; uint32_t status; mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff; value = ch->regs[DBDMA_CONTROL] & 0xffff; value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); status = ch->regs[DBDMA_STATUS]; status = (value & mask) | (status & ~mask); if (status & WAKE) status |= ACTIVE; if (status & RUN) { status |= ACTIVE; status &= ~DEAD; } if (status & PAUSE) status &= ~ACTIVE; if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) { /* RUN is cleared */ status &= ~(ACTIVE|DEAD); } DBDMA_DPRINTF(" status 0x%08x\n", status); ch->regs[DBDMA_STATUS] = status; if (status & ACTIVE) qemu_bh_schedule(dbdma_bh); if (status & FLUSH) ch->flush(&ch->io); }


static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi) { ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); /* Read an LPAE long-descriptor translation table. */ MMUFaultType fault_type = translation_fault; uint32_t level; uint32_t epd = 0; int32_t t0sz, t1sz; uint32_t tg; uint64_t ttbr; int ttbr_select; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; uint32_t attrs; int32_t stride = 9; int32_t va_size; int inputsize; int32_t tbi = 0; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); bool ttbr1_valid = true; uint64_t descaddrmask; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. * This code also does not support shareability levels. * Attribute and permission bit handling should also be checked when adding * support for those page table walks. */ if (arm_el_is_aa64(env, el)) { level = 0; va_size = 64; if (el > 1) { if (mmu_idx != ARMMMUIdx_S2NS) { tbi = extract64(tcr->raw_tcr, 20, 1); } } else { if (extract64(address, 55, 1)) { tbi = extract64(tcr->raw_tcr, 38, 1); } else { tbi = extract64(tcr->raw_tcr, 37, 1); } } tbi *= 8; /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it * invalid. */ if (el > 1) { ttbr1_valid = false; } } else { level = 1; va_size = 32; /* There is no TTBR1 for EL2 */ if (el == 2) { ttbr1_valid = false; } } /* Determine whether this address is in the region controlled by * TTBR0 or TTBR1 (or if it is in neither region and should fault). * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ if (va_size == 64) { /* AArch64 translation. */ t0sz = extract32(tcr->raw_tcr, 0, 6); t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } else if (mmu_idx != ARMMMUIdx_S2NS) { /* AArch32 stage 1 translation. */ t0sz = extract32(tcr->raw_tcr, 0, 3); } else { /* AArch32 stage 2 translation. */ bool sext = extract32(tcr->raw_tcr, 4, 1); bool sign = extract32(tcr->raw_tcr, 3, 1); t0sz = sextract32(tcr->raw_tcr, 0, 4); /* If the sign-extend bit is not the same as t0sz[3], the result * is unpredictable. Flag this as a guest error. */ if (sign != sext) { qemu_log_mask(LOG_GUEST_ERROR, "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n"); } } t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16); } if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { /* there is a ttbr0 region and we are in it (high bits all zero) */ ttbr_select = 0; } else if (ttbr1_valid && t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) { /* there is a ttbr1 region and we are in it (high bits all one) */ ttbr_select = 1; } else if (!t0sz) { /* ttbr0 region is "everything not in the ttbr1 region" */ ttbr_select = 0; } else if (!t1sz && ttbr1_valid) { /* ttbr1 region is "everything not in the ttbr0 region" */ ttbr_select = 1; } else { /* in the gap between the two regions, this is a Translation fault */ fault_type = translation_fault; goto do_fault; } /* Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ if (ttbr_select == 0) { ttbr = regime_ttbr(env, mmu_idx, 0); if (el < 2) { epd = extract32(tcr->raw_tcr, 7, 1); } inputsize = va_size - t0sz; tg = extract32(tcr->raw_tcr, 14, 2); if (tg == 1) { /* 64KB pages */ stride = 13; } if (tg == 2) { /* 16KB pages */ stride = 11; } } else { /* We should only be here if TTBR1 is valid */ assert(ttbr1_valid); ttbr = regime_ttbr(env, mmu_idx, 1); epd = extract32(tcr->raw_tcr, 23, 1); inputsize = va_size - t1sz; tg = extract32(tcr->raw_tcr, 30, 2); if (tg == 3) { /* 64KB pages */ stride = 13; } if (tg == 1) { /* 16KB pages */ stride = 11; } } /* Here we should have set up all the parameters for the translation: * va_size, inputsize, ttbr, epd, stride, tbi */ if (epd) { /* Translation table walk disabled => Translation fault on TLB miss * Note: This is always 0 on 64-bit EL2 and EL3. */ goto do_fault; } if (mmu_idx != ARMMMUIdx_S2NS) { /* The starting level depends on the virtual address size (which can * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to * consume the bits of the input address. In the pseudocode this is: * level = 4 - RoundUp((inputsize - grainsize) / stride) * where their 'inputsize' is our 'inputsize', 'grainsize' is * our 'stride + 3' and 'stride' is our 'stride'. * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: * = 4 - (inputsize - stride - 3 + stride - 1) / stride * = 4 - (inputsize - 4) / stride; */ level = 4 - (inputsize - 4) / stride; } else { /* For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); uint32_t startlevel; bool ok; if (va_size == 32 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; } else { /* 16KB or 64KB pages */ startlevel = 3 - sl0; } /* Check that the starting level is valid. */ ok = check_s2_mmu_setup(cpu, va_size == 64, startlevel, inputsize, stride); if (!ok) { fault_type = translation_fault; goto do_fault; } level = startlevel; } indexmask_grainsize = (1ULL << (stride + 3)) - 1; indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); descaddr &= ~indexmask; /* The address field in the descriptor goes up to bit 39 for ARMv7 * but up to bit 47 for ARMv8, but we use the descaddrmask * up to bit 39 for AArch32, because we don't need other bits in that case * to construct next descriptor address (anyway they should be all zeroes). */ descaddrmask = ((1ull << (va_size == 64 ? 48 : 40)) - 1) & ~indexmask_grainsize; /* Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. */ tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); for (;;) { uint64_t descriptor; bool nstable; descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); if (fi->s1ptw) { goto do_fault; } if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { /* Invalid, or the Reserved level 3 encoding */ goto do_fault; } descaddr = descriptor & descaddrmask; if ((descriptor & 2) && (level < 3)) { /* Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). */ tableattrs |= extract64(descriptor, 59, 5); level++; indexmask = indexmask_grainsize; continue; } /* Block entry at level 1 or 2, or page entry at level 3. * These are basically the same thing, although the number * of bits we pull in from the vaddr varies. */ page_size = (1ULL << ((stride * (4 - level)) + 3)); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor */ attrs = extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); if (mmu_idx == ARMMMUIdx_S2NS) { /* Stage 2 table descriptors do not include any attribute fields */ break; } /* Merge in attributes from table descriptors */ attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ if (extract32(tableattrs, 2, 1)) { attrs &= ~(1 << 4); } attrs |= nstable << 3; /* NS */ break; } /* Here descaddr is the final physical address, and attributes * are all in attrs. */ fault_type = access_fault; if ((attrs & (1 << 8)) == 0) { /* Access flag */ goto do_fault; } ap = extract32(attrs, 4, 2); xn = extract32(attrs, 12, 1); if (mmu_idx == ARMMMUIdx_S2NS) { ns = true; *prot = get_S2prot(env, ap, xn); } else { ns = extract32(attrs, 3, 1); pxn = extract32(attrs, 11, 1); *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); } fault_type = permission_fault; if (!(*prot & (1 << access_type))) { goto do_fault; } if (ns) { /* The NS bit will (as required by the architecture) have no effect if * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ txattrs->secure = false; } *phys_ptr = descaddr; *page_size_ptr = page_size; return false; do_fault: /* Long-descriptor format IFSR/DFSR value */ *fsr = (1 << 9) | (fault_type << 2) | level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); return true; }


static void monitor_parse(const char *optarg, const char *mode, bool pretty) { static int monitor_device_index = 0; Error *local_err = NULL; QemuOpts *opts; const char *p; char label[32]; int def = 0; if (strstart(optarg, "chardev:", &p)) { snprintf(label, sizeof(label), "%s", p); } else { snprintf(label, sizeof(label), "compat_monitor%d", monitor_device_index); if (monitor_device_index == 0) { def = 1; } opts = qemu_chr_parse_compat(label, optarg); if (!opts) { fprintf(stderr, "parse error: %s\n", optarg); exit(1); } } opts = qemu_opts_create(qemu_find_opts("mon"), label, 1, &local_err); if (!opts) { error_report_err(local_err); exit(1); } qemu_opt_set(opts, "mode", mode, &error_abort); qemu_opt_set(opts, "chardev", label, &error_abort); qemu_opt_set_bool(opts, "pretty", pretty, &error_abort); if (def) qemu_opt_set(opts, "default", "on", &error_abort); monitor_device_index++; }


void drive_hot_add(Monitor *mon, const QDict *qdict) { int dom, pci_bus; unsigned slot; int type, bus; int success = 0; PCIDevice *dev; DriveInfo *dinfo; const char *pci_addr = qdict_get_str(qdict, "pci_addr"); const char *opts = qdict_get_str(qdict, "opts"); BusState *scsibus; if (pci_read_devaddr(mon, pci_addr, &dom, &pci_bus, &slot)) { return; } dev = pci_find_device(pci_bus, slot, 0); if (!dev) { monitor_printf(mon, "no pci device with address %s\n", pci_addr); return; } dinfo = add_init_drive(opts); if (!dinfo) return; if (dinfo->devaddr) { monitor_printf(mon, "Parameter addr not supported\n"); return; } type = dinfo->type; bus = drive_get_max_bus (type); switch (type) { case IF_SCSI: success = 1; scsibus = LIST_FIRST(&dev->qdev.child_bus); scsi_bus_legacy_add_drive(DO_UPCAST(SCSIBus, qbus, scsibus), dinfo, dinfo->unit); break; default: monitor_printf(mon, "Can't hot-add drive to type %d\n", type); } if (success) monitor_printf(mon, "OK bus %d, unit %d\n", dinfo->bus, dinfo->unit); return; }


build_append_notify(GArray *device, const char *name, const char *format, int skip, int count) { int i; GArray *method = build_alloc_array(); uint8_t op = 0x14; /* MethodOp */ build_append_nameseg(method, "%s", name); build_append_byte(method, 0x02); /* MethodFlags: ArgCount */ for (i = skip; i < count; i++) { GArray *target = build_alloc_array(); build_append_nameseg(target, format, i); assert(i < 256); /* Fits in 1 byte */ build_append_notify_target(method, target, i, 1); build_free_array(target); } build_package(method, op, 2); build_append_array(device, method); build_free_array(method); }


void virtio_input_send(VirtIOInput *vinput, virtio_input_event *event) { VirtQueueElement *elem; unsigned have, need; int i, len; if (!vinput->active) { return; } /* queue up events ... */ if (vinput->qindex == vinput->qsize) { vinput->qsize++; vinput->queue = g_realloc(vinput->queue, vinput->qsize * sizeof(virtio_input_event)); } vinput->queue[vinput->qindex++] = *event; /* ... until we see a report sync ... */ if (event->type != cpu_to_le16(EV_SYN) || event->code != cpu_to_le16(SYN_REPORT)) { return; } /* ... then check available space ... */ need = sizeof(virtio_input_event) * vinput->qindex; virtqueue_get_avail_bytes(vinput->evt, &have, NULL, need, 0); if (have < need) { vinput->qindex = 0; trace_virtio_input_queue_full(); return; } /* ... and finally pass them to the guest */ for (i = 0; i < vinput->qindex; i++) { elem = virtqueue_pop(vinput->evt, sizeof(VirtQueueElement)); if (!elem) { /* should not happen, we've checked for space beforehand */ fprintf(stderr, "%s: Huh? No vq elem available ...\n", __func__); return; } len = iov_from_buf(elem->in_sg, elem->in_num, 0, vinput->queue+i, sizeof(virtio_input_event)); virtqueue_push(vinput->evt, elem, len); g_free(elem); } virtio_notify(VIRTIO_DEVICE(vinput), vinput->evt); vinput->qindex = 0; }


int bdrv_aio_multiwrite(BlockDriverState *bs, BlockRequest *reqs, int num_reqs) { MultiwriteCB *mcb; int i; /* don't submit writes if we don't have a medium */ if (bs->drv == NULL) { for (i = 0; i < num_reqs; i++) { reqs[i].error = -ENOMEDIUM; } return -1; } if (num_reqs == 0) { return 0; } // Create MultiwriteCB structure mcb = g_malloc0(sizeof(*mcb) + num_reqs * sizeof(*mcb->callbacks)); mcb->num_requests = 0; mcb->num_callbacks = num_reqs; for (i = 0; i < num_reqs; i++) { mcb->callbacks[i].cb = reqs[i].cb; mcb->callbacks[i].opaque = reqs[i].opaque; } // Check for mergable requests num_reqs = multiwrite_merge(bs, reqs, num_reqs, mcb); trace_bdrv_aio_multiwrite(mcb, mcb->num_callbacks, num_reqs); /* Run the aio requests. */ mcb->num_requests = num_reqs; for (i = 0; i < num_reqs; i++) { bdrv_co_aio_rw_vector(bs, reqs[i].sector, reqs[i].qiov, reqs[i].nb_sectors, reqs[i].flags, multiwrite_cb, mcb, true); } return 0; }


static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; int ch = addr >> 6; uint8_t byte = value; if (size != 1) { return omap_badwidth_write8(opaque, addr, size); } if (ch == STI_TRACE_CONTROL_CHANNEL) { /* Flush channel value. */ qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1); } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { if (value == 0xc0 || value == 0xc3) { /* Open channel ch. */ } else if (value == 0x00) qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1); else qemu_chr_fe_write(s->chr, &byte, 1); } }


static void active_parameter_sets(HEVCContext *s) { GetBitContext *gb = &s->HEVClc->gb; int num_sps_ids_minus1; int i; get_bits(gb, 4); // active_video_parameter_set_id get_bits(gb, 1); // self_contained_cvs_flag get_bits(gb, 1); // num_sps_ids_minus1 num_sps_ids_minus1 = get_ue_golomb_long(gb); // num_sps_ids_minus1 s->active_seq_parameter_set_id = get_ue_golomb_long(gb); for (i = 1; i <= num_sps_ids_minus1; i++) get_ue_golomb_long(gb); // active_seq_parameter_set_id[i] }


static void term_backward_char(void) { if (term_cmd_buf_index > 0) { term_cmd_buf_index--; } }


static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); }


static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, uint32_t val) { int dirty_flags; dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; if (!(dirty_flags & CODE_DIRTY_FLAG)) { #if !defined(CONFIG_USER_ONLY) tb_invalidate_phys_page_fast(ram_addr, 1); dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; #endif } stb_p(qemu_get_ram_ptr(ram_addr), val); #ifdef CONFIG_KQEMU if (cpu_single_env->kqemu_enabled && (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) kqemu_modify_page(cpu_single_env, ram_addr); #endif dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; /* we remove the notdirty callback only if the code has been flushed */ if (dirty_flags == 0xff) tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); }


BlockJob *backup_job_create(const char *job_id, BlockDriverState *bs, BlockDriverState *target, int64_t speed, MirrorSyncMode sync_mode, BdrvDirtyBitmap *sync_bitmap, bool compress, BlockdevOnError on_source_error, BlockdevOnError on_target_error, int creation_flags, BlockCompletionFunc *cb, void *opaque, BlockJobTxn *txn, Error **errp) { int64_t len; BlockDriverInfo bdi; BackupBlockJob *job = NULL; int ret; assert(bs); assert(target); if (bs == target) { error_setg(errp, "Source and target cannot be the same"); return NULL; } if (!bdrv_is_inserted(bs)) { error_setg(errp, "Device is not inserted: %s", bdrv_get_device_name(bs)); return NULL; } if (!bdrv_is_inserted(target)) { error_setg(errp, "Device is not inserted: %s", bdrv_get_device_name(target)); return NULL; } if (compress && target->drv->bdrv_co_pwritev_compressed == NULL) { error_setg(errp, "Compression is not supported for this drive %s", bdrv_get_device_name(target)); return NULL; } if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_BACKUP_SOURCE, errp)) { return NULL; } if (bdrv_op_is_blocked(target, BLOCK_OP_TYPE_BACKUP_TARGET, errp)) { return NULL; } if (sync_mode == MIRROR_SYNC_MODE_INCREMENTAL) { if (!sync_bitmap) { error_setg(errp, "must provide a valid bitmap name for " "\"incremental\" sync mode"); return NULL; } /* Create a new bitmap, and freeze/disable this one. */ if (bdrv_dirty_bitmap_create_successor(bs, sync_bitmap, errp) < 0) { return NULL; } } else if (sync_bitmap) { error_setg(errp, "a sync_bitmap was provided to backup_run, " "but received an incompatible sync_mode (%s)", MirrorSyncMode_lookup[sync_mode]); return NULL; } len = bdrv_getlength(bs); if (len < 0) { error_setg_errno(errp, -len, "unable to get length for '%s'", bdrv_get_device_name(bs)); goto error; } /* job->common.len is fixed, so we can't allow resize */ job = block_job_create(job_id, &backup_job_driver, bs, BLK_PERM_CONSISTENT_READ, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE | BLK_PERM_WRITE_UNCHANGED | BLK_PERM_GRAPH_MOD, speed, creation_flags, cb, opaque, errp); if (!job) { goto error; } /* The target must match the source in size, so no resize here either */ job->target = blk_new(BLK_PERM_WRITE, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE | BLK_PERM_WRITE_UNCHANGED | BLK_PERM_GRAPH_MOD); ret = blk_insert_bs(job->target, target, errp); if (ret < 0) { goto error; } job->on_source_error = on_source_error; job->on_target_error = on_target_error; job->sync_mode = sync_mode; job->sync_bitmap = sync_mode == MIRROR_SYNC_MODE_INCREMENTAL ? sync_bitmap : NULL; job->compress = compress; /* If there is no backing file on the target, we cannot rely on COW if our * backup cluster size is smaller than the target cluster size. Even for * targets with a backing file, try to avoid COW if possible. */ ret = bdrv_get_info(target, &bdi); if (ret == -ENOTSUP && !target->backing) { /* Cluster size is not defined */ error_report("WARNING: The target block device doesn't provide " "information about the block size and it doesn't have a " "backing file. The default block size of %u bytes is " "used. If the actual block size of the target exceeds " "this default, the backup may be unusable", BACKUP_CLUSTER_SIZE_DEFAULT); job->cluster_size = BACKUP_CLUSTER_SIZE_DEFAULT; } else if (ret < 0 && !target->backing) { error_setg_errno(errp, -ret, "Couldn't determine the cluster size of the target image, " "which has no backing file"); error_append_hint(errp, "Aborting, since this may create an unusable destination image\n"); goto error; } else if (ret < 0 && target->backing) { /* Not fatal; just trudge on ahead. */ job->cluster_size = BACKUP_CLUSTER_SIZE_DEFAULT; } else { job->cluster_size = MAX(BACKUP_CLUSTER_SIZE_DEFAULT, bdi.cluster_size); } /* Required permissions are already taken with target's blk_new() */ block_job_add_bdrv(&job->common, "target", target, 0, BLK_PERM_ALL, &error_abort); job->common.len = len; block_job_txn_add_job(txn, &job->common); return &job->common; error: if (sync_bitmap) { bdrv_reclaim_dirty_bitmap(bs, sync_bitmap, NULL); } if (job) { backup_clean(&job->common); block_job_early_fail(&job->common); } return NULL; }


void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { CPUState *cs = CPU(x86_env_get_cpu(env)); target_ulong addr; uint32_t event_inj; uint32_t int_ctl; cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0); if (aflag == 2) { addr = env->regs[R_EAX]; } else { addr = (uint32_t)env->regs[R_EAX]; } qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmrun! " TARGET_FMT_lx "\n", addr); env->vm_vmcb = addr; /* save the current CPU state in the hsave page */ stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base), env->gdt.base); stl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit), env->gdt.limit); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.base), env->idt.base); stl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit), env->idt.limit); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.rflags), cpu_compute_eflags(env)); svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es), &env->segs[R_ES]); svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs), &env->segs[R_CS]); svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss), &env->segs[R_SS]); svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds), &env->segs[R_DS]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.rip), env->eip + next_eip_addend); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]); stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]); /* load the interception bitmaps so we do not need to access the vmcb in svm mode */ env->intercept = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept)); env->intercept_cr_read = lduw_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_cr_read)); env->intercept_cr_write = lduw_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_cr_write)); env->intercept_dr_read = lduw_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_dr_read)); env->intercept_dr_write = lduw_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_dr_write)); env->intercept_exceptions = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_exceptions )); /* enable intercepts */ env->hflags |= HF_SVMI_MASK; env->tsc_offset = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.tsc_offset)); env->gdt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base)); env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit)); env->idt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base)); env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit)); /* clear exit_info_2 so we behave like the real hardware */ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0); cpu_x86_update_cr0(env, ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cr0))); cpu_x86_update_cr4(env, ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cr4))); cpu_x86_update_cr3(env, ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cr3))); env->cr[2] = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cr2)); int_ctl = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK); if (int_ctl & V_INTR_MASKING_MASK) { env->v_tpr = int_ctl & V_TPR_MASK; env->hflags2 |= HF2_VINTR_MASK; if (env->eflags & IF_MASK) { env->hflags2 |= HF2_HIF_MASK; } } cpu_load_efer(env, ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.efer))); env->eflags = 0; cpu_load_eflags(env, ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rflags)), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); CC_OP = CC_OP_EFLAGS; svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es), R_ES); svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs), R_CS); svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss), R_SS); svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds), R_DS); env->eip = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rip)); env->regs[R_ESP] = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rsp)); env->regs[R_EAX] = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rax)); env->dr[7] = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.dr7)); env->dr[6] = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.dr6)); cpu_x86_set_cpl(env, ldub_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cpl))); /* FIXME: guest state consistency checks */ switch (ldub_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) { case TLB_CONTROL_DO_NOTHING: break; case TLB_CONTROL_FLUSH_ALL_ASID: /* FIXME: this is not 100% correct but should work for now */ tlb_flush(cs, 1); break; } env->hflags2 |= HF2_GIF_MASK; if (int_ctl & V_IRQ_MASK) { CPUState *cs = CPU(x86_env_get_cpu(env)); cs->interrupt_request |= CPU_INTERRUPT_VIRQ; } /* maybe we need to inject an event */ event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); if (event_inj & SVM_EVTINJ_VALID) { uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK; uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR; uint32_t event_inj_err = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err)); qemu_log_mask(CPU_LOG_TB_IN_ASM, "Injecting(%#hx): ", valid_err); /* FIXME: need to implement valid_err */ switch (event_inj & SVM_EVTINJ_TYPE_MASK) { case SVM_EVTINJ_TYPE_INTR: cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; qemu_log_mask(CPU_LOG_TB_IN_ASM, "INTR"); /* XXX: is it always correct? */ do_interrupt_x86_hardirq(env, vector, 1); break; case SVM_EVTINJ_TYPE_NMI: cs->exception_index = EXCP02_NMI; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI"); cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_EXEPT: cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT"); cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_SOFT: cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 1; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT"); cpu_loop_exit(cs); break; } qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, env->error_code); } }


static void spr_write_ibatu (void *opaque, int sprn) { DisasContext *ctx = opaque; gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2); RET_STOP(ctx); }


static void machine_numa_validate(MachineState *machine) { int i; GString *s = g_string_new(NULL); MachineClass *mc = MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); assert(nb_numa_nodes); for (i = 0; i < possible_cpus->len; i++) { const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; /* at this point numa mappings are initilized by CLI options * or with default mappings so it's sufficient to list * all not yet mapped CPUs here */ /* TODO: make it hard error in future */ if (!cpu_slot->props.has_node_id) { char *cpu_str = cpu_slot_to_string(cpu_slot); g_string_append_printf(s, "%sCPU %d [%s]", s->len ? ", " : "", i, cpu_str); g_free(cpu_str); } } if (s->len) { error_report("warning: CPU(s) not present in any NUMA nodes: %s", s->str); error_report("warning: All CPU(s) up to maxcpus should be described " "in NUMA config, ability to start up with partial NUMA " "mappings is obsoleted and will be removed in future"); } g_string_free(s, true); }


int qcow2_refcount_init(BlockDriverState *bs) { BDRVQcowState *s = bs->opaque; unsigned int refcount_table_size2, i; int ret; assert(s->refcount_table_size <= INT_MAX / sizeof(uint64_t)); refcount_table_size2 = s->refcount_table_size * sizeof(uint64_t); s->refcount_table = g_try_malloc(refcount_table_size2); if (s->refcount_table_size > 0) { if (s->refcount_table == NULL) { goto fail; } BLKDBG_EVENT(bs->file, BLKDBG_REFTABLE_LOAD); ret = bdrv_pread(bs->file, s->refcount_table_offset, s->refcount_table, refcount_table_size2); if (ret != refcount_table_size2) goto fail; for(i = 0; i < s->refcount_table_size; i++) be64_to_cpus(&s->refcount_table[i]); } return 0; fail: return -ENOMEM; }