static av_cold int psy_3gpp_init(FFPsyContext *ctx) { AacPsyContext *pctx; float bark; int i, j, g, start; float prev, minscale, minath, minsnr, pe_min; int chan_bitrate = ctx->avctx->bit_rate / ((ctx->avctx->flags & CODEC_FLAG_QSCALE) ? 2.0f : ctx->avctx->channels); const int bandwidth = ctx->avctx->cutoff ? ctx->avctx->cutoff : AAC_CUTOFF(ctx->avctx); const float num_bark = calc_bark((float)bandwidth); ctx->model_priv_data = av_mallocz(sizeof(AacPsyContext)); if (!ctx->model_priv_data) return AVERROR(ENOMEM); pctx = (AacPsyContext*) ctx->model_priv_data; pctx->global_quality = (ctx->avctx->global_quality ? ctx->avctx->global_quality : 120) * 0.01f; if (ctx->avctx->flags & CODEC_FLAG_QSCALE) { /* Use the target average bitrate to compute spread parameters */ chan_bitrate = (int)(chan_bitrate / 120.0 * (ctx->avctx->global_quality ? ctx->avctx->global_quality : 120)); } pctx->chan_bitrate = chan_bitrate; pctx->frame_bits = FFMIN(2560, chan_bitrate * AAC_BLOCK_SIZE_LONG / ctx->avctx->sample_rate); pctx->pe.min = 8.0f * AAC_BLOCK_SIZE_LONG * bandwidth / (ctx->avctx->sample_rate * 2.0f); pctx->pe.max = 12.0f * AAC_BLOCK_SIZE_LONG * bandwidth / (ctx->avctx->sample_rate * 2.0f); ctx->bitres.size = 6144 - pctx->frame_bits; ctx->bitres.size -= ctx->bitres.size % 8; pctx->fill_level = ctx->bitres.size; minath = ath(3410 - 0.733 * ATH_ADD, ATH_ADD); for (j = 0; j < 2; j++) { AacPsyCoeffs *coeffs = pctx->psy_coef[j]; const uint8_t *band_sizes = ctx->bands[j]; float line_to_frequency = ctx->avctx->sample_rate / (j ? 256.f : 2048.0f); float avg_chan_bits = chan_bitrate * (j ? 128.0f : 1024.0f) / ctx->avctx->sample_rate; /* reference encoder uses 2.4% here instead of 60% like the spec says */ float bark_pe = 0.024f * PSY_3GPP_BITS_TO_PE(avg_chan_bits) / num_bark; float en_spread_low = j ? PSY_3GPP_EN_SPREAD_LOW_S : PSY_3GPP_EN_SPREAD_LOW_L; /* High energy spreading for long blocks <= 22kbps/channel and short blocks are the same. */ float en_spread_hi = (j || (chan_bitrate <= 22.0f)) ? PSY_3GPP_EN_SPREAD_HI_S : PSY_3GPP_EN_SPREAD_HI_L1; i = 0; prev = 0.0; for (g = 0; g < ctx->num_bands[j]; g++) { i += band_sizes[g]; bark = calc_bark((i-1) * line_to_frequency); coeffs[g].barks = (bark + prev) / 2.0; prev = bark; } for (g = 0; g < ctx->num_bands[j] - 1; g++) { AacPsyCoeffs *coeff = &coeffs[g]; float bark_width = coeffs[g+1].barks - coeffs->barks; coeff->spread_low[0] = pow(10.0, -bark_width * PSY_3GPP_THR_SPREAD_LOW); coeff->spread_hi [0] = pow(10.0, -bark_width * PSY_3GPP_THR_SPREAD_HI); coeff->spread_low[1] = pow(10.0, -bark_width * en_spread_low); coeff->spread_hi [1] = pow(10.0, -bark_width * en_spread_hi); pe_min = bark_pe * bark_width; minsnr = exp2(pe_min / band_sizes[g]) - 1.5f; coeff->min_snr = av_clipf(1.0f / minsnr, PSY_SNR_25DB, PSY_SNR_1DB); } start = 0; for (g = 0; g < ctx->num_bands[j]; g++) { minscale = ath(start * line_to_frequency, ATH_ADD); for (i = 1; i < band_sizes[g]; i++) minscale = FFMIN(minscale, ath((start + i) * line_to_frequency, ATH_ADD)); coeffs[g].ath = minscale - minath; start += band_sizes[g]; } } pctx->ch = av_mallocz_array(ctx->avctx->channels, sizeof(AacPsyChannel)); if (!pctx->ch) { av_freep(&ctx->model_priv_data); return AVERROR(ENOMEM); } lame_window_init(pctx, ctx->avctx); return 0; }


static av_cold int nvenc_encode_init(AVCodecContext *avctx) { NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS encode_session_params = { 0 }; NV_ENC_PRESET_CONFIG preset_config = { 0 }; CUcontext cu_context_curr; CUresult cu_res; GUID encoder_preset = NV_ENC_PRESET_HQ_GUID; GUID codec; NVENCSTATUS nv_status = NV_ENC_SUCCESS; AVCPBProperties *cpb_props; int surfaceCount = 0; int i, num_mbs; int isLL = 0; int lossless = 0; int res = 0; int dw, dh; int qp_inter_p; NvencContext *ctx = avctx->priv_data; NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs; NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs; if (!nvenc_dyload_nvenc(avctx)) return AVERROR_EXTERNAL; ctx->last_dts = AV_NOPTS_VALUE; ctx->encode_config.version = NV_ENC_CONFIG_VER; ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER; preset_config.version = NV_ENC_PRESET_CONFIG_VER; preset_config.presetCfg.version = NV_ENC_CONFIG_VER; encode_session_params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER; encode_session_params.apiVersion = NVENCAPI_VERSION; if (ctx->gpu >= dl_fn->nvenc_device_count) { av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->gpu, dl_fn->nvenc_device_count); res = AVERROR(EINVAL); goto error; } ctx->cu_context = NULL; cu_res = dl_fn->cu_ctx_create(&ctx->cu_context, 4, dl_fn->nvenc_devices[ctx->gpu]); // CU_CTX_SCHED_BLOCKING_SYNC=4, avoid CPU spins if (cu_res != CUDA_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "Failed creating CUDA context for NVENC: 0x%x\n", (int)cu_res); res = AVERROR_EXTERNAL; goto error; } cu_res = dl_fn->cu_ctx_pop_current(&cu_context_curr); if (cu_res != CUDA_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "Failed popping CUDA context: 0x%x\n", (int)cu_res); res = AVERROR_EXTERNAL; goto error; } encode_session_params.device = ctx->cu_context; encode_session_params.deviceType = NV_ENC_DEVICE_TYPE_CUDA; nv_status = p_nvenc->nvEncOpenEncodeSessionEx(&encode_session_params, &ctx->nvencoder); if (nv_status != NV_ENC_SUCCESS) { ctx->nvencoder = NULL; av_log(avctx, AV_LOG_FATAL, "OpenEncodeSessionEx failed: 0x%x\n", (int)nv_status); res = AVERROR_EXTERNAL; goto error; } if (ctx->preset) { if (!strcmp(ctx->preset, "slow")) { encoder_preset = NV_ENC_PRESET_HQ_GUID; ctx->twopass = 1; } else if (!strcmp(ctx->preset, "medium")) { encoder_preset = NV_ENC_PRESET_HQ_GUID; ctx->twopass = 0; } else if (!strcmp(ctx->preset, "fast")) { encoder_preset = NV_ENC_PRESET_HP_GUID; ctx->twopass = 0; } else if (!strcmp(ctx->preset, "hq")) { encoder_preset = NV_ENC_PRESET_HQ_GUID; } else if (!strcmp(ctx->preset, "hp")) { encoder_preset = NV_ENC_PRESET_HP_GUID; } else if (!strcmp(ctx->preset, "bd")) { encoder_preset = NV_ENC_PRESET_BD_GUID; } else if (!strcmp(ctx->preset, "ll")) { encoder_preset = NV_ENC_PRESET_LOW_LATENCY_DEFAULT_GUID; isLL = 1; } else if (!strcmp(ctx->preset, "llhp")) { encoder_preset = NV_ENC_PRESET_LOW_LATENCY_HP_GUID; isLL = 1; } else if (!strcmp(ctx->preset, "llhq")) { encoder_preset = NV_ENC_PRESET_LOW_LATENCY_HQ_GUID; isLL = 1; } else if (!strcmp(ctx->preset, "lossless")) { encoder_preset = NV_ENC_PRESET_LOSSLESS_DEFAULT_GUID; lossless = 1; } else if (!strcmp(ctx->preset, "losslesshp")) { encoder_preset = NV_ENC_PRESET_LOSSLESS_HP_GUID; lossless = 1; } else if (!strcmp(ctx->preset, "default")) { encoder_preset = NV_ENC_PRESET_DEFAULT_GUID; } else { av_log(avctx, AV_LOG_FATAL, "Preset \"%s\" is unknown! Supported presets: slow, medium, fast, hp, hq, bd, ll, llhp, llhq, lossless, losslesshp, default\n", ctx->preset); res = AVERROR(EINVAL); goto error; } } if (ctx->twopass < 0) { ctx->twopass = isLL; } switch (avctx->codec->id) { case AV_CODEC_ID_H264: codec = NV_ENC_CODEC_H264_GUID; break; case AV_CODEC_ID_H265: codec = NV_ENC_CODEC_HEVC_GUID; break; default: av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n"); res = AVERROR(EINVAL); goto error; } nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder, codec, encoder_preset, &preset_config); if (nv_status != NV_ENC_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "GetEncodePresetConfig failed: 0x%x\n", (int)nv_status); res = AVERROR_EXTERNAL; goto error; } ctx->init_encode_params.encodeGUID = codec; ctx->init_encode_params.encodeHeight = avctx->height; ctx->init_encode_params.encodeWidth = avctx->width; if (avctx->sample_aspect_ratio.num && avctx->sample_aspect_ratio.den && (avctx->sample_aspect_ratio.num != 1 || avctx->sample_aspect_ratio.num != 1)) { av_reduce(&dw, &dh, avctx->width * avctx->sample_aspect_ratio.num, avctx->height * avctx->sample_aspect_ratio.den, 1024 * 1024); ctx->init_encode_params.darHeight = dh; ctx->init_encode_params.darWidth = dw; } else { ctx->init_encode_params.darHeight = avctx->height; ctx->init_encode_params.darWidth = avctx->width; } // De-compensate for hardware, dubiously, trying to compensate for // playback at 704 pixel width. if (avctx->width == 720 && (avctx->height == 480 || avctx->height == 576)) { av_reduce(&dw, &dh, ctx->init_encode_params.darWidth * 44, ctx->init_encode_params.darHeight * 45, 1024 * 1024); ctx->init_encode_params.darHeight = dh; ctx->init_encode_params.darWidth = dw; } ctx->init_encode_params.frameRateNum = avctx->time_base.den; ctx->init_encode_params.frameRateDen = avctx->time_base.num * avctx->ticks_per_frame; num_mbs = ((avctx->width + 15) >> 4) * ((avctx->height + 15) >> 4); ctx->max_surface_count = (num_mbs >= 8160) ? 32 : 48; if (ctx->buffer_delay >= ctx->max_surface_count) ctx->buffer_delay = ctx->max_surface_count - 1; ctx->init_encode_params.enableEncodeAsync = 0; ctx->init_encode_params.enablePTD = 1; ctx->init_encode_params.presetGUID = encoder_preset; ctx->init_encode_params.encodeConfig = &ctx->encode_config; memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config)); ctx->encode_config.version = NV_ENC_CONFIG_VER; if (avctx->refs >= 0) { /* 0 means "let the hardware decide" */ switch (avctx->codec->id) { case AV_CODEC_ID_H264: ctx->encode_config.encodeCodecConfig.h264Config.maxNumRefFrames = avctx->refs; break; case AV_CODEC_ID_H265: ctx->encode_config.encodeCodecConfig.hevcConfig.maxNumRefFramesInDPB = avctx->refs; break; /* Earlier switch/case will return if unknown codec is passed. */ } } if (avctx->gop_size > 0) { if (avctx->max_b_frames >= 0) { /* 0 is intra-only, 1 is I/P only, 2 is one B Frame, 3 two B frames, and so on. */ ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1; } ctx->encode_config.gopLength = avctx->gop_size; switch (avctx->codec->id) { case AV_CODEC_ID_H264: ctx->encode_config.encodeCodecConfig.h264Config.idrPeriod = avctx->gop_size; break; case AV_CODEC_ID_H265: ctx->encode_config.encodeCodecConfig.hevcConfig.idrPeriod = avctx->gop_size; break; /* Earlier switch/case will return if unknown codec is passed. */ } } else if (avctx->gop_size == 0) { ctx->encode_config.frameIntervalP = 0; ctx->encode_config.gopLength = 1; switch (avctx->codec->id) { case AV_CODEC_ID_H264: ctx->encode_config.encodeCodecConfig.h264Config.idrPeriod = 1; break; case AV_CODEC_ID_H265: ctx->encode_config.encodeCodecConfig.hevcConfig.idrPeriod = 1; break; /* Earlier switch/case will return if unknown codec is passed. */ } } /* when there're b frames, set dts offset */ if (ctx->encode_config.frameIntervalP >= 2) ctx->last_dts = -2; if (avctx->bit_rate > 0) { ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate; } else if (ctx->encode_config.rcParams.averageBitRate > 0) { ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate; } if (avctx->rc_max_rate > 0) ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate; if (lossless) { if (avctx->codec->id == AV_CODEC_ID_H264) ctx->encode_config.encodeCodecConfig.h264Config.qpPrimeYZeroTransformBypassFlag = 1; ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_CONSTQP; ctx->encode_config.rcParams.constQP.qpInterB = 0; ctx->encode_config.rcParams.constQP.qpInterP = 0; ctx->encode_config.rcParams.constQP.qpIntra = 0; avctx->qmin = -1; avctx->qmax = -1; } else if (ctx->cbr) { if (!ctx->twopass) { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_CBR; } else { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_2_PASS_QUALITY; if (avctx->codec->id == AV_CODEC_ID_H264) { ctx->encode_config.encodeCodecConfig.h264Config.adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE; ctx->encode_config.encodeCodecConfig.h264Config.fmoMode = NV_ENC_H264_FMO_DISABLE; } } if (avctx->codec->id == AV_CODEC_ID_H264) { ctx->encode_config.encodeCodecConfig.h264Config.outputBufferingPeriodSEI = 1; ctx->encode_config.encodeCodecConfig.h264Config.outputPictureTimingSEI = 1; } else if(avctx->codec->id == AV_CODEC_ID_H265) { ctx->encode_config.encodeCodecConfig.hevcConfig.outputBufferingPeriodSEI = 1; ctx->encode_config.encodeCodecConfig.hevcConfig.outputPictureTimingSEI = 1; } } else if (avctx->global_quality > 0) { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_CONSTQP; ctx->encode_config.rcParams.constQP.qpInterB = avctx->global_quality; ctx->encode_config.rcParams.constQP.qpInterP = avctx->global_quality; ctx->encode_config.rcParams.constQP.qpIntra = avctx->global_quality; avctx->qmin = -1; avctx->qmax = -1; } else { if (avctx->qmin >= 0 && avctx->qmax >= 0) { ctx->encode_config.rcParams.enableMinQP = 1; ctx->encode_config.rcParams.enableMaxQP = 1; ctx->encode_config.rcParams.minQP.qpInterB = avctx->qmin; ctx->encode_config.rcParams.minQP.qpInterP = avctx->qmin; ctx->encode_config.rcParams.minQP.qpIntra = avctx->qmin; ctx->encode_config.rcParams.maxQP.qpInterB = avctx->qmax; ctx->encode_config.rcParams.maxQP.qpInterP = avctx->qmax; ctx->encode_config.rcParams.maxQP.qpIntra = avctx->qmax; qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin if (ctx->twopass) { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_2_PASS_VBR; if (avctx->codec->id == AV_CODEC_ID_H264) { ctx->encode_config.encodeCodecConfig.h264Config.adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE; ctx->encode_config.encodeCodecConfig.h264Config.fmoMode = NV_ENC_H264_FMO_DISABLE; } } else { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR_MINQP; } } else { qp_inter_p = 26; // default to 26 if (ctx->twopass) { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_2_PASS_VBR; } else { ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR; } } ctx->encode_config.rcParams.enableInitialRCQP = 1; ctx->encode_config.rcParams.initialRCQP.qpInterP = qp_inter_p; if(avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) { ctx->encode_config.rcParams.initialRCQP.qpIntra = av_clip( qp_inter_p * fabs(avctx->i_quant_factor) + avctx->i_quant_offset, 0, 51); ctx->encode_config.rcParams.initialRCQP.qpInterB = av_clip( qp_inter_p * fabs(avctx->b_quant_factor) + avctx->b_quant_offset, 0, 51); } else { ctx->encode_config.rcParams.initialRCQP.qpIntra = qp_inter_p; ctx->encode_config.rcParams.initialRCQP.qpInterB = qp_inter_p; } } if (avctx->rc_buffer_size > 0) { ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size; } else if (ctx->encode_config.rcParams.averageBitRate > 0) { ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate; } if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) { ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD; } else { ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME; } switch (avctx->codec->id) { case AV_CODEC_ID_H264: ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.colourMatrix = avctx->colorspace; ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.colourPrimaries = avctx->color_primaries; ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.transferCharacteristics = avctx->color_trc; ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG || avctx->pix_fmt == AV_PIX_FMT_YUVJ420P || avctx->pix_fmt == AV_PIX_FMT_YUVJ422P || avctx->pix_fmt == AV_PIX_FMT_YUVJ444P); ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.colourDescriptionPresentFlag = (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2); ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.videoSignalTypePresentFlag = (ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.colourDescriptionPresentFlag || ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.videoFormat != 5 || ctx->encode_config.encodeCodecConfig.h264Config.h264VUIParameters.videoFullRangeFlag != 0); ctx->encode_config.encodeCodecConfig.h264Config.sliceMode = 3; ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData = 1; ctx->encode_config.encodeCodecConfig.h264Config.disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0; ctx->encode_config.encodeCodecConfig.h264Config.repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1; ctx->encode_config.encodeCodecConfig.h264Config.outputAUD = 1; if (!ctx->profile && !lossless) { switch (avctx->profile) { case FF_PROFILE_H264_HIGH_444_PREDICTIVE: ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID; break; case FF_PROFILE_H264_BASELINE: ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID; break; case FF_PROFILE_H264_MAIN: ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID; break; case FF_PROFILE_H264_HIGH: case FF_PROFILE_UNKNOWN: ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID; break; default: av_log(avctx, AV_LOG_WARNING, "Unsupported profile requested, falling back to high\n"); ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID; break; } } else if(!lossless) { if (!strcmp(ctx->profile, "high")) { ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID; avctx->profile = FF_PROFILE_H264_HIGH; } else if (!strcmp(ctx->profile, "main")) { ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID; avctx->profile = FF_PROFILE_H264_MAIN; } else if (!strcmp(ctx->profile, "baseline")) { ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID; avctx->profile = FF_PROFILE_H264_BASELINE; } else if (!strcmp(ctx->profile, "high444p")) { ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID; avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE; } else { av_log(avctx, AV_LOG_FATAL, "Profile \"%s\" is unknown! Supported profiles: high, main, baseline\n", ctx->profile); res = AVERROR(EINVAL); goto error; } } // force setting profile as high444p if input is AV_PIX_FMT_YUV444P if (avctx->pix_fmt == AV_PIX_FMT_YUV444P) { ctx->encode_config.profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID; avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE; } ctx->encode_config.encodeCodecConfig.h264Config.chromaFormatIDC = avctx->profile == FF_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1; if (ctx->level) { res = input_string_to_uint32(avctx, nvenc_h264_level_pairs, ctx->level, &ctx->encode_config.encodeCodecConfig.h264Config.level); if (res) { av_log(avctx, AV_LOG_FATAL, "Level \"%s\" is unknown! Supported levels: auto, 1, 1b, 1.1, 1.2, 1.3, 2, 2.1, 2.2, 3, 3.1, 3.2, 4, 4.1, 4.2, 5, 5.1\n", ctx->level); goto error; } } else { ctx->encode_config.encodeCodecConfig.h264Config.level = NV_ENC_LEVEL_AUTOSELECT; } break; case AV_CODEC_ID_H265: ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.colourMatrix = avctx->colorspace; ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.colourPrimaries = avctx->color_primaries; ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.transferCharacteristics = avctx->color_trc; ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG || avctx->pix_fmt == AV_PIX_FMT_YUVJ420P || avctx->pix_fmt == AV_PIX_FMT_YUVJ422P || avctx->pix_fmt == AV_PIX_FMT_YUVJ444P); ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.colourDescriptionPresentFlag = (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2); ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.videoSignalTypePresentFlag = (ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.colourDescriptionPresentFlag || ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.videoFormat != 5 || ctx->encode_config.encodeCodecConfig.hevcConfig.hevcVUIParameters.videoFullRangeFlag != 0); ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode = 3; ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData = 1; ctx->encode_config.encodeCodecConfig.hevcConfig.disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0; ctx->encode_config.encodeCodecConfig.hevcConfig.repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1; ctx->encode_config.encodeCodecConfig.hevcConfig.outputAUD = 1; /* No other profile is supported in the current SDK version 5 */ ctx->encode_config.profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID; avctx->profile = FF_PROFILE_HEVC_MAIN; if (ctx->level) { res = input_string_to_uint32(avctx, nvenc_hevc_level_pairs, ctx->level, &ctx->encode_config.encodeCodecConfig.hevcConfig.level); if (res) { av_log(avctx, AV_LOG_FATAL, "Level \"%s\" is unknown! Supported levels: auto, 1, 2, 2.1, 3, 3.1, 4, 4.1, 5, 5.1, 5.2, 6, 6.1, 6.2\n", ctx->level); goto error; } } else { ctx->encode_config.encodeCodecConfig.hevcConfig.level = NV_ENC_LEVEL_AUTOSELECT; } if (ctx->tier) { if (!strcmp(ctx->tier, "main")) { ctx->encode_config.encodeCodecConfig.hevcConfig.tier = NV_ENC_TIER_HEVC_MAIN; } else if (!strcmp(ctx->tier, "high")) { ctx->encode_config.encodeCodecConfig.hevcConfig.tier = NV_ENC_TIER_HEVC_HIGH; } else { av_log(avctx, AV_LOG_FATAL, "Tier \"%s\" is unknown! Supported tiers: main, high\n", ctx->tier); res = AVERROR(EINVAL); goto error; } } break; /* Earlier switch/case will return if unknown codec is passed. */ } nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params); if (nv_status != NV_ENC_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "InitializeEncoder failed: 0x%x\n", (int)nv_status); res = AVERROR_EXTERNAL; goto error; } ctx->input_surfaces = av_malloc(ctx->max_surface_count * sizeof(*ctx->input_surfaces)); if (!ctx->input_surfaces) { res = AVERROR(ENOMEM); goto error; } ctx->output_surfaces = av_malloc(ctx->max_surface_count * sizeof(*ctx->output_surfaces)); if (!ctx->output_surfaces) { res = AVERROR(ENOMEM); goto error; } for (surfaceCount = 0; surfaceCount < ctx->max_surface_count; ++surfaceCount) { NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 }; NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 }; allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER; allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER; allocSurf.width = (avctx->width + 31) & ~31; allocSurf.height = (avctx->height + 31) & ~31; allocSurf.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED; switch (avctx->pix_fmt) { case AV_PIX_FMT_YUV420P: allocSurf.bufferFmt = NV_ENC_BUFFER_FORMAT_YV12_PL; break; case AV_PIX_FMT_NV12: allocSurf.bufferFmt = NV_ENC_BUFFER_FORMAT_NV12_PL; break; case AV_PIX_FMT_YUV444P: allocSurf.bufferFmt = NV_ENC_BUFFER_FORMAT_YUV444_PL; break; default: av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format\n"); res = AVERROR(EINVAL); goto error; } nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf); if (nv_status != NV_ENC_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "CreateInputBuffer failed\n"); res = AVERROR_EXTERNAL; goto error; } ctx->input_surfaces[surfaceCount].lockCount = 0; ctx->input_surfaces[surfaceCount].input_surface = allocSurf.inputBuffer; ctx->input_surfaces[surfaceCount].format = allocSurf.bufferFmt; ctx->input_surfaces[surfaceCount].width = allocSurf.width; ctx->input_surfaces[surfaceCount].height = allocSurf.height; /* 1MB is large enough to hold most output frames. NVENC increases this automaticaly if it's not enough. */ allocOut.size = 1024 * 1024; allocOut.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED; nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut); if (nv_status != NV_ENC_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "CreateBitstreamBuffer failed\n"); ctx->output_surfaces[surfaceCount++].output_surface = NULL; res = AVERROR_EXTERNAL; goto error; } ctx->output_surfaces[surfaceCount].output_surface = allocOut.bitstreamBuffer; ctx->output_surfaces[surfaceCount].size = allocOut.size; ctx->output_surfaces[surfaceCount].busy = 0; } if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) { uint32_t outSize = 0; char tmpHeader[256]; NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 }; payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER; payload.spsppsBuffer = tmpHeader; payload.inBufferSize = sizeof(tmpHeader); payload.outSPSPPSPayloadSize = &outSize; nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload); if (nv_status != NV_ENC_SUCCESS) { av_log(avctx, AV_LOG_FATAL, "GetSequenceParams failed\n"); goto error; } avctx->extradata_size = outSize; avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE); if (!avctx->extradata) { res = AVERROR(ENOMEM); goto error; } memcpy(avctx->extradata, tmpHeader, outSize); } if (ctx->encode_config.frameIntervalP > 1) avctx->has_b_frames = 2; if (ctx->encode_config.rcParams.averageBitRate > 0) avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate; cpb_props = ff_add_cpb_side_data(avctx); if (!cpb_props) return AVERROR(ENOMEM); cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate; cpb_props->avg_bitrate = avctx->bit_rate; cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize; return 0; error: for (i = 0; i < surfaceCount; ++i) { p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->input_surfaces[i].input_surface); if (ctx->output_surfaces[i].output_surface) p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->output_surfaces[i].output_surface); } if (ctx->nvencoder) p_nvenc->nvEncDestroyEncoder(ctx->nvencoder); if (ctx->cu_context) dl_fn->cu_ctx_destroy(ctx->cu_context); nvenc_unload_nvenc(avctx); ctx->nvencoder = NULL; ctx->cu_context = NULL; return res; }


static inline void RENAME(yuv422ptoyuy2)(const uint8_t *ysrc, const uint8_t *usrc, const uint8_t *vsrc, uint8_t *dst, unsigned int width, unsigned int height, int lumStride, int chromStride, int dstStride) { RENAME(yuvPlanartoyuy2)(ysrc, usrc, vsrc, dst, width, height, lumStride, chromStride, dstStride, 1); }


static void digic_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = digic_realize; }


vcard_emul_mirror_card(VReader *vreader) { /* * lookup certs using the C_FindObjects. The Stan Cert handle won't give * us the real certs until we log in. */ PK11GenericObject *firstObj, *thisObj; int cert_count; unsigned char **certs; int *cert_len; VCardKey **keys; PK11SlotInfo *slot; PRBool ret; slot = vcard_emul_reader_get_slot(vreader); if (slot == NULL) { return NULL; } firstObj = PK11_FindGenericObjects(slot, CKO_CERTIFICATE); if (firstObj == NULL) { return NULL; } /* count the certs */ cert_count = 0; for (thisObj = firstObj; thisObj; thisObj = PK11_GetNextGenericObject(thisObj)) { cert_count++; } if (cert_count == 0) { PK11_DestroyGenericObjects(firstObj); return NULL; } /* allocate the arrays */ ret = vcard_emul_alloc_arrays(&certs, &cert_len, &keys, cert_count); if (ret == PR_FALSE) { return NULL; } /* fill in the arrays */ cert_count = 0; for (thisObj = firstObj; thisObj; thisObj = PK11_GetNextGenericObject(thisObj)) { SECItem derCert; CERTCertificate *cert; SECStatus rv; rv = PK11_ReadRawAttribute(PK11_TypeGeneric, thisObj, CKA_VALUE, &derCert); if (rv != SECSuccess) { continue; } /* create floating temp cert. This gives us a cert structure even if * the token isn't logged in */ cert = CERT_NewTempCertificate(CERT_GetDefaultCertDB(), &derCert, NULL, PR_FALSE, PR_TRUE); SECITEM_FreeItem(&derCert, PR_FALSE); if (cert == NULL) { continue; } certs[cert_count] = cert->derCert.data; cert_len[cert_count] = cert->derCert.len; keys[cert_count] = vcard_emul_make_key(slot, cert); cert_count++; CERT_DestroyCertificate(cert); /* key obj still has a reference */ } /* now create the card */ return vcard_emul_make_card(vreader, certs, cert_len, keys, cert_count); }


static void gen_neon_trn_u8(TCGv t0, TCGv t1) { TCGv rd, tmp; rd = new_tmp(); tmp = new_tmp(); tcg_gen_shli_i32(rd, t0, 8); tcg_gen_andi_i32(rd, rd, 0xff00ff00); tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); tcg_gen_or_i32(rd, rd, tmp); tcg_gen_shri_i32(t1, t1, 8); tcg_gen_andi_i32(t1, t1, 0x00ff00ff); tcg_gen_andi_i32(tmp, t0, 0xff00ff00); tcg_gen_or_i32(t1, t1, tmp); tcg_gen_mov_i32(t0, rd); dead_tmp(tmp); dead_tmp(rd); }


static inline void RENAME(rgb15to32)(const uint8_t *src, uint8_t *dst, unsigned src_size) { const uint16_t *end; #ifdef HAVE_MMX const uint16_t *mm_end; #endif uint8_t *d = (uint8_t *)dst; const uint16_t *s = (const uint16_t *)src; end = s + src_size/2; #ifdef HAVE_MMX __asm __volatile(PREFETCH" %0"::"m"(*s):"memory"); __asm __volatile("pxor %%mm7,%%mm7\n\t":::"memory"); mm_end = end - 3; while(s < mm_end) { __asm __volatile( PREFETCH" 32%1\n\t" "movq %1, %%mm0\n\t" "movq %1, %%mm1\n\t" "movq %1, %%mm2\n\t" "pand %2, %%mm0\n\t" "pand %3, %%mm1\n\t" "pand %4, %%mm2\n\t" "psllq $3, %%mm0\n\t" "psrlq $2, %%mm1\n\t" "psrlq $7, %%mm2\n\t" "movq %%mm0, %%mm3\n\t" "movq %%mm1, %%mm4\n\t" "movq %%mm2, %%mm5\n\t" "punpcklwd %%mm7, %%mm0\n\t" "punpcklwd %%mm7, %%mm1\n\t" "punpcklwd %%mm7, %%mm2\n\t" "punpckhwd %%mm7, %%mm3\n\t" "punpckhwd %%mm7, %%mm4\n\t" "punpckhwd %%mm7, %%mm5\n\t" "psllq $8, %%mm1\n\t" "psllq $16, %%mm2\n\t" "por %%mm1, %%mm0\n\t" "por %%mm2, %%mm0\n\t" "psllq $8, %%mm4\n\t" "psllq $16, %%mm5\n\t" "por %%mm4, %%mm3\n\t" "por %%mm5, %%mm3\n\t" MOVNTQ" %%mm0, %0\n\t" MOVNTQ" %%mm3, 8%0\n\t" :"=m"(*d) :"m"(*s),"m"(mask15b),"m"(mask15g),"m"(mask15r) :"memory"); d += 16; s += 4; } __asm __volatile(SFENCE:::"memory"); __asm __volatile(EMMS:::"memory"); #endif while(s < end) { #if 0 //slightly slower on athlon int bgr= *s++; *((uint32_t*)d)++ = ((bgr&0x1F)<<3) + ((bgr&0x3E0)<<6) + ((bgr&0x7C00)<<9); #else //FIXME this is very likely wrong for bigendian (and the following converters too) register uint16_t bgr; bgr = *s++; #ifdef WORDS_BIGENDIAN *d++ = 0; *d++ = (bgr&0x1F)<<3; *d++ = (bgr&0x3E0)>>2; *d++ = (bgr&0x7C00)>>7; #else *d++ = (bgr&0x1F)<<3; *d++ = (bgr&0x3E0)>>2; *d++ = (bgr&0x7C00)>>7; *d++ = 0; #endif #endif } }


static int xio3130_upstream_initfn(PCIDevice *d) { PCIEPort *p = PCIE_PORT(d); int rc; Error *err = NULL; pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err); if (rc < 0) { assert(rc == -ENOTSUP); error_report_err(err); goto err_bridge; } rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); if (rc < 0) { goto err_bridge; } rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port); if (rc < 0) { goto err_msi; } pcie_cap_flr_init(d); pcie_cap_deverr_init(d); rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } return 0; err: pcie_cap_exit(d); err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); return rc; }


int qemu_register_machine(QEMUMachine *m) { TypeInfo ti = { .name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL), .parent = TYPE_MACHINE, .class_init = machine_class_init, .class_data = (void *)m, }; type_register(&ti); return 0; }


int64_t migrate_xbzrle_cache_size(void) { MigrationState *s; s = migrate_get_current(); return s->xbzrle_cache_size; }


static int line_out_init (HWVoiceOut *hw, struct audsettings *as) { SpiceVoiceOut *out = container_of (hw, SpiceVoiceOut, hw); struct audsettings settings; #if SPICE_INTERFACE_PLAYBACK_MAJOR > 1 || SPICE_INTERFACE_PLAYBACK_MINOR >= 3 settings.freq = spice_server_get_best_playback_rate(NULL); #else settings.freq = SPICE_INTERFACE_PLAYBACK_FREQ; #endif settings.nchannels = SPICE_INTERFACE_PLAYBACK_CHAN; settings.fmt = AUD_FMT_S16; settings.endianness = AUDIO_HOST_ENDIANNESS; audio_pcm_init_info (&hw->info, &settings); hw->samples = LINE_OUT_SAMPLES; out->active = 0; out->sin.base.sif = &playback_sif.base; qemu_spice_add_interface (&out->sin.base); #if SPICE_INTERFACE_PLAYBACK_MAJOR > 1 || SPICE_INTERFACE_PLAYBACK_MINOR >= 3 spice_server_set_playback_rate(&out->sin, settings.freq); #endif return 0; }


static int ipvideo_decode_block_opcode_0xD(IpvideoContext *s) { int y; unsigned char P[2]; /* 4-color block encoding: each 4x4 block is a different color */ CHECK_STREAM_PTR(4); for (y = 0; y < 8; y++) { if (!(y & 3)) { P[0] = *s->stream_ptr++; P[1] = *s->stream_ptr++; } memset(s->pixel_ptr, P[0], 4); memset(s->pixel_ptr + 4, P[1], 4); s->pixel_ptr += s->stride; } /* report success */ return 0; }


void socket_listen_cleanup(int fd, Error **errp) { SocketAddress *addr; addr = socket_local_address(fd, errp); if (addr->type == SOCKET_ADDRESS_TYPE_UNIX && addr->u.q_unix.path) { if (unlink(addr->u.q_unix.path) < 0 && errno != ENOENT) { error_setg_errno(errp, errno, "Failed to unlink socket %s", addr->u.q_unix.path); qapi_free_SocketAddress(addr);


int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) { int ret; sigset_t val; sigset_t *temp = NULL; CPUState *cpu = thread_cpu; TaskState *ts = (TaskState *)cpu->opaque; bool segv_was_blocked = ts->sigsegv_blocked; if (set) { bool has_sigsegv = sigismember(set, SIGSEGV); val = *set; temp = &val; sigdelset(temp, SIGSEGV); switch (how) { case SIG_BLOCK: if (has_sigsegv) { ts->sigsegv_blocked = true; } break; case SIG_UNBLOCK: if (has_sigsegv) { ts->sigsegv_blocked = false; } break; case SIG_SETMASK: ts->sigsegv_blocked = has_sigsegv; break; default: g_assert_not_reached(); } } ret = sigprocmask(how, temp, oldset); if (oldset && segv_was_blocked) { sigaddset(oldset, SIGSEGV); } return ret; }


static int process_work_frame(AVFilterContext *ctx) { FrameRateContext *s = ctx->priv; int64_t work_pts; int interpolate; int ret; if (!s->f1) return 0; if (!s->f0 && !s->flush) return 0; work_pts = s->start_pts + av_rescale_q(s->n, av_inv_q(s->dest_frame_rate), s->dest_time_base); if (work_pts >= s->pts1 && !s->flush) return 0; if (!s->f0) { s->work = av_frame_clone(s->f1); } else { if (work_pts >= s->pts1 + s->delta && s->flush) return 0; interpolate = av_rescale(work_pts - s->pts0, s->max, s->delta); ff_dlog(ctx, "process_work_frame() interpolate:%d/%d\n", interpolate, s->max); if (interpolate > s->interp_end) { s->work = av_frame_clone(s->f1); } else if (interpolate < s->interp_start) { s->work = av_frame_clone(s->f0); } else { ret = blend_frames(ctx, interpolate); if (ret < 0) return ret; if (ret == 0) s->work = av_frame_clone(interpolate > (s->max >> 1) ? s->f1 : s->f0); } } if (!s->work) return AVERROR(ENOMEM); s->work->pts = work_pts; s->n++; return 1; }


int ff_h2645_packet_split(H2645Packet *pkt, const uint8_t *buf, int length, void *logctx, int is_nalff, int nal_length_size, enum AVCodecID codec_id) { int consumed, ret = 0; const uint8_t *next_avc = buf + (is_nalff ? 0 : length); pkt->nb_nals = 0; while (length >= 4) { H2645NAL *nal; int extract_length = 0; int skip_trailing_zeros = 1; /* * Only parse an AVC1 length field if one is expected at the current * buffer position. There are unfortunately streams with multiple * NAL units covered by the length field. Those NAL units are delimited * by Annex B start code prefixes. ff_h2645_extract_rbsp() detects it * correctly and consumes only the first NAL unit. The additional NAL * units are handled here in the Annex B parsing code. */ if (buf == next_avc) { int i; for (i = 0; i < nal_length_size; i++) extract_length = (extract_length << 8) | buf[i]; if (extract_length > length) { av_log(logctx, AV_LOG_ERROR, "Invalid NAL unit size (%d > %d).\n", extract_length, length); return AVERROR_INVALIDDATA; } buf += nal_length_size; length -= nal_length_size; // keep track of the next AVC1 length field next_avc = buf + extract_length; } else { /* * expected to return immediately except for streams with mixed * NAL unit coding */ int buf_index = find_next_start_code(buf, next_avc); buf += buf_index; length -= buf_index; /* * break if an AVC1 length field is expected at the current buffer * position */ if (buf == next_avc) continue; if (length > 0) { extract_length = length; } else if (pkt->nb_nals == 0) { av_log(logctx, AV_LOG_ERROR, "No NAL unit found\n"); return AVERROR_INVALIDDATA; } else { break; } } if (pkt->nals_allocated < pkt->nb_nals + 1) { int new_size = pkt->nals_allocated + 1; H2645NAL *tmp = av_realloc_array(pkt->nals, new_size, sizeof(*tmp)); if (!tmp) return AVERROR(ENOMEM); pkt->nals = tmp; memset(pkt->nals + pkt->nals_allocated, 0, (new_size - pkt->nals_allocated) * sizeof(*tmp)); pkt->nals_allocated = new_size; } nal = &pkt->nals[pkt->nb_nals++]; consumed = ff_h2645_extract_rbsp(buf, extract_length, nal); if (consumed < 0) return consumed; /* see commit 3566042a0 */ if (consumed < length - 3 && buf[consumed] == 0x00 && buf[consumed + 1] == 0x00 && buf[consumed + 2] == 0x01 && buf[consumed + 3] == 0xE0) skip_trailing_zeros = 0; nal->size_bits = get_bit_length(nal, skip_trailing_zeros); ret = init_get_bits(&nal->gb, nal->data, nal->size_bits); if (ret < 0) return ret; if (codec_id == AV_CODEC_ID_HEVC) ret = hevc_parse_nal_header(nal, logctx); else ret = h264_parse_nal_header(nal, logctx); if (ret <= 0) { if (ret < 0) { av_log(logctx, AV_LOG_ERROR, "Invalid NAL unit %d, skipping.\n", nal->type); } pkt->nb_nals--; } buf += consumed; length -= consumed; } return 0; }


static void gen_check_interrupts(DisasContext *dc) { if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } }


static void put_buffer(QEMUFile *f, void *pv, size_t size) { uint8_t *v = pv; qemu_put_buffer(f, v, size); }


static void boston_lcd_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { BostonState *s = opaque; switch (size) { case 8: s->lcd_content[(addr + 7) & 0x7] = val >> 56; s->lcd_content[(addr + 6) & 0x7] = val >> 48; s->lcd_content[(addr + 5) & 0x7] = val >> 40; s->lcd_content[(addr + 4) & 0x7] = val >> 32; /* fall through */ case 4: s->lcd_content[(addr + 3) & 0x7] = val >> 24; s->lcd_content[(addr + 2) & 0x7] = val >> 16; /* fall through */ case 2: s->lcd_content[(addr + 1) & 0x7] = val >> 8; /* fall through */ case 1: s->lcd_content[(addr + 0) & 0x7] = val; break; } qemu_chr_fe_printf(&s->lcd_display, "\r%-8.8s", s->lcd_content); }


int qemu_loadvm_state(QEMUFile *f) { QLIST_HEAD(, LoadStateEntry) loadvm_handlers = QLIST_HEAD_INITIALIZER(loadvm_handlers); LoadStateEntry *le, *new_le; Error *local_err = NULL; uint8_t section_type; unsigned int v; int ret; int file_error_after_eof = -1; if (qemu_savevm_state_blocked(&local_err)) { error_report_err(local_err); return -EINVAL; } v = qemu_get_be32(f); if (v != QEMU_VM_FILE_MAGIC) { error_report("Not a migration stream"); return -EINVAL; } v = qemu_get_be32(f); if (v == QEMU_VM_FILE_VERSION_COMPAT) { error_report("SaveVM v2 format is obsolete and don't work anymore"); return -ENOTSUP; } if (v != QEMU_VM_FILE_VERSION) { error_report("Unsupported migration stream version"); return -ENOTSUP; } while ((section_type = qemu_get_byte(f)) != QEMU_VM_EOF) { uint32_t instance_id, version_id, section_id; SaveStateEntry *se; char idstr[257]; int len; trace_qemu_loadvm_state_section(section_type); switch (section_type) { case QEMU_VM_SECTION_START: case QEMU_VM_SECTION_FULL: /* Read section start */ section_id = qemu_get_be32(f); len = qemu_get_byte(f); qemu_get_buffer(f, (uint8_t *)idstr, len); idstr[len] = 0; instance_id = qemu_get_be32(f); version_id = qemu_get_be32(f); trace_qemu_loadvm_state_section_startfull(section_id, idstr, instance_id, version_id); /* Find savevm section */ se = find_se(idstr, instance_id); if (se == NULL) { error_report("Unknown savevm section or instance '%s' %d", idstr, instance_id); ret = -EINVAL; goto out; } /* Validate version */ if (version_id > se->version_id) { error_report("savevm: unsupported version %d for '%s' v%d", version_id, idstr, se->version_id); ret = -EINVAL; goto out; } /* Add entry */ le = g_malloc0(sizeof(*le)); le->se = se; le->section_id = section_id; le->version_id = version_id; QLIST_INSERT_HEAD(&loadvm_handlers, le, entry); ret = vmstate_load(f, le->se, le->version_id); if (ret < 0) { error_report("error while loading state for instance 0x%x of" " device '%s'", instance_id, idstr); goto out; } break; case QEMU_VM_SECTION_PART: case QEMU_VM_SECTION_END: section_id = qemu_get_be32(f); trace_qemu_loadvm_state_section_partend(section_id); QLIST_FOREACH(le, &loadvm_handlers, entry) { if (le->section_id == section_id) { break; } } if (le == NULL) { error_report("Unknown savevm section %d", section_id); ret = -EINVAL; goto out; } ret = vmstate_load(f, le->se, le->version_id); if (ret < 0) { error_report("error while loading state section id %d(%s)", section_id, le->se->idstr); goto out; } break; default: error_report("Unknown savevm section type %d", section_type); ret = -EINVAL; goto out; } } file_error_after_eof = qemu_file_get_error(f); /* * Try to read in the VMDESC section as well, so that dumping tools that * intercept our migration stream have the chance to see it. */ if (qemu_get_byte(f) == QEMU_VM_VMDESCRIPTION) { uint32_t size = qemu_get_be32(f); uint8_t *buf = g_malloc(0x1000); while (size > 0) { uint32_t read_chunk = MIN(size, 0x1000); qemu_get_buffer(f, buf, read_chunk); size -= read_chunk; } g_free(buf); } cpu_synchronize_all_post_init(); ret = 0; out: QLIST_FOREACH_SAFE(le, &loadvm_handlers, entry, new_le) { QLIST_REMOVE(le, entry); g_free(le); } if (ret == 0) { /* We may not have a VMDESC section, so ignore relative errors */ ret = file_error_after_eof; } return ret; }


int inet_connect(const char *str, bool block, Error **errp) { QemuOpts *opts; int sock = -1; opts = qemu_opts_create(&dummy_opts, NULL, 0); if (inet_parse(opts, str) == 0) { if (block) { qemu_opt_set(opts, "block", "on"); } sock = inet_connect_opts(opts, errp); } else { error_set(errp, QERR_SOCKET_CREATE_FAILED); } qemu_opts_del(opts); return sock; }


static void blkverify_verify_readv(BlkverifyAIOCB *acb) { ssize_t offset = qemu_iovec_compare(acb->qiov, &acb->raw_qiov); if (offset != -1) { blkverify_err(acb, "contents mismatch in sector %" PRId64, acb->sector_num + (int64_t)(offset / BDRV_SECTOR_SIZE)); } }


static void png_filter_row(DSPContext *dsp, uint8_t *dst, int filter_type, uint8_t *src, uint8_t *top, int size, int bpp) { int i; switch(filter_type) { case PNG_FILTER_VALUE_NONE: memcpy(dst, src, size); break; case PNG_FILTER_VALUE_SUB: dsp->diff_bytes(dst, src, src-bpp, size); memcpy(dst, src, bpp); break; case PNG_FILTER_VALUE_UP: dsp->diff_bytes(dst, src, top, size); break; case PNG_FILTER_VALUE_AVG: for(i = 0; i < bpp; i++) dst[i] = src[i] - (top[i] >> 1); for(; i < size; i++) dst[i] = src[i] - ((src[i-bpp] + top[i]) >> 1); break; case PNG_FILTER_VALUE_PAETH: for(i = 0; i < bpp; i++) dst[i] = src[i] - top[i]; sub_png_paeth_prediction(dst+i, src+i, top+i, size-i, bpp); break; } }


static void handle_9p_output(VirtIODevice *vdev, VirtQueue *vq) { V9fsVirtioState *v = (V9fsVirtioState *)vdev; V9fsState *s = &v->state; V9fsPDU *pdu; ssize_t len; while ((pdu = pdu_alloc(s))) { struct { uint32_t size_le; uint8_t id; uint16_t tag_le; } QEMU_PACKED out; VirtQueueElement *elem; elem = virtqueue_pop(vq, sizeof(VirtQueueElement)); if (!elem) { pdu_free(pdu); break; } BUG_ON(elem->out_num == 0 || elem->in_num == 0); QEMU_BUILD_BUG_ON(sizeof(out) != 7); v->elems[pdu->idx] = elem; len = iov_to_buf(elem->out_sg, elem->out_num, 0, &out, sizeof(out)); BUG_ON(len != sizeof(out)); pdu->size = le32_to_cpu(out.size_le); pdu->id = out.id; pdu->tag = le16_to_cpu(out.tag_le); qemu_co_queue_init(&pdu->complete); pdu_submit(pdu); } }


static void add_keysym(char *line, int keysym, int keycode, kbd_layout_t *k) { if (keysym < MAX_NORMAL_KEYCODE) { trace_keymap_add("normal", keysym, keycode, line); k->keysym2keycode[keysym] = keycode; } else { if (k->extra_count >= MAX_EXTRA_COUNT) { fprintf(stderr, "Warning: Could not assign keysym %s (0x%x)" " because of memory constraints.\n", line, keysym); } else { trace_keymap_add("extra", keysym, keycode, line); k->keysym2keycode_extra[k->extra_count]. keysym = keysym; k->keysym2keycode_extra[k->extra_count]. keycode = keycode; k->extra_count++; } } }


static int local_unlinkat(FsContext *ctx, V9fsPath *dir, const char *name, int flags) { int ret; V9fsString fullname; char buffer[PATH_MAX]; v9fs_string_init(&fullname); v9fs_string_sprintf(&fullname, "%s/%s", dir->data, name); if (ctx->export_flags & V9FS_SM_MAPPED_FILE) { if (flags == AT_REMOVEDIR) { /* * If directory remove .virtfs_metadata contained in the * directory */ snprintf(buffer, ARRAY_SIZE(buffer), "%s/%s/%s", ctx->fs_root, fullname.data, VIRTFS_META_DIR); ret = remove(buffer); if (ret < 0 && errno != ENOENT) { /* * We didn't had the .virtfs_metadata file. May be file created * in non-mapped mode ?. Ignore ENOENT. */ goto err_out; } } /* * Now remove the name from parent directory * .virtfs_metadata directory. */ ret = remove(local_mapped_attr_path(ctx, fullname.data, buffer)); if (ret < 0 && errno != ENOENT) { /* * We didn't had the .virtfs_metadata file. May be file created * in non-mapped mode ?. Ignore ENOENT. */ goto err_out; } } /* Remove the name finally */ ret = remove(rpath(ctx, fullname.data, buffer)); err_out: v9fs_string_free(&fullname); return ret; }


static int dnxhd_init_vlc(DNXHDEncContext *ctx) { int i, j, level, run; int max_level = 1<<(ctx->cid_table->bit_depth+2); FF_ALLOCZ_OR_GOTO(ctx->m.avctx, ctx->vlc_codes, max_level*4*sizeof(*ctx->vlc_codes), fail); FF_ALLOCZ_OR_GOTO(ctx->m.avctx, ctx->vlc_bits, max_level*4*sizeof(*ctx->vlc_bits) , fail); FF_ALLOCZ_OR_GOTO(ctx->m.avctx, ctx->run_codes, 63*2, fail); FF_ALLOCZ_OR_GOTO(ctx->m.avctx, ctx->run_bits, 63, fail); ctx->vlc_codes += max_level*2; ctx->vlc_bits += max_level*2; for (level = -max_level; level < max_level; level++) { for (run = 0; run < 2; run++) { int index = (level<<1)|run; int sign, offset = 0, alevel = level; MASK_ABS(sign, alevel); if (alevel > 64) { offset = (alevel-1)>>6; alevel -= offset<<6; } for (j = 0; j < 257; j++) { if (ctx->cid_table->ac_level[j] >> 1 == alevel && (!offset || (ctx->cid_table->ac_index_flag[j] && offset)) && (!run || (ctx->cid_table->ac_run_flag [j] && run))) { assert(!ctx->vlc_codes[index]); if (alevel) { ctx->vlc_codes[index] = (ctx->cid_table->ac_codes[j]<<1)|(sign&1); ctx->vlc_bits [index] = ctx->cid_table->ac_bits[j]+1; } else { ctx->vlc_codes[index] = ctx->cid_table->ac_codes[j]; ctx->vlc_bits [index] = ctx->cid_table->ac_bits [j]; } break; } } assert(!alevel || j < 257); if (offset) { ctx->vlc_codes[index] = (ctx->vlc_codes[index]<<ctx->cid_table->index_bits)|offset; ctx->vlc_bits [index]+= ctx->cid_table->index_bits; } } } for (i = 0; i < 62; i++) { int run = ctx->cid_table->run[i]; assert(run < 63); ctx->run_codes[run] = ctx->cid_table->run_codes[i]; ctx->run_bits [run] = ctx->cid_table->run_bits[i]; } return 0; fail: return -1; }


static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { uint32_t config_addr = rtas_ld(args, 0); uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); sPAPRPHBState *phb = NULL; PCIDevice *pdev = NULL; spapr_pci_msi *msi; /* Find sPAPRPHBState */ phb = find_phb(spapr, buid); if (phb) { pdev = find_dev(spapr, buid, config_addr); } if (!phb || !pdev) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); return; } /* Find device descriptor and start IRQ */ msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { trace_spapr_pci_msi("Failed to return vector", config_addr); rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } intr_src_num = msi->first_irq + ioa_intr_num; trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, intr_src_num); rtas_st(rets, 0, RTAS_OUT_SUCCESS); rtas_st(rets, 1, intr_src_num); rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ }


void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value, Error **errp) { CPUPPCState *env = &cpu->env; target_ulong htabsize = value & SDR_64_HTABSIZE; env->spr[SPR_SDR1] = value; if (htabsize > 28) { error_setg(errp, "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1", htabsize); htabsize = 28; } env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1; env->htab_base = value & SDR_64_HTABORG; }


static coroutine_fn int cow_co_write(BlockDriverState *bs, int64_t sector_num, const uint8_t *buf, int nb_sectors) { int ret; BDRVCowState *s = bs->opaque; qemu_co_mutex_lock(&s->lock); ret = cow_write(bs, sector_num, buf, nb_sectors); qemu_co_mutex_unlock(&s->lock); return ret; }


static void x86_cpu_reset(CPUState *s) { X86CPU *cpu = X86_CPU(s); X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); CPUX86State *env = &cpu->env; target_ulong cr4; uint64_t xcr0; int i; xcc->parent_reset(s); memset(env, 0, offsetof(CPUX86State, end_reset_fields)); tlb_flush(s, 1); env->old_exception = -1; /* init to reset state */ env->hflags2 |= HF2_GIF_MASK; cpu_x86_update_cr0(env, 0x60000010); env->a20_mask = ~0x0; env->smbase = 0x30000; env->idt.limit = 0xffff; env->gdt.limit = 0xffff; env->ldt.limit = 0xffff; env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); env->tr.limit = 0xffff; env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); env->eip = 0xfff0; env->regs[R_EDX] = env->cpuid_version; env->eflags = 0x2; /* FPU init */ for (i = 0; i < 8; i++) { env->fptags[i] = 1; } cpu_set_fpuc(env, 0x37f); env->mxcsr = 0x1f80; /* All units are in INIT state. */ env->xstate_bv = 0; env->pat = 0x0007040600070406ULL; env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); cr4 = 0; xcr0 = XSTATE_FP_MASK; #ifdef CONFIG_USER_ONLY /* Enable all the features for user-mode. */ if (env->features[FEAT_1_EDX] & CPUID_SSE) { xcr0 |= XSTATE_SSE_MASK; } for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; if ((env->features[esa->feature] & esa->bits) == esa->bits) { xcr0 |= 1ull << i; } } if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; } if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { cr4 |= CR4_FSGSBASE_MASK; } #endif env->xcr0 = xcr0; cpu_x86_update_cr4(env, cr4); /* * SDM 11.11.5 requires: * - IA32_MTRR_DEF_TYPE MSR.E = 0 * - IA32_MTRR_PHYSMASKn.V = 0 * All other bits are undefined. For simplification, zero it all. */ env->mtrr_deftype = 0; memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); s->halted = !cpu_is_bsp(cpu); if (kvm_enabled()) { kvm_arch_reset_vcpu(cpu); } #endif }


static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, const int *const_args) { tcg_out_cmp2(s, args, const_args); tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, args[5]); }


static int net_rx_ok(NetClientState *nc) { struct XenNetDev *netdev = qemu_get_nic_opaque(nc); RING_IDX rc, rp; if (netdev->xendev.be_state != XenbusStateConnected) { return 0; } rc = netdev->rx_ring.req_cons; rp = netdev->rx_ring.sring->req_prod; xen_rmb(); if (rc == rp || RING_REQUEST_CONS_OVERFLOW(&netdev->rx_ring, rc)) { xen_be_printf(&netdev->xendev, 2, "%s: no rx buffers (%d/%d)\n", __FUNCTION__, rc, rp); return 0; } return 1; }


static void page_flush_tb_1(int level, void **lp) { int i; if (*lp == NULL) { return; } if (level == 0) { PageDesc *pd = *lp; for (i = 0; i < L2_SIZE; ++i) { pd[i].first_tb = NULL; invalidate_page_bitmap(pd + i); } } else { void **pp = *lp; for (i = 0; i < L2_SIZE; ++i) { page_flush_tb_1(level - 1, pp + i); } } }


static void disas_sparc_insn(DisasContext * dc) { unsigned int insn, opc, rs1, rs2, rd; insn = ldl_code(dc->pc); opc = GET_FIELD(insn, 0, 1); rd = GET_FIELD(insn, 2, 6); switch (opc) { case 0: /* branches/sethi */ { unsigned int xop = GET_FIELD(insn, 7, 9); int32_t target; switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ { int cc; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 18); target <<= 2; cc = GET_FIELD_SP(insn, 20, 21); if (cc == 0) do_branch(dc, target, insn, 0); else if (cc == 2) do_branch(dc, target, insn, 1); else goto illegal_insn; goto jmp_insn; } case 0x3: /* V9 BPr */ { target = GET_FIELD_SP(insn, 0, 13) | (GET_FIELD_SP(insn, 20, 21) << 14); target = sign_extend(target, 16); target <<= 2; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); do_branch_reg(dc, target, insn); goto jmp_insn; } case 0x5: /* V9 FBPcc */ { int cc = GET_FIELD_SP(insn, 20, 21); if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 19); target <<= 2; do_fbranch(dc, target, insn, cc); goto jmp_insn; } #else case 0x7: /* CBN+x */ { goto ncp_insn; } #endif case 0x2: /* BN+x */ { target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_branch(dc, target, insn, 0); goto jmp_insn; } case 0x6: /* FBN+x */ { if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_fbranch(dc, target, insn, 0); goto jmp_insn; } case 0x4: /* SETHI */ #define OPTIM #if defined(OPTIM) if (rd) { // nop #endif uint32_t value = GET_FIELD(insn, 10, 31); gen_movl_imm_T0(value << 10); gen_movl_T0_reg(rd); #if defined(OPTIM) } #endif break; case 0x0: /* UNIMPL */ default: goto illegal_insn; } break; } break; case 1: /*CALL*/ { target_long target = GET_FIELDs(insn, 2, 31) << 2; #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T0_im(dc->pc); #endif gen_movl_T0_reg(15); target += dc->pc; gen_mov_pc_npc(dc); dc->npc = target; } goto jmp_insn; case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); if (xop == 0x3a) { /* generate trap */ int cond; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELD(insn, 25, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } cond = GET_FIELD(insn, 3, 6); if (cond == 0x8) { save_state(dc); gen_op_trap_T0(); } else if (cond != 0) { #ifdef TARGET_SPARC64 /* V9 icc/xcc */ int cc = GET_FIELD_SP(insn, 11, 12); flush_T2(dc); save_state(dc); if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else goto illegal_insn; #else flush_T2(dc); save_state(dc); gen_cond[0][cond](); #endif gen_op_trapcc_T0(); } gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; goto jmp_insn; } else if (xop == 0x28) { rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ #ifndef TARGET_SPARC64 case 0x01 ... 0x0e: /* undefined in the SPARCv8 manual, rdy on the microSPARC II */ case 0x0f: /* stbar in the SPARCv8 manual, rdy on the microSPARC II */ case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, rdy on the microSPARC II */ #endif gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); gen_movl_T0_reg(rd); break; #ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ gen_op_rdccr(); gen_movl_T0_reg(rd); break; case 0x3: /* V9 rdasi */ gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); gen_movl_T0_reg(rd); break; case 0x4: /* V9 rdtick */ gen_op_rdtick(); gen_movl_T0_reg(rd); break; case 0x5: /* V9 rdpc */ if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } gen_movl_T0_reg(rd); break; case 0x6: /* V9 rdfprs */ gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); gen_movl_T0_reg(rd); break; case 0xf: /* V9 membar */ break; /* no effect */ case 0x13: /* Graphics Status */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); gen_movl_T0_reg(rd); break; case 0x17: /* Tick compare */ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); gen_movl_T0_reg(rd); break; case 0x18: /* System tick */ gen_op_rdstick(); gen_movl_T0_reg(rd); break; case 0x19: /* System tick compare */ gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); gen_movl_T0_reg(rd); break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ case 0x14: /* Softint set, WO */ case 0x15: /* Softint clear, WO */ case 0x16: /* Softint write */ #endif default: goto illegal_insn; } #if !defined(CONFIG_USER_ONLY) } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ #ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; gen_op_rdpsr(); #else if (!hypervisor(dc)) goto priv_insn; rs1 = GET_FIELD(insn, 13, 17); switch (rs1) { case 0: // hpstate // gen_op_rdhpstate(); break; case 1: // htstate // gen_op_rdhtstate(); break; case 3: // hintp gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); break; case 5: // htba gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); break; case 6: // hver gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); break; case 31: // hstick_cmpr gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); break; default: goto illegal_insn; } #endif gen_movl_T0_reg(rd); break; } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 rs1 = GET_FIELD(insn, 13, 17); switch (rs1) { case 0: // tpc gen_op_rdtpc(); break; case 1: // tnpc gen_op_rdtnpc(); break; case 2: // tstate gen_op_rdtstate(); break; case 3: // tt gen_op_rdtt(); break; case 4: // tick gen_op_rdtick(); break; case 5: // tba gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); break; case 6: // pstate gen_op_rdpstate(); break; case 7: // tl gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); break; case 8: // pil gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp gen_op_rdcwp(); break; case 10: // cansave gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); break; case 16: // UA2005 gl gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); break; case 26: // UA2005 strand status if (!hypervisor(dc)) goto priv_insn; gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); break; case 31: // ver gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); break; case 15: // fq default: goto illegal_insn; } #else gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); #endif gen_movl_T0_reg(rd); break; } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 gen_op_flushw(); #else if (!supervisor(dc)) goto priv_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); gen_movl_T0_reg(rd); #endif break; #endif } else if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_clear_ieee_excp_and_FTT(); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); switch (xop) { case 0x1: /* fmovs */ gen_op_load_fpr_FT0(rs2); gen_op_store_FT0_fpr(rd); break; case 0x5: /* fnegs */ gen_op_load_fpr_FT1(rs2); gen_op_fnegs(); gen_op_store_FT0_fpr(rd); break; case 0x9: /* fabss */ gen_op_load_fpr_FT1(rs2); gen_op_fabss(); gen_op_store_FT0_fpr(rd); break; case 0x29: /* fsqrts */ gen_op_load_fpr_FT1(rs2); gen_op_fsqrts(); gen_op_store_FT0_fpr(rd); break; case 0x2a: /* fsqrtd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsqrtd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x2b: /* fsqrtq */ goto nfpu_insn; case 0x41: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fadds(); gen_op_store_FT0_fpr(rd); break; case 0x42: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_faddd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x43: /* faddq */ goto nfpu_insn; case 0x45: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsubs(); gen_op_store_FT0_fpr(rd); break; case 0x46: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsubd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x47: /* fsubq */ goto nfpu_insn; case 0x49: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fmuls(); gen_op_store_FT0_fpr(rd); break; case 0x4a: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fmuld(); gen_op_store_DT0_fpr(rd); break; case 0x4b: /* fmulq */ goto nfpu_insn; case 0x4d: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fdivs(); gen_op_store_FT0_fpr(rd); break; case 0x4e: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdivd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4f: /* fdivq */ goto nfpu_insn; case 0x69: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsmuld(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6e: /* fdmulq */ goto nfpu_insn; case 0xc4: gen_op_load_fpr_FT1(rs2); gen_op_fitos(); gen_op_store_FT0_fpr(rd); break; case 0xc6: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtos(); gen_op_store_FT0_fpr(rd); break; case 0xc7: /* fqtos */ goto nfpu_insn; case 0xc8: gen_op_load_fpr_FT1(rs2); gen_op_fitod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xc9: gen_op_load_fpr_FT1(rs2); gen_op_fstod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcb: /* fqtod */ goto nfpu_insn; case 0xcc: /* fitoq */ goto nfpu_insn; case 0xcd: /* fstoq */ goto nfpu_insn; case 0xce: /* fdtoq */ goto nfpu_insn; case 0xd1: gen_op_load_fpr_FT1(rs2); gen_op_fstoi(); gen_op_store_FT0_fpr(rd); break; case 0xd2: gen_op_load_fpr_DT1(rs2); gen_op_fdtoi(); gen_op_store_FT0_fpr(rd); break; case 0xd3: /* fqtoi */ goto nfpu_insn; #ifdef TARGET_SPARC64 case 0x2: /* V9 fmovd */ gen_op_load_fpr_DT0(DFPREG(rs2)); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6: /* V9 fnegd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fnegd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xa: /* V9 fabsd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fabsd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x81: /* V9 fstox */ gen_op_load_fpr_FT1(rs2); gen_op_fstox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x82: /* V9 fdtox */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x84: /* V9 fxtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtos(); gen_op_store_FT0_fpr(rd); break; case 0x88: /* V9 fxtod */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x3: /* V9 fmovq */ case 0x7: /* V9 fnegq */ case 0xb: /* V9 fabsq */ case 0x83: /* V9 fqtox */ case 0x8c: /* V9 fxtoq */ goto nfpu_insn; #endif default: goto illegal_insn; } } else if (xop == 0x35) { /* FPU Operations */ #ifdef TARGET_SPARC64 int cond; #endif if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_clear_ieee_excp_and_FTT(); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); #ifdef TARGET_SPARC64 if ((xop & 0x11f) == 0x005) { // V9 fmovsr cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); flush_T2(dc); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_DT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr goto nfpu_insn; } #endif switch (xop) { #ifdef TARGET_SPARC64 case 0x001: /* V9 fmovscc %fcc0 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x002: /* V9 fmovdcc %fcc0 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x003: /* V9 fmovqcc %fcc0 */ goto nfpu_insn; case 0x041: /* V9 fmovscc %fcc1 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x042: /* V9 fmovdcc %fcc1 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x043: /* V9 fmovqcc %fcc1 */ goto nfpu_insn; case 0x081: /* V9 fmovscc %fcc2 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x082: /* V9 fmovdcc %fcc2 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x083: /* V9 fmovqcc %fcc2 */ goto nfpu_insn; case 0x0c1: /* V9 fmovscc %fcc3 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x0c2: /* V9 fmovdcc %fcc3 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x0c3: /* V9 fmovqcc %fcc3 */ goto nfpu_insn; case 0x101: /* V9 fmovscc %icc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x102: /* V9 fmovdcc %icc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x103: /* V9 fmovqcc %icc */ goto nfpu_insn; case 0x181: /* V9 fmovscc %xcc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x182: /* V9 fmovdcc %xcc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x183: /* V9 fmovqcc %xcc */ goto nfpu_insn; #endif case 0x51: /* V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmps[rd & 3](); #else gen_op_fcmps(); #endif break; case 0x52: /* V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmpd[rd & 3](); #else gen_op_fcmpd(); #endif break; case 0x53: /* fcmpq */ goto nfpu_insn; case 0x55: /* fcmpes, V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmpes[rd & 3](); #else gen_op_fcmpes(); #endif break; case 0x56: /* fcmped, V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmped[rd & 3](); #else gen_op_fcmped(); #endif break; case 0x57: /* fcmpeq */ goto nfpu_insn; default: goto illegal_insn; } #if defined(OPTIM) } else if (xop == 0x2) { // clr/mov shortcut rs1 = GET_FIELD(insn, 13, 17); if (rs1 == 0) { // or %g0, x, y -> mov T1, x; mov y, T1 if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } gen_movl_T1_reg(rd); } else { gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ // or x, #0, y -> mov T1, x; mov y, T1 rs2 = GET_FIELDs(insn, 19, 31); if (rs2 != 0) { gen_movl_simm_T1(rs2); gen_op_or_T1_T0(); } } else { /* register */ // or x, %g0, y -> mov T1, x; mov y, T1 rs2 = GET_FIELD(insn, 27, 31); if (rs2 != 0) { gen_movl_reg_T1(rs2); gen_op_or_T1_T0(); } } gen_movl_T0_reg(rd); } #endif #ifdef TARGET_SPARC64 } else if (xop == 0x25) { /* sll, V9 sllx */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_sllx(); else gen_op_sll(); gen_movl_T0_reg(rd); } else if (xop == 0x26) { /* srl, V9 srlx */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srlx(); else gen_op_srl(); gen_movl_T0_reg(rd); } else if (xop == 0x27) { /* sra, V9 srax */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srax(); else gen_op_sra(); gen_movl_T0_reg(rd); #endif } else if (xop < 0x36) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (xop < 0x20) { switch (xop & ~0x10) { case 0x0: if (xop & 0x10) gen_op_add_T1_T0_cc(); else gen_op_add_T1_T0(); break; case 0x1: gen_op_and_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x2: gen_op_or_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x3: gen_op_xor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x4: if (xop & 0x10) gen_op_sub_T1_T0_cc(); else gen_op_sub_T1_T0(); break; case 0x5: gen_op_andn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x6: gen_op_orn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x7: gen_op_xnor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x8: if (xop & 0x10) gen_op_addx_T1_T0_cc(); else gen_op_addx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0x9: /* V9 mulx */ gen_op_mulx_T1_T0(); break; #endif case 0xa: gen_op_umul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xb: gen_op_smul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xc: if (xop & 0x10) gen_op_subx_T1_T0_cc(); else gen_op_subx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_op_udivx_T1_T0(); break; #endif case 0xe: gen_op_udiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; case 0xf: gen_op_sdiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; default: goto illegal_insn; } gen_movl_T0_reg(rd); } else { switch (xop) { case 0x20: /* taddcc */ gen_op_tadd_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x21: /* tsubcc */ gen_op_tsub_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x22: /* taddcctv */ save_state(dc); gen_op_tadd_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x23: /* tsubcctv */ save_state(dc); gen_op_tsub_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x24: /* mulscc */ gen_op_mulscc_T1_T0(); gen_movl_T0_reg(rd); break; #ifndef TARGET_SPARC64 case 0x25: /* sll */ gen_op_sll(); gen_movl_T0_reg(rd); break; case 0x26: /* srl */ gen_op_srl(); gen_movl_T0_reg(rd); break; case 0x27: /* sra */ gen_op_sra(); gen_movl_T0_reg(rd); break; #endif case 0x30: { switch(rd) { case 0: /* wry */ gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0f: /* undefined in the SPARCv8 manual, nop on the microSPARC II */ case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */ break; #else case 0x2: /* V9 wrccr */ gen_op_xor_T1_T0(); gen_op_wrccr(); break; case 0x3: /* V9 wrasi */ gen_op_xor_T1_T0(); gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); break; case 0x6: /* V9 wrfprs */ gen_op_xor_T1_T0(); gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; break; case 0xf: /* V9 sir, nop if user */ #if !defined(CONFIG_USER_ONLY) if (supervisor(dc)) gen_op_sir(); #endif break; case 0x13: /* Graphics Status */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) goto illegal_insn; #endif gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); gen_op_wrtick_cmpr(); break; case 0x18: /* System tick */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) goto illegal_insn; #endif gen_op_xor_T1_T0(); gen_op_wrstick(); break; case 0x19: /* System tick compare */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) goto illegal_insn; #endif gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); gen_op_wrstick_cmpr(); break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ case 0x14: /* Softint set */ case 0x15: /* Softint clear */ case 0x16: /* Softint write */ #endif default: goto illegal_insn; } } break; #if !defined(CONFIG_USER_ONLY) case 0x31: /* wrpsr, V9 saved, restored */ { if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 switch (rd) { case 0: gen_op_saved(); break; case 1: gen_op_restored(); break; case 2: /* UA2005 allclean */ case 3: /* UA2005 otherw */ case 4: /* UA2005 normalw */ case 5: /* UA2005 invalw */ // XXX default: goto illegal_insn; } #else gen_op_xor_T1_T0(); gen_op_wrpsr(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; #endif } break; case 0x32: /* wrwim, V9 wrpr */ { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); #ifdef TARGET_SPARC64 switch (rd) { case 0: // tpc gen_op_wrtpc(); break; case 1: // tnpc gen_op_wrtnpc(); break; case 2: // tstate gen_op_wrtstate(); break; case 3: // tt gen_op_wrtt(); break; case 4: // tick gen_op_wrtick(); break; case 5: // tba gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); break; case 6: // pstate gen_op_wrpstate(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; break; case 7: // tl gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); break; case 8: // pil gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp gen_op_wrcwp(); break; case 10: // cansave gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); break; case 16: // UA2005 gl gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); break; case 26: // UA2005 strand status if (!hypervisor(dc)) goto priv_insn; gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); break; default: goto illegal_insn; } #else gen_op_wrwim(); #endif } break; case 0x33: /* wrtbr, UA2005 wrhpr */ { #ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); #else if (!hypervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); switch (rd) { case 0: // hpstate // XXX gen_op_wrhpstate(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; break; case 1: // htstate // XXX gen_op_wrhtstate(); break; case 3: // hintp gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); break; case 5: // htba gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); break; case 31: // hstick_cmpr gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); gen_op_wrhstick_cmpr(); break; case 6: // hver readonly default: goto illegal_insn; } #endif } break; #endif #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ { int cc = GET_FIELD_SP(insn, 11, 12); int cond = GET_FIELD_SP(insn, 14, 17); if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 10); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); flush_T2(dc); if (insn & (1 << 18)) { if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else goto illegal_insn; } else { gen_fcond[cc][cond](); } gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } case 0x2d: /* V9 sdivx */ gen_op_sdivx_T1_T0(); gen_movl_T0_reg(rd); break; case 0x2e: /* V9 popc */ { if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 12); gen_movl_simm_T1(rs2); // XXX optimize: popc(constant) } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_op_popc(); gen_movl_T0_reg(rd); } case 0x2f: /* V9 movr */ { int cond = GET_FIELD_SP(insn, 10, 12); rs1 = GET_FIELD(insn, 13, 17); flush_T2(dc); gen_movl_reg_T0(rs1); gen_cond_reg(cond); if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 9); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } #endif default: goto illegal_insn; } } } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ #ifdef TARGET_SPARC64 int opf = GET_FIELD_SP(insn, 5, 13); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (opf) { case 0x000: /* VIS I edge8cc */ case 0x001: /* VIS II edge8n */ case 0x002: /* VIS I edge8lcc */ case 0x003: /* VIS II edge8ln */ case 0x004: /* VIS I edge16cc */ case 0x005: /* VIS II edge16n */ case 0x006: /* VIS I edge16lcc */ case 0x007: /* VIS II edge16ln */ case 0x008: /* VIS I edge32cc */ case 0x009: /* VIS II edge32n */ case 0x00a: /* VIS I edge32lcc */ case 0x00b: /* VIS II edge32ln */ // XXX goto illegal_insn; case 0x010: /* VIS I array8 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_array8(); gen_movl_T0_reg(rd); break; case 0x012: /* VIS I array16 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_array16(); gen_movl_T0_reg(rd); break; case 0x014: /* VIS I array32 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_array32(); gen_movl_T0_reg(rd); break; case 0x018: /* VIS I alignaddr */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_alignaddr(); gen_movl_T0_reg(rd); break; case 0x019: /* VIS II bmask */ case 0x01a: /* VIS I alignaddrl */ // XXX goto illegal_insn; case 0x020: /* VIS I fcmple16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmple16(); gen_op_store_DT0_fpr(rd); break; case 0x022: /* VIS I fcmpne16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpne16(); gen_op_store_DT0_fpr(rd); break; case 0x024: /* VIS I fcmple32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmple32(); gen_op_store_DT0_fpr(rd); break; case 0x026: /* VIS I fcmpne32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpne32(); gen_op_store_DT0_fpr(rd); break; case 0x028: /* VIS I fcmpgt16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpgt16(); gen_op_store_DT0_fpr(rd); break; case 0x02a: /* VIS I fcmpeq16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpeq16(); gen_op_store_DT0_fpr(rd); break; case 0x02c: /* VIS I fcmpgt32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpgt32(); gen_op_store_DT0_fpr(rd); break; case 0x02e: /* VIS I fcmpeq32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fcmpeq32(); gen_op_store_DT0_fpr(rd); break; case 0x031: /* VIS I fmul8x16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmul8x16(); gen_op_store_DT0_fpr(rd); break; case 0x033: /* VIS I fmul8x16au */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmul8x16au(); gen_op_store_DT0_fpr(rd); break; case 0x035: /* VIS I fmul8x16al */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmul8x16al(); gen_op_store_DT0_fpr(rd); break; case 0x036: /* VIS I fmul8sux16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmul8sux16(); gen_op_store_DT0_fpr(rd); break; case 0x037: /* VIS I fmul8ulx16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmul8ulx16(); gen_op_store_DT0_fpr(rd); break; case 0x038: /* VIS I fmuld8sux16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmuld8sux16(); gen_op_store_DT0_fpr(rd); break; case 0x039: /* VIS I fmuld8ulx16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fmuld8ulx16(); gen_op_store_DT0_fpr(rd); break; case 0x03a: /* VIS I fpack32 */ case 0x03b: /* VIS I fpack16 */ case 0x03d: /* VIS I fpackfix */ case 0x03e: /* VIS I pdist */ // XXX goto illegal_insn; case 0x048: /* VIS I faligndata */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_faligndata(); gen_op_store_DT0_fpr(rd); break; case 0x04b: /* VIS I fpmerge */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fpmerge(); gen_op_store_DT0_fpr(rd); break; case 0x04c: /* VIS II bshuffle */ // XXX goto illegal_insn; case 0x04d: /* VIS I fexpand */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fexpand(); gen_op_store_DT0_fpr(rd); break; case 0x050: /* VIS I fpadd16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fpadd16(); gen_op_store_DT0_fpr(rd); break; case 0x051: /* VIS I fpadd16s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fpadd16s(); gen_op_store_FT0_fpr(rd); break; case 0x052: /* VIS I fpadd32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fpadd32(); gen_op_store_DT0_fpr(rd); break; case 0x053: /* VIS I fpadd32s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fpadd32s(); gen_op_store_FT0_fpr(rd); break; case 0x054: /* VIS I fpsub16 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fpsub16(); gen_op_store_DT0_fpr(rd); break; case 0x055: /* VIS I fpsub16s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fpsub16s(); gen_op_store_FT0_fpr(rd); break; case 0x056: /* VIS I fpsub32 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fpadd32(); gen_op_store_DT0_fpr(rd); break; case 0x057: /* VIS I fpsub32s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fpsub32s(); gen_op_store_FT0_fpr(rd); break; case 0x060: /* VIS I fzero */ gen_op_movl_DT0_0(); gen_op_store_DT0_fpr(rd); break; case 0x061: /* VIS I fzeros */ gen_op_movl_FT0_0(); gen_op_store_FT0_fpr(rd); break; case 0x062: /* VIS I fnor */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fnor(); gen_op_store_DT0_fpr(rd); break; case 0x063: /* VIS I fnors */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fnors(); gen_op_store_FT0_fpr(rd); break; case 0x064: /* VIS I fandnot2 */ gen_op_load_fpr_DT1(rs1); gen_op_load_fpr_DT0(rs2); gen_op_fandnot(); gen_op_store_DT0_fpr(rd); break; case 0x065: /* VIS I fandnot2s */ gen_op_load_fpr_FT1(rs1); gen_op_load_fpr_FT0(rs2); gen_op_fandnots(); gen_op_store_FT0_fpr(rd); break; case 0x066: /* VIS I fnot2 */ gen_op_load_fpr_DT1(rs2); gen_op_fnot(); gen_op_store_DT0_fpr(rd); break; case 0x067: /* VIS I fnot2s */ gen_op_load_fpr_FT1(rs2); gen_op_fnot(); gen_op_store_FT0_fpr(rd); break; case 0x068: /* VIS I fandnot1 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fandnot(); gen_op_store_DT0_fpr(rd); break; case 0x069: /* VIS I fandnot1s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fandnots(); gen_op_store_FT0_fpr(rd); break; case 0x06a: /* VIS I fnot1 */ gen_op_load_fpr_DT1(rs1); gen_op_fnot(); gen_op_store_DT0_fpr(rd); break; case 0x06b: /* VIS I fnot1s */ gen_op_load_fpr_FT1(rs1); gen_op_fnot(); gen_op_store_FT0_fpr(rd); break; case 0x06c: /* VIS I fxor */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fxor(); gen_op_store_DT0_fpr(rd); break; case 0x06d: /* VIS I fxors */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fxors(); gen_op_store_FT0_fpr(rd); break; case 0x06e: /* VIS I fnand */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fnand(); gen_op_store_DT0_fpr(rd); break; case 0x06f: /* VIS I fnands */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fnands(); gen_op_store_FT0_fpr(rd); break; case 0x070: /* VIS I fand */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fand(); gen_op_store_DT0_fpr(rd); break; case 0x071: /* VIS I fands */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fands(); gen_op_store_FT0_fpr(rd); break; case 0x072: /* VIS I fxnor */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fxnor(); gen_op_store_DT0_fpr(rd); break; case 0x073: /* VIS I fxnors */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fxnors(); gen_op_store_FT0_fpr(rd); break; case 0x074: /* VIS I fsrc1 */ gen_op_load_fpr_DT0(rs1); gen_op_store_DT0_fpr(rd); break; case 0x075: /* VIS I fsrc1s */ gen_op_load_fpr_FT0(rs1); gen_op_store_FT0_fpr(rd); break; case 0x076: /* VIS I fornot2 */ gen_op_load_fpr_DT1(rs1); gen_op_load_fpr_DT0(rs2); gen_op_fornot(); gen_op_store_DT0_fpr(rd); break; case 0x077: /* VIS I fornot2s */ gen_op_load_fpr_FT1(rs1); gen_op_load_fpr_FT0(rs2); gen_op_fornots(); gen_op_store_FT0_fpr(rd); break; case 0x078: /* VIS I fsrc2 */ gen_op_load_fpr_DT0(rs2); gen_op_store_DT0_fpr(rd); break; case 0x079: /* VIS I fsrc2s */ gen_op_load_fpr_FT0(rs2); gen_op_store_FT0_fpr(rd); break; case 0x07a: /* VIS I fornot1 */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_fornot(); gen_op_store_DT0_fpr(rd); break; case 0x07b: /* VIS I fornot1s */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fornots(); gen_op_store_FT0_fpr(rd); break; case 0x07c: /* VIS I for */ gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_for(); gen_op_store_DT0_fpr(rd); break; case 0x07d: /* VIS I fors */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fors(); gen_op_store_FT0_fpr(rd); break; case 0x07e: /* VIS I fone */ gen_op_movl_DT0_1(); gen_op_store_DT0_fpr(rd); break; case 0x07f: /* VIS I fones */ gen_op_movl_FT0_1(); gen_op_store_FT0_fpr(rd); break; case 0x080: /* VIS I shutdown */ case 0x081: /* VIS II siam */ // XXX goto illegal_insn; default: goto illegal_insn; } #else goto ncp_insn; #endif } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ #ifdef TARGET_SPARC64 goto illegal_insn; #else goto ncp_insn; #endif #ifdef TARGET_SPARC64 } else if (xop == 0x39) { /* V9 return */ rs1 = GET_FIELD(insn, 13, 17); save_state(dc); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } gen_op_restore(); gen_mov_pc_npc(dc); gen_op_check_align_T0_3(); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; goto jmp_insn; #endif } else { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } switch (xop) { case 0x38: /* jmpl */ { if (rd != 0) { #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T1_im(dc->pc); } else { gen_op_movq_T1_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T1_im(dc->pc); #endif gen_movl_T1_reg(rd); } gen_mov_pc_npc(dc); gen_op_check_align_T0_3(); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; } goto jmp_insn; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ { if (!supervisor(dc)) goto priv_insn; gen_mov_pc_npc(dc); gen_op_check_align_T0_3(); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; gen_op_rett(); } goto jmp_insn; #endif case 0x3b: /* flush */ gen_op_flush_T0(); break; case 0x3c: /* save */ save_state(dc); gen_op_save(); gen_movl_T0_reg(rd); break; case 0x3d: /* restore */ save_state(dc); gen_op_restore(); gen_movl_T0_reg(rd); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: /* V9 done/retry */ { switch (rd) { case 0: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_done(); goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_retry(); goto jmp_insn; default: goto illegal_insn; } } break; #endif default: goto illegal_insn; } } break; } break; case 3: /* load/store instructions */ { unsigned int xop = GET_FIELD(insn, 7, 12); rs1 = GET_FIELD(insn, 13, 17); save_state(dc); gen_movl_reg_T0(rs1); if (xop == 0x3c || xop == 0x3e) { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } else if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || (xop > 0x17 && xop <= 0x1d ) || (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { switch (xop) { case 0x0: /* load word */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif #ifndef TARGET_SPARC64 gen_op_ldst(ld); #else gen_op_ldst(lduw); #endif break; case 0x1: /* load unsigned byte */ gen_op_ldst(ldub); break; case 0x2: /* load unsigned halfword */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_op_ldst(lduh); break; case 0x3: /* load double word */ gen_op_check_align_T0_7(); if (rd & 1) goto illegal_insn; gen_op_ldst(ldd); gen_movl_T0_reg(rd + 1); break; case 0x9: /* load signed byte */ gen_op_ldst(ldsb); break; case 0xa: /* load signed halfword */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_op_ldst(ldsh); break; case 0xd: /* ldstub -- XXX: should be atomically */ gen_op_ldst(ldstub); break; case 0x0f: /* swap register with memory. Also atomically */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_movl_reg_T1(rd); gen_op_ldst(swap); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: /* load word alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #elif CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_ld_asi(insn, 4, 0); break; case 0x11: /* load unsigned byte alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif gen_ld_asi(insn, 1, 0); break; case 0x12: /* load unsigned halfword alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #elif CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_ld_asi(insn, 2, 0); break; case 0x13: /* load double word alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif if (rd & 1) goto illegal_insn; gen_op_check_align_T0_7(); gen_ldda_asi(insn); gen_movl_T0_reg(rd + 1); break; case 0x19: /* load signed byte alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif gen_ld_asi(insn, 1, 1); break; case 0x1a: /* load signed halfword alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #elif CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_ld_asi(insn, 2, 1); break; case 0x1d: /* ldstuba -- XXX: should be atomically */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif gen_ldstub_asi(insn); break; case 0x1f: /* swap reg with alt. memory. Also atomically */ #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #elif CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_movl_reg_T1(rd); gen_swap_asi(insn); break; #ifndef TARGET_SPARC64 case 0x30: /* ldc */ case 0x31: /* ldcsr */ case 0x33: /* lddc */ goto ncp_insn; #endif #endif #ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_ldst(ldsw); break; case 0x0b: /* V9 ldx */ gen_op_check_align_T0_7(); gen_op_ldst(ldx); break; case 0x18: /* V9 ldswa */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_ld_asi(insn, 4, 1); break; case 0x1b: /* V9 ldxa */ gen_op_check_align_T0_7(); gen_ld_asi(insn, 8, 0); break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; case 0x30: /* V9 ldfa */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_ldf_asi(insn, 4); goto skip_move; case 0x33: /* V9 lddfa */ gen_op_check_align_T0_3(); gen_ldf_asi(insn, 8); goto skip_move; case 0x3d: /* V9 prefetcha, no effect */ goto skip_move; case 0x32: /* V9 ldqfa */ goto nfpu_insn; #endif default: goto illegal_insn; } gen_movl_T1_reg(rd); #ifdef TARGET_SPARC64 skip_move: ; #endif } else if (xop >= 0x20 && xop < 0x24) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x20: /* load fpreg */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_ldst(ldf); gen_op_store_FT0_fpr(rd); break; case 0x21: /* load fsr */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_ldst(ldf); gen_op_ldfsr(); break; case 0x22: /* load quad fpreg */ goto nfpu_insn; case 0x23: /* load double fpreg */ gen_op_check_align_T0_7(); gen_op_ldst(lddf); gen_op_store_DT0_fpr(DFPREG(rd)); break; default: goto illegal_insn; } } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ xop == 0xe || xop == 0x1e) { gen_movl_reg_T1(rd); switch (xop) { case 0x4: #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_ldst(st); break; case 0x5: gen_op_ldst(stb); break; case 0x6: #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_op_ldst(sth); break; case 0x7: if (rd & 1) goto illegal_insn; gen_op_check_align_T0_7(); flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_ldst(std); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_st_asi(insn, 4); break; case 0x15: #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif gen_st_asi(insn, 1); break; case 0x16: #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_1(); #endif gen_st_asi(insn, 2); break; case 0x17: #ifndef TARGET_SPARC64 if (IS_IMM) goto illegal_insn; if (!supervisor(dc)) goto priv_insn; #endif if (rd & 1) goto illegal_insn; gen_op_check_align_T0_7(); flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_stda_asi(insn); break; #endif #ifdef TARGET_SPARC64 case 0x0e: /* V9 stx */ gen_op_check_align_T0_7(); gen_op_ldst(stx); break; case 0x1e: /* V9 stxa */ gen_op_check_align_T0_7(); gen_st_asi(insn, 8); break; #endif default: goto illegal_insn; } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x24: #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_load_fpr_FT0(rd); gen_op_ldst(stf); break; case 0x25: /* stfsr, V9 stxfsr */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_stfsr(); gen_op_ldst(stf); break; #if !defined(CONFIG_USER_ONLY) case 0x26: /* stdfq */ if (!supervisor(dc)) goto priv_insn; if (gen_trap_ifnofpu(dc)) goto jmp_insn; goto nfq_insn; #endif case 0x27: gen_op_check_align_T0_7(); gen_op_load_fpr_DT0(DFPREG(rd)); gen_op_ldst(stdf); break; default: goto illegal_insn; } } else if (xop > 0x33 && xop < 0x3f) { switch (xop) { #ifdef TARGET_SPARC64 case 0x34: /* V9 stfa */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif gen_op_load_fpr_FT0(rd); gen_stf_asi(insn, 4); break; case 0x37: /* V9 stdfa */ gen_op_check_align_T0_3(); gen_op_load_fpr_DT0(DFPREG(rd)); gen_stf_asi(insn, 8); break; case 0x3c: /* V9 casa */ #ifdef CONFIG_USER_ONLY gen_op_check_align_T0_3(); #endif flush_T2(dc); gen_movl_reg_T2(rd); gen_cas_asi(insn); gen_movl_T1_reg(rd); break; case 0x3e: /* V9 casxa */ gen_op_check_align_T0_7(); flush_T2(dc); gen_movl_reg_T2(rd); gen_casx_asi(insn); gen_movl_T1_reg(rd); break; case 0x36: /* V9 stqfa */ goto nfpu_insn; #else case 0x34: /* stc */ case 0x35: /* stcsr */ case 0x36: /* stdcq */ case 0x37: /* stdc */ goto ncp_insn; #endif default: goto illegal_insn; } } else goto illegal_insn; } break; } /* default case for non jump instructions */ if (dc->npc == DYNAMIC_PC) { dc->pc = DYNAMIC_PC; gen_op_next_insn(); } else if (dc->npc == JUMP_PC) { /* we can do a static jump */ gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]); dc->is_br = 1; } else { dc->pc = dc->npc; dc->npc = dc->npc + 4; } jmp_insn: return; illegal_insn: save_state(dc); gen_op_exception(TT_ILL_INSN); dc->is_br = 1; return; #if !defined(CONFIG_USER_ONLY) priv_insn: save_state(dc); gen_op_exception(TT_PRIV_INSN); dc->is_br = 1; return; #endif nfpu_insn: save_state(dc); gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); dc->is_br = 1; return; #if !defined(CONFIG_USER_ONLY) nfq_insn: save_state(dc); gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); dc->is_br = 1; return; #endif #ifndef TARGET_SPARC64 ncp_insn: save_state(dc); gen_op_exception(TT_NCP_INSN); dc->is_br = 1; return; #endif }


static int local_set_xattr(const char *path, FsCred *credp) { int err; if (credp->fc_uid != -1) { err = setxattr(path, "user.virtfs.uid", &credp->fc_uid, sizeof(uid_t), 0); if (err) { return err; } } if (credp->fc_gid != -1) { err = setxattr(path, "user.virtfs.gid", &credp->fc_gid, sizeof(gid_t), 0); if (err) { return err; } } if (credp->fc_mode != -1) { err = setxattr(path, "user.virtfs.mode", &credp->fc_mode, sizeof(mode_t), 0); if (err) { return err; } } if (credp->fc_rdev != -1) { err = setxattr(path, "user.virtfs.rdev", &credp->fc_rdev, sizeof(dev_t), 0); if (err) { return err; } } return 0; }